RISC-V: Add test for vec_duplicate + vnmsub.vv signed combine with GR2VR cost 0,...

Add asm dump check and run test for vec_duplicate + vnmsub.vv
combine to vnmsub.vx, with the GR2VR cost is 0, 2 and 15.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c: Add asm check
	for vnmsub.vx.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary.h: Add test
	helper macros.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary_data.h: Add test
	data for run test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-i16.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-i32.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-i64.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-i8.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c
index 29cab3a2e614f0efff04fe82b42a092e79d2d1ec..8879af34650d03ac177c80ba8cd32f9151d6053f 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c
@@ -26,3 +26,4 @@ TEST_TERNARY_VX_SIGNED_0(T)
 /* { dg-final { scan-assembler-times {vmacc.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vnmsac.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vmadd.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vnmsub.vx} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c
index 0e7c9675f5a35ddf464766abab2d208d76972e03..1b7b7401ada7cccc01c893b14d0e325c37a5eefe 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c
@@ -26,3 +26,4 @@ TEST_TERNARY_VX_SIGNED_0(T)
 /* { dg-final { scan-assembler-times {vmacc.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vnmsac.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vmadd.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vnmsub.vx} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c
index 1524e714200d8484244f0a7d4283ee9bdf470abe..00d8ef7d85beab9902dd00b15d1a4abf8f720f72 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c
@@ -29,3 +29,4 @@ TEST_TERNARY_VX_SIGNED_0(T)
 /* { dg-final { scan-assembler-times {vmacc.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vnmsac.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vmadd.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vnmsub.vx} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c
index 0967fc3980bd978e8b9c85b4fe84224efc4b7033..4480635033aa52833ca88734fa4aa2400bd48e56 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c
@@ -26,3 +26,4 @@ TEST_TERNARY_VX_SIGNED_0(T)
 /* { dg-final { scan-assembler-times {vmacc.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vnmsac.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vmadd.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vnmsub.vx} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c
index fd0098d052f219a728c85a528ff3470ba1f4e112..d02aaa347dff262b6b6889417b77bdabd038bf60 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c
@@ -26,3 +26,4 @@ TEST_TERNARY_VX_SIGNED_0(T)
 /* { dg-final { scan-assembler-not {vmacc.vx} } } */
 /* { dg-final { scan-assembler-not {vnmsac.vx} } } */
 /* { dg-final { scan-assembler-not {vmadd.vx} } } */
+/* { dg-final { scan-assembler-not {vnmsub.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c
index e73ef30ca0f87b17bb3480edffe3ce9ff3667512..5921fe66baef3ad27aae1fbbbadec155e9d80b6d 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c
@@ -26,3 +26,4 @@ TEST_TERNARY_VX_SIGNED_0(T)
 /* { dg-final { scan-assembler-not {vmacc.vx} } } */
 /* { dg-final { scan-assembler-not {vnmsac.vx} } } */
 /* { dg-final { scan-assembler-not {vmadd.vx} } } */
+/* { dg-final { scan-assembler-not {vnmsub.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c
index ab4c6c22722ca18ca66f34457013c4eb049e621b..3b5331914692ca4ec6632324dc4a41d862743fa3 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c
@@ -26,3 +26,4 @@ TEST_TERNARY_VX_SIGNED_0(T)
 /* { dg-final { scan-assembler-not {vmacc.vx} } } */
 /* { dg-final { scan-assembler-not {vnmsac.vx} } } */
 /* { dg-final { scan-assembler-not {vmadd.vx} } } */
+/* { dg-final { scan-assembler-not {vnmsub.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c
index cb9c25305ce1f204968419539dee7569212399f3..ca9fa4a30711519d4776c41a54b2ec42edef6605 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c
@@ -26,3 +26,4 @@ TEST_TERNARY_VX_SIGNED_0(T)
 /* { dg-final { scan-assembler-not {vmacc.vx} } } */
 /* { dg-final { scan-assembler-not {vnmsac.vx} } } */
 /* { dg-final { scan-assembler-not {vmadd.vx} } } */
+/* { dg-final { scan-assembler-not {vnmsub.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c
index 881917b95f4f9e48b85d10b8a1e9adff771dc126..573ae91bd1fe54032e6e073a29d7fd2edc3b5c90 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c
@@ -26,3 +26,4 @@ TEST_TERNARY_VX_SIGNED_0(T)
 /* { dg-final { scan-assembler-not {vmacc.vx} } } */
 /* { dg-final { scan-assembler-not {vnmsac.vx} } } */
 /* { dg-final { scan-assembler-not {vmadd.vx} } } */
+/* { dg-final { scan-assembler-not {vnmsub.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c
index e60e2321b3b3e0258ce9e32d48b14187545475c6..5fab6befc2392fd6be25260da7b855e7bd939f75 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c
@@ -26,3 +26,4 @@ TEST_TERNARY_VX_SIGNED_0(T)
 /* { dg-final { scan-assembler-not {vmacc.vx} } } */
 /* { dg-final { scan-assembler-not {vnmsac.vx} } } */
 /* { dg-final { scan-assembler-not {vmadd.vx} } } */
+/* { dg-final { scan-assembler-not {vnmsub.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c
index 3aade3c1f011740ce36c444aa1da30f0a7446162..5d67e47c4d9bc0a200fddedece4d0be33febb760 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c
@@ -26,3 +26,4 @@ TEST_TERNARY_VX_SIGNED_0(T)
 /* { dg-final { scan-assembler-not {vmacc.vx} } } */
 /* { dg-final { scan-assembler-not {vnmsac.vx} } } */
 /* { dg-final { scan-assembler-not {vmadd.vx} } } */
+/* { dg-final { scan-assembler-not {vnmsub.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c
index 3c7935d75f2972dfac9d975d8f79d0d23ddc7a9c..d889a841c4dce85ebf15fd406aa7fe70fa31da01 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c
@@ -26,3 +26,4 @@ TEST_TERNARY_VX_SIGNED_0(T)
 /* { dg-final { scan-assembler-not {vmacc.vx} } } */
 /* { dg-final { scan-assembler-not {vnmsac.vx} } } */
 /* { dg-final { scan-assembler-not {vmadd.vx} } } */
+/* { dg-final { scan-assembler-not {vnmsub.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary.h
index 06fde11fea8a5e71fb3f61e273b2b161323689d7..987aa7311d049d5e2e2f6843d47fe2f4ad9dc76d 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary.h
@@ -49,10 +49,12 @@ test_vx_ternary_##NAME##_##T##_case_1 (T * restrict vd, T * restrict vs2, \
   DEF_VX_TERNARY_CASE_0_WRAP(T, *, +, macc)                        \
   DEF_VX_TERNARY_CASE_1_WRAP(T, *, +, madd)                        \
   DEF_VX_TERNARY_CASE_0_WRAP(T, *, -, nmsac)                       \
+  DEF_VX_TERNARY_CASE_1_WRAP(T, *, -, nmsub)                       \
 
 #define TEST_TERNARY_VX_UNSIGNED_0(T)                              \
   DEF_VX_TERNARY_CASE_0_WRAP(T, *, +, macc)                        \
   DEF_VX_TERNARY_CASE_1_WRAP(T, *, +, madd)                        \
   DEF_VX_TERNARY_CASE_0_WRAP(T, *, -, nmsac)                       \
+  DEF_VX_TERNARY_CASE_1_WRAP(T, *, -, nmsub)                       \
 
 #endif

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary_data.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary_data.h
index 447a58cbace30bcbddeed4f001fb5ad739e251f0..08c71fe264ed895db5afdf5c0b979a9a52fbecd6 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary_data.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary_data.h
@@ -1110,4 +1110,372 @@ uint64_t TEST_TERNARY_DATA(uint64_t, madd)[][4][N] =
   },
 };
 
+int8_t TEST_TERNARY_DATA(int8_t, nmsub)[][4][N] =
+{
+  {
+    { 1 }, /* rs1 */
+    { /* vs2 */
+       1,  1,  1,  1,
+       2,  2,  2,  2,
+       0,  0,  0,  0,
+      -1, -1, -1, -1,
+    },
+    { /* vd */
+       0,  0,  0,  0,
+       1,  1,  1,  1,
+      -1, -1, -1, -1,
+      -2, -2, -2, -2,
+    },
+    {
+       1,  1,  1,  1,
+       1,  1,  1,  1,
+       1,  1,  1,  1,
+       1,  1,  1,  1,
+    },
+  },
+  {
+    { 127 }, /* rs1 */
+    { /* vs2 */
+       127,  127,  127,  127,
+         2,    2,    2,    2,
+         0,    0,    0,    0,
+      -128, -128, -128, -128,
+    },
+    { /* vd */
+       0,  0,  0,  0,
+       1,  1,  1,  1,
+      -8, -8, -8, -8,
+      -2, -2, -2, -2,
+    },
+    {
+       127,  127,  127,  127,
+      -125, -125, -125, -125,
+        -8,   -8,   -8,   -8,
+       126,  126,  126,  126,
+    },
+  },
+};
+
+int16_t TEST_TERNARY_DATA(int16_t, nmsub)[][4][N] =
+{
+  {
+    { 1 }, /* rs1 */
+    { /* vs2 */
+       1,  1,  1,  1,
+       2,  2,  2,  2,
+       0,  0,  0,  0,
+      -1, -1, -1, -1,
+    },
+    { /* vd */
+       0,  0,  0,  0,
+       1,  1,  1,  1,
+      -1, -1, -1, -1,
+      -2, -2, -2, -2,
+    },
+    {
+       1,  1,  1,  1,
+       1,  1,  1,  1,
+       1,  1,  1,  1,
+       1,  1,  1,  1,
+    },
+  },
+  {
+    { 32767 }, /* rs1 */
+    { /* vs2 */
+       32767,  32767,  32767,  32767,
+           2,      2,      2,      2,
+           0,      0,      0,      0,
+      -32768, -32768, -32768, -32768,
+    },
+    { /* vd */
+       0,  0,  0,  0,
+       1,  1,  1,  1,
+      -8, -8, -8, -8,
+      -2, -2, -2, -2,
+    },
+    {
+       32767,  32767,  32767,  32767,
+      -32765, -32765, -32765, -32765,
+          -8,     -8,     -8,     -8,
+       32766,  32766,  32766,  32766,
+    },
+  },
+};
+
+int32_t TEST_TERNARY_DATA(int32_t, nmsub)[][4][N] =
+{
+  {
+    { 1 }, /* rs1 */
+    { /* vs2 */
+       1,  1,  1,  1,
+       2,  2,  2,  2,
+       0,  0,  0,  0,
+      -1, -1, -1, -1,
+    },
+    { /* vd */
+       0,  0,  0,  0,
+       1,  1,  1,  1,
+      -1, -1, -1, -1,
+      -2, -2, -2, -2,
+    },
+    {
+       1,  1,  1,  1,
+       1,  1,  1,  1,
+       1,  1,  1,  1,
+       1,  1,  1,  1,
+    },
+  },
+  {
+    { 2147483647 }, /* rs1 */
+    { /* vs2 */
+       2147483647,  2147483647,  2147483647,  2147483647,
+                2,           2,           2,           2,
+                0,           0,           0,           0,
+      -2147483648, -2147483648, -2147483648, -2147483648,
+    },
+    { /* vd */
+       0,  0,  0,  0,
+       1,  1,  1,  1,
+      -8, -8, -8, -8,
+      -2, -2, -2, -2,
+    },
+    {
+       2147483647,  2147483647,  2147483647,  2147483647,
+      -2147483645, -2147483645, -2147483645, -2147483645,
+               -8,          -8,          -8,          -8,
+       2147483646,  2147483646,  2147483646,  2147483646,
+    },
+  },
+};
+
+int64_t TEST_TERNARY_DATA(int64_t, nmsub)[][4][N] =
+{
+  {
+    { 1 }, /* rs1 */
+    { /* vs2 */
+       1,  1,  1,  1,
+       2,  2,  2,  2,
+       0,  0,  0,  0,
+      -1, -1, -1, -1,
+    },
+    { /* vd */
+       0,  0,  0,  0,
+       1,  1,  1,  1,
+      -1, -1, -1, -1,
+      -2, -2, -2, -2,
+    },
+    {
+       1,  1,  1,  1,
+       1,  1,  1,  1,
+       1,  1,  1,  1,
+       1,  1,  1,  1,
+    },
+  },
+  {
+    { 9223372036854775807ull }, /* rs1 */
+    { /* vs2 */
+       9223372036854775807ull,  9223372036854775807ull,  9223372036854775807ull,  9223372036854775807ull,
+                            2,                       2,                       2,                       2,
+                            0,                       0,                       0,                       0,
+      -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull,
+    },
+    { /* vd */
+       0,  0,  0,  0,
+       1,  1,  1,  1,
+      -8, -8, -8, -8,
+      -2, -2, -2, -2,
+    },
+    {
+       9223372036854775807ull,  9223372036854775807ull,  9223372036854775807ull,  9223372036854775807ull,
+      -9223372036854775805ull, -9223372036854775805ull, -9223372036854775805ull, -9223372036854775805ull,
+                           -8,                      -8,                      -8,                      -8,
+       9223372036854775806ull,  9223372036854775806ull,  9223372036854775806ull,  9223372036854775806ull,
+    },
+  },
+};
+
+uint8_t TEST_TERNARY_DATA(uint8_t, nmsub)[][4][N] =
+{
+  {
+    { 1 }, /* rs1 */
+    { /* vs2 */
+       1,  1,  1,  1,
+       2,  2,  2,  2,
+       8,  8,  8,  8,
+       7,  7,  7,  7,
+    },
+    { /* vd */
+       0,  0,  0,  0,
+       1,  1,  1,  1,
+       1,  1,  1,  1,
+       2,  2,  2,  2,
+    },
+    {
+       1,  1,  1,  1,
+       1,  1,  1,  1,
+       7,  7,  7,  7,
+       5,  5,  5,  5,
+    },
+  },
+  {
+    { 128 }, /* rs1 */
+    { /* vs2 */
+       127,  127,  127,  127,
+       255,  255,  255,  255,
+       254,  254,  254,  254,
+       252,  252,  252,  252,
+    },
+    { /* vd */
+       0,  0,  0,  0,
+       1,  1,  1,  1,
+       8,  8,  8,  8,
+       2,  2,  2,  2,
+    },
+    {
+       127,  127,  127,  127,
+       127,  127,  127,  127,
+       254,  254,  254,  254,
+       252,  252,  252,  252,
+    },
+  },
+};
+
+uint16_t TEST_TERNARY_DATA(uint16_t, nmsub)[][4][N] =
+{
+  {
+    { 1 }, /* rs1 */
+    { /* vs2 */
+       1,  1,  1,  1,
+       2,  2,  2,  2,
+       8,  8,  8,  8,
+       7,  7,  7,  7,
+    },
+    { /* vd */
+       0,  0,  0,  0,
+       1,  1,  1,  1,
+       1,  1,  1,  1,
+       2,  2,  2,  2,
+    },
+    {
+       1,  1,  1,  1,
+       1,  1,  1,  1,
+       7,  7,  7,  7,
+       5,  5,  5,  5,
+    },
+  },
+  {
+    { 32768 }, /* rs1 */
+    { /* vs2 */
+       32767,  32767,  32767,  32767,
+       65535,  65535,  65535,  65535,
+       65534,  65534,  65534,  65534,
+       65532,  65532,  65532,  65532,
+    },
+    { /* vd */
+       0,  0,  0,  0,
+       1,  1,  1,  1,
+       8,  8,  8,  8,
+       2,  2,  2,  2,
+    },
+    {
+       32767,  32767,  32767,  32767,
+       32767,  32767,  32767,  32767,
+       65534,  65534,  65534,  65534,
+       65532,  65532,  65532,  65532,
+    },
+  },
+};
+
+uint32_t TEST_TERNARY_DATA(uint32_t, nmsub)[][4][N] =
+{
+  {
+    { 1 }, /* rs1 */
+    { /* vs2 */
+       1,  1,  1,  1,
+       2,  2,  2,  2,
+       8,  8,  8,  8,
+       7,  7,  7,  7,
+    },
+    { /* vd */
+       0,  0,  0,  0,
+       1,  1,  1,  1,
+       1,  1,  1,  1,
+       2,  2,  2,  2,
+    },
+    {
+       1,  1,  1,  1,
+       1,  1,  1,  1,
+       7,  7,  7,  7,
+       5,  5,  5,  5,
+    },
+  },
+  {
+    { 2147483648 }, /* rs1 */
+    { /* vs2 */
+       2147483647,  2147483647,  2147483647,  2147483647,
+       4294967295,  4294967295,  4294967295,  4294967295,
+       4294967294,  4294967294,  4294967294,  4294967294,
+       4294967292,  4294967292,  4294967292,  4294967292,
+    },
+    { /* vd */
+       0,  0,  0,  0,
+       1,  1,  1,  1,
+       8,  8,  8,  8,
+       2,  2,  2,  2,
+    },
+    {
+       2147483647,  2147483647,  2147483647,  2147483647,
+       2147483647,  2147483647,  2147483647,  2147483647,
+       4294967294,  4294967294,  4294967294,  4294967294,
+       4294967292,  4294967292,  4294967292,  4294967292,
+    },
+  },
+};
+
+uint64_t TEST_TERNARY_DATA(uint64_t, nmsub)[][4][N] =
+{
+  {
+    { 1 }, /* rs1 */
+    { /* vs2 */
+       1,  1,  1,  1,
+       2,  2,  2,  2,
+       8,  8,  8,  8,
+       7,  7,  7,  7,
+    },
+    { /* vd */
+       0,  0,  0,  0,
+       1,  1,  1,  1,
+       1,  1,  1,  1,
+       2,  2,  2,  2,
+    },
+    {
+       1,  1,  1,  1,
+       1,  1,  1,  1,
+       7,  7,  7,  7,
+       5,  5,  5,  5,
+    },
+  },
+  {
+    { 9223372036854775808ull }, /* rs1 */
+    { /* vs2 */
+        9223372036854775807ull,   9223372036854775807ull,   9223372036854775807ull,   9223372036854775807ull,
+       18446744073709551615ull,  18446744073709551615ull,  18446744073709551615ull,  18446744073709551615ull,
+       18446744073709551614ull,  18446744073709551614ull,  18446744073709551614ull,  18446744073709551614ull,
+       18446744073709551612ull,  18446744073709551612ull,  18446744073709551612ull,  18446744073709551612ull,
+    },
+    { /* vd */
+       0,  0,  0,  0,
+       1,  1,  1,  1,
+       8,  8,  8,  8,
+       2,  2,  2,  2,
+    },
+    {
+        9223372036854775807ull,   9223372036854775807ull,   9223372036854775807ull,   9223372036854775807ull,
+        9223372036854775807ull,   9223372036854775807ull,   9223372036854775807ull,   9223372036854775807ull,
+       18446744073709551614ull,  18446744073709551614ull,  18446744073709551614ull,  18446744073709551614ull,
+       18446744073709551612ull,  18446744073709551612ull,  18446744073709551612ull,  18446744073709551612ull,
+    },
+  },
+};
+
 #endif

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-i16.c
new file mode 100644 (file)
index 0000000..5d0c33a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-i16.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_ternary.h"
+#include "vx_ternary_data.h"
+
+#define T          int16_t
+#define NAME       nmsub
+#define TEST_DATA  TEST_TERNARY_DATA_WRAP(T, NAME)
+
+DEF_VX_TERNARY_CASE_1_WRAP(T, *, -, NAME)
+
+#define TEST_RUN(T, NAME, vd, vs2, rs1, n) \
+  RUN_VX_TERNARY_CASE_1_WRAP(T, NAME, vd, vs2, rs1, n)
+
+#include "vx_ternary_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-i32.c
new file mode 100644 (file)
index 0000000..e7cd272
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-i32.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_ternary.h"
+#include "vx_ternary_data.h"
+
+#define T          int32_t
+#define NAME       nmsub
+#define TEST_DATA  TEST_TERNARY_DATA_WRAP(T, NAME)
+
+DEF_VX_TERNARY_CASE_1_WRAP(T, *, -, NAME)
+
+#define TEST_RUN(T, NAME, vd, vs2, rs1, n) \
+  RUN_VX_TERNARY_CASE_1_WRAP(T, NAME, vd, vs2, rs1, n)
+
+#include "vx_ternary_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-i64.c
new file mode 100644 (file)
index 0000000..c038e5c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-i64.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_ternary.h"
+#include "vx_ternary_data.h"
+
+#define T          int64_t
+#define NAME       nmsub
+#define TEST_DATA  TEST_TERNARY_DATA_WRAP(T, NAME)
+
+DEF_VX_TERNARY_CASE_1_WRAP(T, *, -, NAME)
+
+#define TEST_RUN(T, NAME, vd, vs2, rs1, n) \
+  RUN_VX_TERNARY_CASE_1_WRAP(T, NAME, vd, vs2, rs1, n)
+
+#include "vx_ternary_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-i8.c
new file mode 100644 (file)
index 0000000..52325b7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-i8.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_ternary.h"
+#include "vx_ternary_data.h"
+
+#define T          int8_t
+#define NAME       nmsub
+#define TEST_DATA  TEST_TERNARY_DATA_WRAP(T, NAME)
+
+DEF_VX_TERNARY_CASE_1_WRAP(T, *, -, NAME)
+
+#define TEST_RUN(T, NAME, vd, vs2, rs1, n) \
+  RUN_VX_TERNARY_CASE_1_WRAP(T, NAME, vd, vs2, rs1, n)
+
+#include "vx_ternary_run.h"