clk: renesas: r9a09g056: Add support for PLLVDO, CRU clocks, and resets

Add support for the PLLVDO clock and its related CRU clocks and reset
entries in the R9A09G056 CPG driver. Introduce `CLK_PLLVDO` and associated
clocks like `CLK_PLLVDO_CRU0` and `CLK_PLLVDO_CRU1`, along with their
corresponding dividers.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251023210724.666476-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/r9a09g056-cpg.c b/drivers/clk/renesas/r9a09g056-cpg.c
index 70b73d4101351d0f9d3b71104a7091610517deb2..9c536f7706ff23e2b7b5569da3a988e82c04b19c 100644 (file)
--- a/drivers/clk/renesas/r9a09g056-cpg.c
+++ b/drivers/clk/renesas/r9a09g056-cpg.c
@@ -29,6 +29,7 @@ enum clk_ids {
        CLK_PLLCLN,
        CLK_PLLDTY,
        CLK_PLLCA55,
+       CLK_PLLVDO,
        CLK_PLLETH,
        CLK_PLLDSI,
        CLK_PLLGPU,
@@ -50,6 +51,8 @@ enum clk_ids {
        CLK_PLLDTY_ACPU_DIV4,
        CLK_PLLDTY_DIV8,
        CLK_PLLDTY_DIV16,
+       CLK_PLLVDO_CRU0,
+       CLK_PLLVDO_CRU1,
        CLK_PLLETH_DIV_250_FIX,
        CLK_PLLETH_DIV_125_FIX,
        CLK_CSDIV_PLLETH_GBE0,
@@ -75,6 +78,12 @@ static const struct clk_div_table dtable_1_8[] = {
        {0, 0},
 };
 
+static const struct clk_div_table dtable_2_4[] = {
+       {0, 2},
+       {1, 4},
+       {0, 0},
+};
+
 static const struct clk_div_table dtable_2_16[] = {
        {0, 2},
        {1, 4},
@@ -149,6 +158,7 @@ static const struct cpg_core_clk r9a09g056_core_clks[] __initconst = {
        DEF_FIXED(".pllcln", CLK_PLLCLN, CLK_QEXTAL, 200, 3),
        DEF_FIXED(".plldty", CLK_PLLDTY, CLK_QEXTAL, 200, 3),
        DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLLCA55),
+       DEF_FIXED(".pllvdo", CLK_PLLVDO, CLK_QEXTAL, 105, 2),
        DEF_FIXED(".plleth", CLK_PLLETH, CLK_QEXTAL, 125, 3),
        DEF_PLLDSI(".plldsi", CLK_PLLDSI, CLK_QEXTAL, PLLDSI),
        DEF_PLL(".pllgpu", CLK_PLLGPU, CLK_QEXTAL, PLLGPU),
@@ -174,6 +184,9 @@ static const struct cpg_core_clk r9a09g056_core_clks[] __initconst = {
        DEF_FIXED(".plldty_div8", CLK_PLLDTY_DIV8, CLK_PLLDTY, 1, 8),
        DEF_FIXED(".plldty_div16", CLK_PLLDTY_DIV16, CLK_PLLDTY, 1, 16),
 
+       DEF_DDIV(".pllvdo_cru0", CLK_PLLVDO_CRU0, CLK_PLLVDO, CDDIV3_DIVCTL3, dtable_2_4),
+       DEF_DDIV(".pllvdo_cru1", CLK_PLLVDO_CRU1, CLK_PLLVDO, CDDIV4_DIVCTL0, dtable_2_4),
+
        DEF_FIXED(".plleth_250_fix", CLK_PLLETH_DIV_250_FIX, CLK_PLLETH, 1, 4),
        DEF_FIXED(".plleth_125_fix", CLK_PLLETH_DIV_125_FIX, CLK_PLLETH_DIV_250_FIX, 1, 2),
        DEF_CSDIV(".plleth_gbe0", CLK_CSDIV_PLLETH_GBE0,
@@ -334,6 +347,18 @@ static const struct rzv2h_mod_clk r9a09g056_mod_clks[] __initconst = {
                                                BUS_MSTOP(8, BIT(6))),
        DEF_MOD("gbeth_1_aclk_i",               CLK_PLLDTY_DIV8, 12, 3, 6, 3,
                                                BUS_MSTOP(8, BIT(6))),
+       DEF_MOD("cru_0_aclk",                   CLK_PLLDTY_ACPU_DIV2, 13, 2, 6, 18,
+                                               BUS_MSTOP(9, BIT(4))),
+       DEF_MOD_NO_PM("cru_0_vclk",             CLK_PLLVDO_CRU0, 13, 3, 6, 19,
+                                               BUS_MSTOP(9, BIT(4))),
+       DEF_MOD("cru_0_pclk",                   CLK_PLLDTY_DIV16, 13, 4, 6, 20,
+                                               BUS_MSTOP(9, BIT(4))),
+       DEF_MOD("cru_1_aclk",                   CLK_PLLDTY_ACPU_DIV2, 13, 5, 6, 21,
+                                               BUS_MSTOP(9, BIT(5))),
+       DEF_MOD_NO_PM("cru_1_vclk",             CLK_PLLVDO_CRU1, 13, 6, 6, 22,
+                                               BUS_MSTOP(9, BIT(5))),
+       DEF_MOD("cru_1_pclk",                   CLK_PLLDTY_DIV16, 13, 7, 6, 23,
+                                               BUS_MSTOP(9, BIT(5))),
        DEF_MOD("dsi_0_pclk",                   CLK_PLLDTY_DIV16, 14, 8, 7, 8,
                                                BUS_MSTOP(9, BIT(14) | BIT(15))),
        DEF_MOD("dsi_0_aclk",                   CLK_PLLDTY_ACPU_DIV2, 14, 9, 7, 9,
@@ -396,6 +421,12 @@ static const struct rzv2h_reset r9a09g056_resets[] __initconst = {
        DEF_RST(10, 15, 5, 0),          /* USB2_0_PRESETN */
        DEF_RST(11, 0, 5, 1),           /* GBETH_0_ARESETN_I */
        DEF_RST(11, 1, 5, 2),           /* GBETH_1_ARESETN_I */
+       DEF_RST(12, 5, 5, 22),          /* CRU_0_PRESETN */
+       DEF_RST(12, 6, 5, 23),          /* CRU_0_ARESETN */
+       DEF_RST(12, 7, 5, 24),          /* CRU_0_S_RESETN */
+       DEF_RST(12, 8, 5, 25),          /* CRU_1_PRESETN */
+       DEF_RST(12, 9, 5, 26),          /* CRU_1_ARESETN */
+       DEF_RST(12, 10, 5, 27),         /* CRU_1_S_RESETN */
        DEF_RST(13, 7, 6, 8),           /* DSI_0_PRESETN */
        DEF_RST(13, 8, 6, 9),           /* DSI_0_ARESETN */
        DEF_RST(13, 12, 6, 13),         /* LCDC_0_RESET_N */