arm64: dts: qcom: sm8450: Use standalone ICE node for UFS

With the ICE driver now merged let's convert the ufs node to use the new
style.

Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20221209-dt-binding-ufs-v5-5-c9a58c0a53f5@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index 1c71c0a2cd81196942c01f1488168529e1e15e4f..b97998c684b053e984b88888be830e4486a7a66f 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -4120,9 +4120,7 @@
                ufs_mem_hc: ufshc@1d84000 {
                        compatible = "qcom,sm8450-ufshc", "qcom,ufshc",
                                     "jedec,ufs-2.0";
-                       reg = <0 0x01d84000 0 0x3000>,
-                             <0 0x01d88000 0 0x8000>;
-                       reg-names = "std", "ice";
+                       reg = <0 0x01d84000 0 0x3000>;
                        interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
                        phys = <&ufs_mem_phy_lanes>;
                        phy-names = "ufsphy";
@@ -4147,8 +4145,7 @@
                                "ref_clk",
                                "tx_lane0_sync_clk",
                                "rx_lane0_sync_clk",
-                               "rx_lane1_sync_clk",
-                               "ice_core_clk";
+                               "rx_lane1_sync_clk";
                        clocks =
                                <&gcc GCC_UFS_PHY_AXI_CLK>,
                                <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
@@ -4157,8 +4154,7 @@
                                <&rpmhcc RPMH_CXO_CLK>,
                                <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
                                <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
-                               <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>,
-                               <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
+                               <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
                        freq-table-hz =
                                <75000000 300000000>,
                                <0 0>,
@@ -4167,8 +4163,9 @@
                                <75000000 300000000>,
                                <0 0>,
                                <0 0>,
-                               <0 0>,
-                               <75000000 300000000>;
+                               <0 0>;
+                       qcom,ice = <&ice>;
+
                        status = "disabled";
                };
 
@@ -4198,6 +4195,13 @@
                        };
                };
 
+               ice: crypto@1d88000 {
+                       compatible = "qcom,sm8450-inline-crypto-engine",
+                                    "qcom,inline-crypto-engine";
+                       reg = <0 0x01d88000 0 0x8000>;
+                       clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
+               };
+
                cryptobam: dma-controller@1dc4000 {
                        compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
                        reg = <0 0x01dc4000 0 0x28000>;