drm/amd/display: update sequential pg logic DCN35

[WHY & HOW]
No check for HUBP/DPP power gating when DSC instance is still running. Avoid HUBP/DPP to
power gate when corresponding DSC block is still running in the power gating calculation.

Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Duncan Ma <duncan.ma@amd.com>
Signed-off-by: Yihan Zhu <Yihan.Zhu@amd.com>
Signed-off-by: Roman Li <roman.li@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
index d5f76cc69c73609e2cba52f1f50362673c374fca..8207fea4f99a96e2369e90b828d77c218fee705e 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
@@ -1032,8 +1032,13 @@ void dcn35_calc_blocks_to_gate(struct dc *dc, struct dc_state *context,
                if (pipe_ctx->plane_res.dpp || pipe_ctx->stream_res.opp)
                        update_state->pg_pipe_res_update[PG_MPCC][pipe_ctx->plane_res.mpcc_inst] = false;
 
-               if (pipe_ctx->stream_res.dsc)
+               if (pipe_ctx->stream_res.dsc) {
                        update_state->pg_pipe_res_update[PG_DSC][pipe_ctx->stream_res.dsc->inst] = false;
+                       if (dc->caps.sequential_ono) {
+                               update_state->pg_pipe_res_update[PG_HUBP][pipe_ctx->stream_res.dsc->inst] = false;
+                               update_state->pg_pipe_res_update[PG_DPP][pipe_ctx->stream_res.dsc->inst] = false;
+                       }
+               }
 
                if (pipe_ctx->stream_res.opp)
                        update_state->pg_pipe_res_update[PG_OPP][pipe_ctx->stream_res.opp->inst] = false;