arm64: dts: apple: t8012: Add cpufreq nodes

Add cpufreq nodes for Apple A10 SoC. There is a transparent hardware
big.LITTLE switcher in this SoC. Spoof E-core p-state frequencies such
that CPU capacity does not appear to change when switching between core
types.

Signed-off-by: Nick Chan <towinchenmi@gmail.com>
Reviewed-by: Neal Gompa <neal@gompa.dev>
Signed-off-by: Sven Peter <sven@svenpeter.dev>

diff --git a/arch/arm64/boot/dts/apple/t8012.dtsi b/arch/arm64/boot/dts/apple/t8012.dtsi
index 907ba127be79c8d177d6578999f0f6ce0559acdd..42df2f51ad7be4c4533e76d18e49a9a747b6b7a8 100644 (file)
--- a/arch/arm64/boot/dts/apple/t8012.dtsi
+++ b/arch/arm64/boot/dts/apple/t8012.dtsi
@@ -32,6 +32,8 @@
                        compatible = "apple,hurricane-zephyr";
                        reg = <0x0 0x10000>;
                        cpu-release-addr = <0 0>; /* To be filled by loader */
+                       operating-points-v2 = <&fusion_opp>;
+                       performance-domains = <&cpufreq>;
                        enable-method = "spin-table";
                        device_type = "cpu";
                };
@@ -40,11 +42,86 @@
                        compatible = "apple,hurricane-zephyr";
                        reg = <0x0 0x10001>;
                        cpu-release-addr = <0 0>; /* To be filled by loader */
+                       operating-points-v2 = <&fusion_opp>;
+                       performance-domains = <&cpufreq>;
                        enable-method = "spin-table";
                        device_type = "cpu";
                };
        };
 
+       fusion_opp: opp-table {
+               compatible = "operating-points-v2";
+
+               /*
+                * Apple Fusion Architecture: Hardware big.LITTLE switcher
+                * that use p-state transitions to switch between cores.
+                * Only one type of core can be active at a given time.
+                *
+                * The E-core frequencies are adjusted so performance scales
+                * linearly with reported clock speed.
+                */
+
+               opp01 {
+                       opp-hz = /bits/ 64 <172000000>; /* 300 MHz, E-core */
+                       opp-level = <1>;
+                       clock-latency-ns = <11000>;
+               };
+               opp02 {
+                       opp-hz = /bits/ 64 <230000000>; /* 396 MHz, E-core */
+                       opp-level = <2>;
+                       clock-latency-ns = <140000>;
+               };
+               opp03 {
+                       opp-hz = /bits/ 64 <425000000>; /* 732 MHz, E-core */
+                       opp-level = <3>;
+                       clock-latency-ns = <110000>;
+               };
+               opp04 {
+                       opp-hz = /bits/ 64 <637000000>; /* 1092 MHz, E-core */
+                       opp-level = <4>;
+                       clock-latency-ns = <130000>;
+               };
+               opp05 {
+                       opp-hz = /bits/ 64 <756000000>;
+                       opp-level = <5>;
+                       clock-latency-ns = <130000>;
+               };
+               opp06 {
+                       opp-hz = /bits/ 64 <1056000000>;
+                       opp-level = <6>;
+                       clock-latency-ns = <130000>;
+               };
+               opp07 {
+                       opp-hz = /bits/ 64 <1356000000>;
+                       opp-level = <7>;
+                       clock-latency-ns = <130000>;
+               };
+               opp08 {
+                       opp-hz = /bits/ 64 <1644000000>;
+                       opp-level = <8>;
+                       clock-latency-ns = <135000>;
+               };
+               opp09 {
+                       opp-hz = /bits/ 64 <1944000000>;
+                       opp-level = <9>;
+                       clock-latency-ns = <140000>;
+               };
+               opp10 {
+                       opp-hz = /bits/ 64 <2244000000>;
+                       opp-level = <10>;
+                       clock-latency-ns = <150000>;
+               };
+#if 0
+               /* Not available until CPU deep sleep is implemented */
+               opp11 {
+                       opp-hz = /bits/ 64 <2340000000>;
+                       opp-level = <11>;
+                       clock-latency-ns = <150000>;
+                       turbo-mode;
+               };
+#endif
+       };
+
        soc {
                compatible = "simple-bus";
                #address-cells = <2>;
@@ -52,6 +129,12 @@
                nonposted-mmio;
                ranges;
 
+               cpufreq: performance-controller@202f20000 {
+                       compatible = "apple,t8010-cluster-cpufreq", "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq";
+                       reg = <0x2 0x02f20000 0 0x1000>;
+                       #performance-domain-cells = <0>;
+               };
+
                serial0: serial@20a600000 {
                        compatible = "apple,s5l-uart";
                        reg = <0x2 0x0a600000 0x0 0x4000>;