static int airoha_dev_init(struct net_device *dev)
{
struct airoha_gdm_port *port = netdev_priv(dev);
- struct airoha_qdma *qdma = port->qdma;
- struct airoha_eth *eth = qdma->eth;
+ struct airoha_eth *eth = port->eth;
u32 fe_cpu_port;
u8 ppe_id;
+ /* QDMA0 is used for lan ports while QDMA1 is used for WAN ports */
+ port->qdma = ð->qdma[!airoha_is_lan_gdm_port(port)];
+ port->dev->irq = port->qdma->irq_banks[0].irq;
airoha_set_macaddr(port, dev->dev_addr);
switch (port->id) {
}
fallthrough;
default: {
- u8 qdma_id = qdma - ð->qdma[0];
+ u8 qdma_id = port->qdma - ð->qdma[0];
/* For PPE1 select cpu port according to the running QDMA. */
fe_cpu_port = qdma_id ? FE_PSE_PORT_CDM2 : FE_PSE_PORT_CDM1;
}
static int airoha_alloc_gdm_port(struct airoha_eth *eth,
- struct device_node *np, int index)
+ struct device_node *np)
{
const __be32 *id_ptr = of_get_property(np, "reg", NULL);
struct airoha_gdm_port *port;
- struct airoha_qdma *qdma;
struct net_device *dev;
int err, p;
u32 id;
return -ENOMEM;
}
- qdma = ð->qdma[index % AIROHA_MAX_NUM_QDMA];
dev->netdev_ops = &airoha_netdev_ops;
dev->ethtool_ops = &airoha_ethtool_ops;
dev->max_mtu = AIROHA_MAX_MTU;
dev->features |= dev->hw_features;
dev->vlan_features = dev->hw_features;
dev->dev.of_node = np;
- dev->irq = qdma->irq_banks[0].irq;
SET_NETDEV_DEV(dev, eth->dev);
/* reserve hw queues for HTB offloading */
port = netdev_priv(dev);
u64_stats_init(&port->stats.syncp);
spin_lock_init(&port->stats.lock);
- port->qdma = qdma;
+ port->eth = eth;
port->dev = dev;
port->id = id;
eth->ports[p] = port;
for (i = 0; i < ARRAY_SIZE(eth->qdma); i++)
airoha_qdma_start_napi(ð->qdma[i]);
- i = 0;
for_each_child_of_node(pdev->dev.of_node, np) {
if (!of_device_is_compatible(np, "airoha,eth-mac"))
continue;
if (!of_device_is_available(np))
continue;
- err = airoha_alloc_gdm_port(eth, np, i++);
+ err = airoha_alloc_gdm_port(eth, np);
if (err) {
of_node_put(np);
goto error_napi_stop;