]> git.ipfire.org Git - thirdparty/u-boot.git/commitdiff
arm: mach-k3: {am6/j7}*_hardware.h: Expose MCU R5 proc and device ids
authorBeleswar Padhi <b-padhi@ti.com>
Mon, 9 Jun 2025 08:14:26 +0000 (13:44 +0530)
committerTom Rini <trini@konsulko.com>
Wed, 18 Jun 2025 18:16:39 +0000 (12:16 -0600)
Currently the MCU R5 processor ids and device ids are only defined for
R5 SPL Stage. Expose these ids always so that A72 SPL can utilize this
information to shutdown MCU R5 Core 1 when booted in Split mode.

Signed-off-by: Beleswar Padhi <b-padhi@ti.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
arch/arm/mach-k3/include/mach/am62_hardware.h
arch/arm/mach-k3/include/mach/am62a_hardware.h
arch/arm/mach-k3/include/mach/am62p_hardware.h
arch/arm/mach-k3/include/mach/am64_hardware.h
arch/arm/mach-k3/include/mach/am6_hardware.h
arch/arm/mach-k3/include/mach/j721e_hardware.h
arch/arm/mach-k3/include/mach/j721s2_hardware.h
arch/arm/mach-k3/include/mach/j722s_hardware.h
arch/arm/mach-k3/include/mach/j784s4_hardware.h

index bcbc4821c82f5154ec4605fe6c09cff02f6f7c50..d44342d43d429b4861b12c752e34feaee4a9a69f 100644 (file)
@@ -158,8 +158,8 @@ static inline int k3_has_gpu(void)
 
 static const u32 put_device_ids[] = {};
 
-static const u32 put_core_ids[] = {};
-
 #endif
 
+static const u32 put_core_ids[] = {};
+
 #endif /* __ASM_ARCH_AM62_HARDWARE_H */
index cd61abe0185c98f7ba92e2fd8e9193d165e9f5f0..f3fd736f31b8444d84e95099441003c572843226 100644 (file)
@@ -90,8 +90,8 @@
 
 static const u32 put_device_ids[] = {};
 
-static const u32 put_core_ids[] = {};
-
 #endif
 
+static const u32 put_core_ids[] = {};
+
 #endif /* __ASM_ARCH_AM62A_HARDWARE_H */
index 95af5c5c547a4d22dd96e3cf66234a6b9139be35..a310b52b45dc5cb76c215c598deee287a2e8e3c6 100644 (file)
@@ -141,8 +141,8 @@ static inline int k3_get_a53_max_frequency(void)
 
 static const u32 put_device_ids[] = {};
 
-static const u32 put_core_ids[] = {};
-
 #endif
 
+static const u32 put_core_ids[] = {};
+
 #endif /* __ASM_ARCH_AM62P_HARDWARE_H */
index 44df887d5df8646c40206430f0f007471fc9e5fd..105b42986de57aea5da2dabdffb659e330266737 100644 (file)
 
 #define AM64X_DEV_RTI8                 127
 #define AM64X_DEV_RTI9                 128
-#define AM64X_DEV_R5FSS0_CORE0         121
-#define AM64X_DEV_R5FSS0_CORE1         122
 
 static const u32 put_device_ids[] = {
        AM64X_DEV_RTI9,
        AM64X_DEV_RTI8,
 };
 
+#endif
+
+#define AM64X_DEV_R5FSS0_CORE0         121
+#define AM64X_DEV_R5FSS0_CORE1         122
+
 static const u32 put_core_ids[] = {
        AM64X_DEV_R5FSS0_CORE1,
        AM64X_DEV_R5FSS0_CORE0, /* Handle CPU0 after CPU1 */
 };
 
-#endif
-
 #endif /* __ASM_ARCH_DRA8_HARDWARE_H */
index 9913964c46bdbf222f1ac112c2cc939c7c714335..8169584a37292b1bdef4df7dbd973ad02280840f 100644 (file)
 
 #define AM6_DEV_MCU_RTI0                       134
 #define AM6_DEV_MCU_RTI1                       135
-#define AM6_DEV_MCU_ARMSS0_CPU0                        159
-#define AM6_DEV_MCU_ARMSS0_CPU1                        245
 
 static const u32 put_device_ids[] = {
        AM6_DEV_MCU_RTI0,
        AM6_DEV_MCU_RTI1,
 };
 
+#endif
+
+#define AM6_DEV_MCU_ARMSS0_CPU0                        159
+#define AM6_DEV_MCU_ARMSS0_CPU1                        245
+
 static const u32 put_core_ids[] = {
        AM6_DEV_MCU_ARMSS0_CPU1,
        AM6_DEV_MCU_ARMSS0_CPU0,        /* Handle CPU0 after CPU1 */
 };
 
-#endif
-
 #endif /* __ASM_ARCH_AM6_HARDWARE_H */
index 2b5ec771e18bd7a5485864278890ceb8d2ab3a71..5bef309af0a4d1572eb58b127e30969dc034f3e8 100644 (file)
 
 #define J721E_DEV_MCU_RTI0                     262
 #define J721E_DEV_MCU_RTI1                     263
-#define J721E_DEV_MCU_ARMSS0_CPU0              250
-#define J721E_DEV_MCU_ARMSS0_CPU1              251
 
 static const u32 put_device_ids[] = {
        J721E_DEV_MCU_RTI0,
        J721E_DEV_MCU_RTI1,
 };
 
+#endif
+
+#define J721E_DEV_MCU_ARMSS0_CPU0              250
+#define J721E_DEV_MCU_ARMSS0_CPU1              251
+
 static const u32 put_core_ids[] = {
        J721E_DEV_MCU_ARMSS0_CPU1,
        J721E_DEV_MCU_ARMSS0_CPU0,      /* Handle CPU0 after CPU1 */
 };
 
-#endif
-
 #endif /* __ASM_ARCH_J721E_HARDWARE_H */
index 8daea82a77eedb02dc06c15855238baa48844e78..82f076a45e018519938e717c70ba5c089e189d98 100644 (file)
 
 #define J721S2_DEV_MCU_RTI0                    295
 #define J721S2_DEV_MCU_RTI1                    296
-#define J721S2_DEV_MCU_ARMSS0_CPU0             284
-#define J721S2_DEV_MCU_ARMSS0_CPU1             285
 
 static const u32 put_device_ids[] = {
        J721S2_DEV_MCU_RTI0,
        J721S2_DEV_MCU_RTI1,
 };
 
+#endif
+
+#define J721S2_DEV_MCU_ARMSS0_CPU0             284
+#define J721S2_DEV_MCU_ARMSS0_CPU1             285
+
 static const u32 put_core_ids[] = {
        J721S2_DEV_MCU_ARMSS0_CPU1,
        J721S2_DEV_MCU_ARMSS0_CPU0,     /* Handle CPU0 after CPU1 */
 };
 
-#endif
-
 #endif /* __ASM_ARCH_J721S2_HARDWARE_H */
index 8d0bec220684ac5aa315bd728e7b803660716e07..0c695134c2886a1c63a8746637a9f019f83d4317 100644 (file)
@@ -76,8 +76,8 @@
 
 static const u32 put_device_ids[] = {};
 
-static const u32 put_core_ids[] = {};
-
 #endif
 
+static const u32 put_core_ids[] = {};
+
 #endif /* __ASM_ARCH_J722S_HARDWARE_H */
index 0ffe238cdaef99e3889abf8016427f54ce69b6ac..29a894baed34bc4672b8f769f652b2d509ee911f 100644 (file)
 
 #define J784S4_DEV_MCU_RTI0                    367
 #define J784S4_DEV_MCU_RTI1                    368
-#define J784S4_DEV_MCU_ARMSS0_CPU0             346
-#define J784S4_DEV_MCU_ARMSS0_CPU1             347
 
 static const u32 put_device_ids[] = {
        J784S4_DEV_MCU_RTI0,
        J784S4_DEV_MCU_RTI1,
 };
 
+#endif
+
+#define J784S4_DEV_MCU_ARMSS0_CPU0             346
+#define J784S4_DEV_MCU_ARMSS0_CPU1             347
+
 static const u32 put_core_ids[] = {
        J784S4_DEV_MCU_ARMSS0_CPU1,
        J784S4_DEV_MCU_ARMSS0_CPU0,     /* Handle CPU0 after CPU1 */
 };
 
-#endif
-
 #endif /* __ASM_ARCH_J784S4_HARDWARE_H */