arm64: disable trapping of POR_EL0 to EL2

Allow EL0 or EL1 to access POR_EL0 without being trapped to EL2.

Signed-off-by: Joey Gouly <joey.gouly@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com>
Link: https://lore.kernel.org/r/20240822151113.1479789-5-joey.gouly@arm.com
[will: Rename Lset_poe_fgt to Lskip_pie_fgt to ease merge with for-next/misc]
Signed-off-by: Will Deacon <will@kernel.org>

diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el2_setup.h
index fd87c4b8f984039ceeba3d2da074f66293733a64..1173aba9c6a8349dab10d8dff3bf9b67be68da6b 100644 (file)
--- a/arch/arm64/include/asm/el2_setup.h
+++ b/arch/arm64/include/asm/el2_setup.h
@@ -185,12 +185,20 @@
 .Lset_pie_fgt_\@:
        mrs_s   x1, SYS_ID_AA64MMFR3_EL1
        ubfx    x1, x1, #ID_AA64MMFR3_EL1_S1PIE_SHIFT, #4
-       cbz     x1, .Lset_fgt_\@
+       cbz     x1, .Lskip_pie_fgt_\@
 
        /* Disable trapping of PIR_EL1 / PIRE0_EL1 */
        orr     x0, x0, #HFGxTR_EL2_nPIR_EL1
        orr     x0, x0, #HFGxTR_EL2_nPIRE0_EL1
 
+.Lskip_pie_fgt_\@:
+       mrs_s   x1, SYS_ID_AA64MMFR3_EL1
+       ubfx    x1, x1, #ID_AA64MMFR3_EL1_S1POE_SHIFT, #4
+       cbz     x1, .Lset_fgt_\@
+
+       /* Disable trapping of POR_EL0 */
+       orr     x0, x0, #HFGxTR_EL2_nPOR_EL0
+
 .Lset_fgt_\@:
        msr_s   SYS_HFGRTR_EL2, x0
        msr_s   SYS_HFGWTR_EL2, x0