pinctrl: renesas: rzg2l: Reorganize variable configuration macro

The `PIN_CFG_VARIABLE` macro did not indicate the capabilities of a pin
but served as a flag indicating that the pins of a port have different
capabilities.

To better reflect its purpose, move the `PIN_CFG_VARIABLE` macro beside
`RZG2L_SINGLE_PIN` and rename it to `RZG2L_VARIABLE_CFG`. Additionally,
introduce new macros for packing variable port configurations:
  - `RZG2L_GPIO_PORT_PACK_VARIABLE(n, a)`: Combines `RZG2L_VARIABLE_CFG`
    with `RZG2L_GPIO_PORT_PACK` to handle variable pin configurations
    for a packed port.
  - `RZG2L_GPIO_PORT_SPARSE_PACK_VARIABLE(m, a)`: Combines
    `RZG2L_VARIABLE_CFG` with `RZG2L_GPIO_PORT_SPARSE_PACK` to handle
    variable pin configurations for a sparse port.

Due to the above change the configuration macros have been reorganized
as follows:
- Shift the bit positions of `PIN_CFG_NOGPIO_INT`, `PIN_CFG_NOD`,
  `PIN_CFG_SMT`, `PIN_CFG_ELC`, and `PIN_CFG_IOLH_RZV2H` down by one
  to accommodate the removal of `PIN_CFG_VARIABLE`.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Link: https://lore.kernel.org/r/20240618174831.415583-5-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
index 37a99d33400dba5dc0c6bf0b0a391c73b6f96c0e..a04a4ce4a80e8e28ad9c34c18680976a5a0e1127 100644 (file)
--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
@@ -57,14 +57,14 @@
 #define PIN_CFG_IOLH_C                 BIT(13)
 #define PIN_CFG_SOFT_PS                        BIT(14)
 #define PIN_CFG_OEN                    BIT(15)
-#define PIN_CFG_VARIABLE               BIT(16)
-#define PIN_CFG_NOGPIO_INT             BIT(17)
-#define PIN_CFG_NOD                    BIT(18) /* N-ch Open Drain */
-#define PIN_CFG_SMT                    BIT(19) /* Schmitt-trigger input control */
-#define PIN_CFG_ELC                    BIT(20)
-#define PIN_CFG_IOLH_RZV2H             BIT(21)
+#define PIN_CFG_NOGPIO_INT             BIT(16)
+#define PIN_CFG_NOD                    BIT(17) /* N-ch Open Drain */
+#define PIN_CFG_SMT                    BIT(18) /* Schmitt-trigger input control */
+#define PIN_CFG_ELC                    BIT(19)
+#define PIN_CFG_IOLH_RZV2H             BIT(20)
 
 #define RZG2L_SINGLE_PIN               BIT_ULL(63)     /* Dedicated pin */
+#define RZG2L_VARIABLE_CFG             BIT_ULL(62)     /* Variable cfg for port pins */
 
 #define RZG2L_MPXED_COMMON_PIN_FUNCS(group) \
                                        (PIN_CFG_IOLH_##group | \
@@ -100,12 +100,17 @@
 #define RZG2L_GPIO_PORT_SPARSE_PACK(m, a, f)   (FIELD_PREP_CONST(PIN_CFG_PIN_MAP_MASK, (m)) | \
                                                 FIELD_PREP_CONST(PIN_CFG_PIN_REG_MASK, (a)) | \
                                                 FIELD_PREP_CONST(PIN_CFG_MASK, (f)))
+#define RZG2L_GPIO_PORT_SPARSE_PACK_VARIABLE(m, a)     \
+                                               (RZG2L_VARIABLE_CFG | \
+                                                RZG2L_GPIO_PORT_SPARSE_PACK(m, a, 0))
 
 /*
  * n indicates number of pins in the port, a is the register index
  * and f is pin configuration capabilities supported.
  */
 #define RZG2L_GPIO_PORT_PACK(n, a, f)  RZG2L_GPIO_PORT_SPARSE_PACK((1ULL << (n)) - 1, (a), (f))
+#define RZG2L_GPIO_PORT_PACK_VARIABLE(n, a)    (RZG2L_VARIABLE_CFG | \
+                                                RZG2L_GPIO_PORT_PACK(n, a, 0))
 
 #define RZG2L_SINGLE_PIN_INDEX_MASK    GENMASK_ULL(62, 56)
 #define RZG2L_SINGLE_PIN_BITS_MASK     GENMASK_ULL(55, 53)
@@ -371,7 +376,7 @@ static u64 rzg2l_pinctrl_get_variable_pin_cfg(struct rzg2l_pinctrl *pctrl,
 
                if (FIELD_GET(VARIABLE_PIN_CFG_PORT_MASK, cfg) == port &&
                    FIELD_GET(VARIABLE_PIN_CFG_PIN_MASK, cfg) == pin)
-                       return (pincfg & ~PIN_CFG_VARIABLE) | FIELD_GET(PIN_CFG_MASK, cfg);
+                       return (pincfg & ~RZG2L_VARIABLE_CFG) | FIELD_GET(PIN_CFG_MASK, cfg);
        }
 
        return 0;
@@ -1835,13 +1840,13 @@ static const u64 r9a07g043_gpio_configs[] = {
        RZG2L_GPIO_PORT_SPARSE_PACK(0x2, 0x06, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
                                    PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL |
                                    PIN_CFG_IEN | PIN_CFG_NOGPIO_INT),                  /* P19 */
-       RZG2L_GPIO_PORT_PACK(8, 0x07, PIN_CFG_VARIABLE),                                /* P20 */
+       RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x07),                                         /* P20 */
        RZG2L_GPIO_PORT_SPARSE_PACK(0x2, 0x08, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
                                    PIN_CFG_IEN | PIN_CFG_NOGPIO_INT),                  /* P21 */
        RZG2L_GPIO_PORT_PACK(4, 0x09, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
                             PIN_CFG_IEN | PIN_CFG_NOGPIO_INT),                         /* P22 */
-       RZG2L_GPIO_PORT_SPARSE_PACK(0x3e, 0x0a, PIN_CFG_VARIABLE),                      /* P23 */
-       RZG2L_GPIO_PORT_PACK(6, 0x0b, PIN_CFG_VARIABLE),                                /* P24 */
+       RZG2L_GPIO_PORT_SPARSE_PACK_VARIABLE(0x3e, 0x0a),                               /* P23 */
+       RZG2L_GPIO_PORT_PACK_VARIABLE(6, 0x0b),                                         /* P24 */
        RZG2L_GPIO_PORT_SPARSE_PACK(0x2, 0x0c, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_FILONOFF |
                                    PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL |
                                    PIN_CFG_NOGPIO_INT),                                /* P25 */
@@ -1913,7 +1918,7 @@ static const u64 r9a09g057_gpio_configs[] = {
                                      PIN_CFG_ELC),             /* P8 */
        RZG2L_GPIO_PORT_PACK(8, 0x29, RZV2H_MPXED_PIN_FUNCS),   /* P9 */
        RZG2L_GPIO_PORT_PACK(8, 0x2a, RZV2H_MPXED_PIN_FUNCS),   /* PA */
-       RZG2L_GPIO_PORT_PACK(6, 0x2b, PIN_CFG_VARIABLE),        /* PB */
+       RZG2L_GPIO_PORT_PACK_VARIABLE(6, 0x2b),                 /* PB */
 };
 
 static const struct {
@@ -2637,7 +2642,7 @@ static int rzg2l_pinctrl_register(struct rzg2l_pinctrl *pctrl)
                if (i && !(i % RZG2L_PINS_PER_PORT))
                        j++;
                pin_data[i] = pctrl->data->port_pin_configs[j];
-               if (pin_data[i] & PIN_CFG_VARIABLE)
+               if (pin_data[i] & RZG2L_VARIABLE_CFG)
                        pin_data[i] = rzg2l_pinctrl_get_variable_pin_cfg(pctrl,
                                                                         pin_data[i],
                                                                         j,