riscv: dts: starfive - Add hwrng node for JH7110 SoC

Add hardware rng controller node for StarFive JH7110 SoC.

Co-developed-by: Jenny Zhang <jenny.zhang@starfivetech.com>
Signed-off-by: Jenny Zhang <jenny.zhang@starfivetech.com>
Signed-off-by: Jia Jie Ho <jiajie.ho@starfivetech.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index 96fb88e702a6c5bff2f3f2d78356adda7a74d0a9..c2b401f4d8033d91882e3858f2039c8e21274046 100644 (file)
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -848,6 +848,16 @@
                        #dma-cells = <2>;
                };
 
+               rng: rng@1600c000 {
+                       compatible = "starfive,jh7110-trng";
+                       reg = <0x0 0x1600C000 0x0 0x4000>;
+                       clocks = <&stgcrg JH7110_STGCLK_SEC_AHB>,
+                                <&stgcrg JH7110_STGCLK_SEC_MISC_AHB>;
+                       clock-names = "hclk", "ahb";
+                       resets = <&stgcrg JH7110_STGRST_SEC_AHB>;
+                       interrupts = <30>;
+               };
+
                mmc0: mmc@16010000 {
                        compatible = "starfive,jh7110-mmc";
                        reg = <0x0 0x16010000 0x0 0x10000>;