sdhci_set_clock(mmc, mmc->clock);
if (mmc->clk_disable)
- sdhci_set_clock(mmc, 0);
+ return sdhci_set_clock(mmc, 0);
/* Set bus width */
ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
no_hispd_bit = true;
}
- if (!no_hispd_bit) {
- if (mmc->selected_mode == MMC_HS ||
- mmc->selected_mode == SD_HS ||
- mmc->selected_mode == MMC_DDR_52 ||
- mmc->selected_mode == MMC_HS_200 ||
- mmc->selected_mode == MMC_HS_400 ||
- mmc->selected_mode == UHS_SDR25 ||
- mmc->selected_mode == UHS_SDR50 ||
- mmc->selected_mode == UHS_SDR104 ||
- mmc->selected_mode == UHS_DDR50)
- ctrl |= SDHCI_CTRL_HISPD;
- else
- ctrl &= ~SDHCI_CTRL_HISPD;
+ sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
+
+ if (IS_SD(mmc) && SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
+ if (host->ops && host->ops->set_control_reg)
+ host->ops->set_control_reg(host);
}
sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
reg |= SDHCI_CTRL_VDD_180;
sdhci_writew(host, reg, SDHCI_HOST_CONTROL2);
+ /*
+ * 5ms delay is required as per SD3.0 spec while switching
+ * voltage to 1.8v
+ */
+ mdelay(5);
}
if (mmc->selected_mode > SD_HS &&