]> git.ipfire.org Git - thirdparty/kernel/stable.git/commitdiff
drm/amdgpu: Simplify amdgpu_lockup_timeout usage.
authorAndrey Grodzovsky <andrey.grodzovsky@amd.com>
Wed, 13 Dec 2017 19:36:53 +0000 (14:36 -0500)
committerAlex Deucher <alexander.deucher@amd.com>
Fri, 15 Dec 2017 22:15:00 +0000 (17:15 -0500)
With introduction of amdgpu_gpu_recovery we don't need any more
to rely on amdgpu_lockup_timeout == 0 for disabling GPU reset.

Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c
drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c

index 3f63f5ca4fa7809284a42dbbf5a09b1c33d08033..79869827985f76cfc9d9ebd08896b973b8dc5930 100644 (file)
@@ -1229,6 +1229,11 @@ static void amdgpu_check_arguments(struct amdgpu_device *adev)
                         amdgpu_vram_page_split);
                amdgpu_vram_page_split = 1024;
        }
+
+       if (amdgpu_lockup_timeout == 0) {
+               dev_warn(adev->dev, "lockup_timeout msut be > 0, adjusting to 10000\n");
+               amdgpu_lockup_timeout = 10000;
+       }
 }
 
 /**
@@ -2827,7 +2832,7 @@ bool amdgpu_need_backup(struct amdgpu_device *adev)
        if (adev->flags & AMD_IS_APU)
                return false;
 
-       return amdgpu_lockup_timeout > 0 ? true : false;
+       return amdgpu_gpu_recovery;
 }
 
 static int amdgpu_recover_vram_from_shadow(struct amdgpu_device *adev,
index b734cd668ff14b3ef7d528d9f7b6d334805b062c..1fc5499cb5fd954951cadec648b42ac9a6137588 100644 (file)
@@ -90,7 +90,7 @@ int amdgpu_disp_priority = 0;
 int amdgpu_hw_i2c = 0;
 int amdgpu_pcie_gen2 = -1;
 int amdgpu_msi = -1;
-int amdgpu_lockup_timeout = 0;
+int amdgpu_lockup_timeout = 10000;
 int amdgpu_dpm = -1;
 int amdgpu_fw_load_type = -1;
 int amdgpu_aspm = -1;
@@ -166,7 +166,7 @@ module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444);
 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
 module_param_named(msi, amdgpu_msi, int, 0444);
 
-MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default 0 = disable)");
+MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms > 0 (default 10000)");
 module_param_named(lockup_timeout, amdgpu_lockup_timeout, int, 0444);
 
 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
index d3ce121495429251953fc4a3d58f1a27e9d1d60c..da1510f65ee073f7bd228026942644d64b49aa58 100644 (file)
@@ -410,7 +410,6 @@ int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
 int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring,
                                  unsigned num_hw_submission)
 {
-       long timeout;
        int r;
 
        /* Check that num_hw_submission is a power of two */
@@ -434,20 +433,9 @@ int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring,
 
        /* No need to setup the GPU scheduler for KIQ ring */
        if (ring->funcs->type != AMDGPU_RING_TYPE_KIQ) {
-               timeout = msecs_to_jiffies(amdgpu_lockup_timeout);
-               if (timeout == 0) {
-                       /*
-                        * FIXME:
-                        * Delayed workqueue cannot use it directly,
-                        * so the scheduler will not use delayed workqueue if
-                        * MAX_SCHEDULE_TIMEOUT is set.
-                        * Currently keep it simple and silly.
-                        */
-                       timeout = MAX_SCHEDULE_TIMEOUT;
-               }
                r = drm_sched_init(&ring->sched, &amdgpu_sched_ops,
                                   num_hw_submission, amdgpu_job_hang_limit,
-                                  timeout, ring->name);
+                                  msecs_to_jiffies(amdgpu_lockup_timeout), ring->name);
                if (r) {
                        DRM_ERROR("Failed to create scheduler on ring %s.\n",
                                  ring->name);
index 7ade56d59c2773d79a9394d5744d95174fba668e..43e74ec93147aafc314c27f6739fa760354ae027 100644 (file)
@@ -277,7 +277,7 @@ static int xgpu_ai_mailbox_rcv_irq(struct amdgpu_device *adev,
        int r;
 
        /* trigger gpu-reset by hypervisor only if TDR disbaled */
-       if (amdgpu_lockup_timeout == 0) {
+       if (!amdgpu_gpu_recovery) {
                /* see what event we get */
                r = xgpu_ai_mailbox_rcv_msg(adev, IDH_FLR_NOTIFICATION);
 
index e05823d86cfb2fc41bc76173ca87b0bb32d63601..da7c261d5d876b66ce37be78d954003ea27ee1a2 100644 (file)
@@ -545,7 +545,7 @@ static int xgpu_vi_mailbox_rcv_irq(struct amdgpu_device *adev,
        int r;
 
        /* trigger gpu-reset by hypervisor only if TDR disbaled */
-       if (amdgpu_lockup_timeout == 0) {
+       if (!amdgpu_gpu_recovery) {
                /* see what event we get */
                r = xgpu_vi_mailbox_rcv_msg(adev, IDH_FLR_NOTIFICATION);