MIPS: Convert ICACHE_REFILLS_WORKAROUND_WAR into a config option

Use a new config option to enable I-cache refill workaround and remove
define from different war.h files.

Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 04a413d52b26afb97da22ff67c45be45e5394e68..5df92ae935d4368d757784bc2106490c5a4979d3 100644 (file)
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -568,6 +568,7 @@ config MIPS_MALTA
        select SYS_SUPPORTS_VPE_LOADER
        select SYS_SUPPORTS_ZBOOT
        select USE_OF
+       select WAR_ICACHE_REFILLS
        select ZONE_DMA32 if 64BIT
        help
          This enables support for the MIPS Technologies Malta evaluation
@@ -756,6 +757,7 @@ config SGI_IP32
        select SYS_HAS_CPU_NEVADA
        select SYS_SUPPORTS_64BIT_KERNEL
        select SYS_SUPPORTS_BIG_ENDIAN
+       select WAR_ICACHE_REFILLS
        help
          If you want this kernel to run on SGI O2 workstation, say Y here.
 
@@ -2666,6 +2668,13 @@ config WAR_R4600_V2_HIT_CACHEOP
 config WAR_TX49XX_ICACHE_INDEX_INV
        bool
 
+# The RM7000 processors and the E9000 cores have a bug (though PMC-Sierra
+# opposes it being called that) where invalid instructions in the same
+# I-cache line worth of instructions being fetched may case spurious
+# exceptions.
+config WAR_ICACHE_REFILLS
+       bool
+
 #
 # - Highmem only makes sense for the 32-bit kernel.
 # - The current highmem code will only work properly on physically indexed

diff --git a/arch/mips/include/asm/mach-cavium-octeon/war.h b/arch/mips/include/asm/mach-cavium-octeon/war.h
index 1cb30485dc94b08a28d2fc7d75375bd537df7b1e..1061917152c678ad73e45a2fc1c28ba15ac50953 100644 (file)
--- a/arch/mips/include/asm/mach-cavium-octeon/war.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/war.h
@@ -11,7 +11,6 @@
 
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
-#define ICACHE_REFILLS_WORKAROUND_WAR  0
 #define R10000_LLSC_WAR                        0
 #define MIPS34K_MISSED_ITLB_WAR                0
 

diff --git a/arch/mips/include/asm/mach-generic/war.h b/arch/mips/include/asm/mach-generic/war.h
index 79530836cc79325fea6a647dfb93c476b1e61f22..966f40aedf169e80e69c10a625edc88cb6059e92 100644 (file)
--- a/arch/mips/include/asm/mach-generic/war.h
+++ b/arch/mips/include/asm/mach-generic/war.h
@@ -10,7 +10,6 @@
 
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
-#define ICACHE_REFILLS_WORKAROUND_WAR  0
 #define R10000_LLSC_WAR                        0
 #define MIPS34K_MISSED_ITLB_WAR                0
 

diff --git a/arch/mips/include/asm/mach-ip22/war.h b/arch/mips/include/asm/mach-ip22/war.h
index 35286ba3ec5779f5409410c60c0239f3bafeda8f..99f6531e5b9ba82982ced81e8bbfbb65bb6ed1f3 100644 (file)
--- a/arch/mips/include/asm/mach-ip22/war.h
+++ b/arch/mips/include/asm/mach-ip22/war.h
@@ -10,7 +10,6 @@
 
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
-#define ICACHE_REFILLS_WORKAROUND_WAR  0
 #define R10000_LLSC_WAR                        0
 #define MIPS34K_MISSED_ITLB_WAR                0
 

diff --git a/arch/mips/include/asm/mach-ip27/war.h b/arch/mips/include/asm/mach-ip27/war.h
index a18293c16ade6c3cf35946b716279ca5b707a0ef..d8dfa7258bea218e1b9153d6fcb85b03af4acd38 100644 (file)
--- a/arch/mips/include/asm/mach-ip27/war.h
+++ b/arch/mips/include/asm/mach-ip27/war.h
@@ -10,7 +10,6 @@
 
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
-#define ICACHE_REFILLS_WORKAROUND_WAR  0
 #define R10000_LLSC_WAR                        1
 #define MIPS34K_MISSED_ITLB_WAR                0
 

diff --git a/arch/mips/include/asm/mach-ip28/war.h b/arch/mips/include/asm/mach-ip28/war.h
index 1a6092e5c7b381631b99562bfa6a6c07ff14dadb..f252df761ec878de269f30bee0782b08e2fdeaac 100644 (file)
--- a/arch/mips/include/asm/mach-ip28/war.h
+++ b/arch/mips/include/asm/mach-ip28/war.h
@@ -10,7 +10,6 @@
 
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
-#define ICACHE_REFILLS_WORKAROUND_WAR  0
 #define R10000_LLSC_WAR                        1
 #define MIPS34K_MISSED_ITLB_WAR                0
 

diff --git a/arch/mips/include/asm/mach-ip30/war.h b/arch/mips/include/asm/mach-ip30/war.h
index 031c7b9c52362b0fab248c4ba950c844667227bc..58ff9ca345b748a9fa80848c75f499388924d1b5 100644 (file)
--- a/arch/mips/include/asm/mach-ip30/war.h
+++ b/arch/mips/include/asm/mach-ip30/war.h
@@ -7,7 +7,6 @@
 
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
-#define ICACHE_REFILLS_WORKAROUND_WAR  0
 #ifdef CONFIG_CPU_R10000
 #define R10000_LLSC_WAR                        1
 #else

diff --git a/arch/mips/include/asm/mach-ip32/war.h b/arch/mips/include/asm/mach-ip32/war.h
index 25552158fa3a199bed7930c3610a3c91940c61e0..ca3efe457ae035098ddabfbc257be4010f542410 100644 (file)
--- a/arch/mips/include/asm/mach-ip32/war.h
+++ b/arch/mips/include/asm/mach-ip32/war.h
@@ -10,7 +10,6 @@
 
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
-#define ICACHE_REFILLS_WORKAROUND_WAR  1
 #define R10000_LLSC_WAR                        0
 #define MIPS34K_MISSED_ITLB_WAR                0
 

diff --git a/arch/mips/include/asm/mach-malta/war.h b/arch/mips/include/asm/mach-malta/war.h
index 9b0803537bcef998a612832aa0c25286c250747e..b7827eb09375c399b9929c363db00f7f69d6a7d9 100644 (file)
--- a/arch/mips/include/asm/mach-malta/war.h
+++ b/arch/mips/include/asm/mach-malta/war.h
@@ -10,7 +10,6 @@
 
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
-#define ICACHE_REFILLS_WORKAROUND_WAR  1
 #define R10000_LLSC_WAR                        0
 #define MIPS34K_MISSED_ITLB_WAR                0
 

diff --git a/arch/mips/include/asm/mach-rc32434/war.h b/arch/mips/include/asm/mach-rc32434/war.h
index 924b51b9a3401c4c1037870addac00f29d724af8..b7827eb09375c399b9929c363db00f7f69d6a7d9 100644 (file)
--- a/arch/mips/include/asm/mach-rc32434/war.h
+++ b/arch/mips/include/asm/mach-rc32434/war.h
@@ -10,7 +10,6 @@
 
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
-#define ICACHE_REFILLS_WORKAROUND_WAR  0
 #define R10000_LLSC_WAR                        0
 #define MIPS34K_MISSED_ITLB_WAR                0
 

diff --git a/arch/mips/include/asm/mach-rm/war.h b/arch/mips/include/asm/mach-rm/war.h
index 0536972b24c88c35bdf906a990e1853dffa45067..fe04d059dd0cee9b6e223ac1e84c332b551f715e 100644 (file)
--- a/arch/mips/include/asm/mach-rm/war.h
+++ b/arch/mips/include/asm/mach-rm/war.h
@@ -10,7 +10,6 @@
 
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
-#define ICACHE_REFILLS_WORKAROUND_WAR  0
 #define R10000_LLSC_WAR                        0
 #define MIPS34K_MISSED_ITLB_WAR                0
 

diff --git a/arch/mips/include/asm/mach-sibyte/war.h b/arch/mips/include/asm/mach-sibyte/war.h
index 9e006fdcf38a396e04bed9e2a350c58d6427ab8b..7c376f6eee9bb3fbcc97a4aa4eb8a3d96bb656ea 100644 (file)
--- a/arch/mips/include/asm/mach-sibyte/war.h
+++ b/arch/mips/include/asm/mach-sibyte/war.h
@@ -24,7 +24,6 @@ extern int sb1250_m3_workaround_needed(void);
 
 #endif
 
-#define ICACHE_REFILLS_WORKAROUND_WAR  0
 #define R10000_LLSC_WAR                        0
 #define MIPS34K_MISSED_ITLB_WAR                0
 

diff --git a/arch/mips/include/asm/mach-tx49xx/war.h b/arch/mips/include/asm/mach-tx49xx/war.h
index 9293c5f9ffb2de35155c7ec9ebb668d43a7db30d..5768889c20a71f89486cb5b96883fe716d520ad3 100644 (file)
--- a/arch/mips/include/asm/mach-tx49xx/war.h
+++ b/arch/mips/include/asm/mach-tx49xx/war.h
@@ -10,7 +10,6 @@
 
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
-#define ICACHE_REFILLS_WORKAROUND_WAR  0
 #define R10000_LLSC_WAR                        0
 #define MIPS34K_MISSED_ITLB_WAR                0
 

diff --git a/arch/mips/include/asm/war.h b/arch/mips/include/asm/war.h
index 7a69641de57b594bee89f32bd610fcf28af6eff4..a0942821d67dc2ea5278ac891ded08ba9e130b3d 100644 (file)
--- a/arch/mips/include/asm/war.h
+++ b/arch/mips/include/asm/war.h
@@ -93,16 +93,6 @@
 #error Check setting of SIBYTE_1956_WAR for your platform
 #endif
 
-/*
- * The RM7000 processors and the E9000 cores have a bug (though PMC-Sierra
- * opposes it being called that) where invalid instructions in the same
- * I-cache line worth of instructions being fetched may case spurious
- * exceptions.
- */
-#ifndef ICACHE_REFILLS_WORKAROUND_WAR
-#error Check setting of ICACHE_REFILLS_WORKAROUND_WAR for your platform
-#endif
-
 /*
  * On the R10000 up to version 2.6 (not sure about 2.7) there is a bug that
  * may cause ll / sc and lld / scd sequences to execute non-atomically.

diff --git a/arch/mips/kernel/signal.c b/arch/mips/kernel/signal.c
index a0262729cd4c388b1085864e5f2e28c7f6c14773..f44265025281c4a5c7ef0b8d2a829ed639541a7d 100644 (file)
--- a/arch/mips/kernel/signal.c
+++ b/arch/mips/kernel/signal.c
@@ -545,6 +545,12 @@ int restore_sigcontext(struct pt_regs *regs, struct sigcontext __user *sc)
        return err ?: protected_restore_fp_context(sc);
 }
 
+#ifdef CONFIG_WAR_ICACHE_REFILLS
+#define SIGMASK                ~(cpu_icache_line_size()-1)
+#else
+#define SIGMASK                ALMASK
+#endif
+
 void __user *get_sigframe(struct ksignal *ksig, struct pt_regs *regs,
                          size_t frame_size)
 {
@@ -565,7 +571,7 @@ void __user *get_sigframe(struct ksignal *ksig, struct pt_regs *regs,
 
        sp = sigsp(sp, ksig);
 
-       return (void __user *)((sp - frame_size) & (ICACHE_REFILLS_WORKAROUND_WAR ? ~(cpu_icache_line_size()-1) : ALMASK));
+       return (void __user *)((sp - frame_size) & SIGMASK);
 }
 
 /*