]> git.ipfire.org Git - thirdparty/gcc.git/commitdiff
rs6000: Make all shift instructions one type
authorSegher Boessenkool <segher@kernel.crashing.org>
Fri, 23 May 2014 16:41:20 +0000 (18:41 +0200)
committerSegher Boessenkool <segher@gcc.gnu.org>
Fri, 23 May 2014 16:41:20 +0000 (18:41 +0200)
This uses the attributes "var_shift" and "dot" to specify the differences:

var_shift_rotate    -> shift var_shift=yes
delayed_compare     -> shift var_shift=no  dot=yes
var_delayed_compare -> shift var_shift=yes dot=yes

From-SVN: r210870

26 files changed:
gcc/ChangeLog
gcc/config/rs6000/40x.md
gcc/config/rs6000/440.md
gcc/config/rs6000/476.md
gcc/config/rs6000/601.md
gcc/config/rs6000/603.md
gcc/config/rs6000/6xx.md
gcc/config/rs6000/7450.md
gcc/config/rs6000/7xx.md
gcc/config/rs6000/8540.md
gcc/config/rs6000/cell.md
gcc/config/rs6000/e300c2c3.md
gcc/config/rs6000/e500mc.md
gcc/config/rs6000/e500mc64.md
gcc/config/rs6000/e5500.md
gcc/config/rs6000/e6500.md
gcc/config/rs6000/mpc.md
gcc/config/rs6000/power4.md
gcc/config/rs6000/power5.md
gcc/config/rs6000/power6.md
gcc/config/rs6000/power7.md
gcc/config/rs6000/power8.md
gcc/config/rs6000/rs6000.c
gcc/config/rs6000/rs6000.md
gcc/config/rs6000/rs64.md
gcc/config/rs6000/titan.md

index 84d9817827c6982d0d22247e7ef7924b975ce505..dba8ed8f1684dedb73f7b3315055c6086393e036 100644 (file)
@@ -1,3 +1,68 @@
+2014-05-23  Segher Boessenkool  <segher@kernel.crashing.org>
+
+       * config/rs6000/rs6000.md (type): Delete "var_shift_rotate",
+       "delayed_compare", "var_delayed_compare".
+       (var_shift): New attribute.
+       (cell_micro): Adjust.
+       (*andsi3_internal2_mc, *andsi3_internal3_mc, *andsi3_internal4,
+       *andsi3_internal5_mc, *extzvsi_internal1, *extzvsi_internal2,
+       rotlsi3, *rotlsi3_64, *rotlsi3_internal2, *rotlsi3_internal3,
+       *rotlsi3_internal4, *rotlsi3_internal5, *rotlsi3_internal6,
+       *rotlsi3_internal8le, *rotlsi3_internal8be, *rotlsi3_internal9le,
+       *rotlsi3_internal9be, *rotlsi3_internal10le, *rotlsi3_internal10be,
+       *rotlsi3_internal11le, *rotlsi3_internal11be, *rotlsi3_internal12le,
+       *rotlsi3_internal12be, ashlsi3, *ashlsi3_64, lshrsi3, *lshrsi3_64,
+       *lshiftrt_internal2le, *lshiftrt_internal2be, *lshiftrt_internal3le,
+       *lshiftrt_internal3be, *lshiftrt_internal5le, *lshiftrt_internal5be,
+       *lshiftrt_internal5le, *lshiftrt_internal5be, ashrsi3, *ashrsi3_64,
+       rotldi3, *rotldi3_internal2, *rotldi3_internal3, *rotldi3_internal4,
+       *rotldi3_internal5, *rotldi3_internal6, *rotldi3_internal7le,
+       *rotldi3_internal7be, *rotldi3_internal8le, *rotldi3_internal8be,
+       *rotldi3_internal9le, *rotldi3_internal9be, *rotldi3_internal10le,
+       *rotldi3_internal10be, *rotldi3_internal11le, *rotldi3_internal11be,
+       *rotldi3_internal12le, *rotldi3_internal12be, *rotldi3_internal13le,
+       *rotldi3_internal13be, *rotldi3_internal14le, *rotldi3_internal14be,
+       *rotldi3_internal15le, *rotldi3_internal15be, *ashldi3_internal1,
+       *ashldi3_internal2, *ashldi3_internal3, *lshrdi3_internal1,
+       *lshrdi3_internal2, *lshrdi3_internal3, *ashrdi3_internal1,
+       *ashrdi3_internal2, *ashrdi3_internal3, *anddi3_internal2_mc,
+       *anddi3_internal3_mc, as well as 11 anonymous define_insns): Adjust.
+       * config/rs6000/rs6000.c (rs6000_adjust_cost, is_cracked_insn,
+       insn_must_be_first_in_group, insn_must_be_last_in_group): Adjust.
+
+       * config/rs6000/40x.md (ppc403-integer, ppc403-compare): Adjust.
+       * config/rs6000/440.md (ppc440-integer): Adjust.
+       * config/rs6000/476.md (ppc476-simple-integer, ppc476-compare):
+       Adjust.
+       * config/rs6000/601.md (ppc601-integer, ppc601-compare): Adjust.
+       * config/rs6000/603.md (ppc603-integer, ppc603-compare): Adjust.
+       * config/rs6000/6xx.md (ppc604-integer, ppc604-compare): Adjust.
+       * config/rs6000/7450.md (ppc7450-integer, ppc7450-compare):
+       Adjust.
+       * config/rs6000/7xx.md (ppc750-integer, ppc750-compare): Adjust.
+       * config/rs6000/8540.md (ppc8540_su): Adjust.
+       * config/rs6000/cell.md (cell-integer, cell-fast-cmp,
+       cell-cmp-microcoded): Adjust.
+       * config/rs6000/e300c2c3.md (ppce300c3_cmp): Adjust.
+       * config/rs6000/e500mc.md (e500mc_su): Adjust.
+       * config/rs6000/e500mc64.md (e500mc64_su, e500mc64_su2,
+       e500mc64_delayed): Adjust.
+       * config/rs6000/e5500.md (e5500_sfx, e5500_delayed): Adjust.
+       * config/rs6000/e6500.md (e6500_sfx, e6500_delayed): Adjust.
+       * config/rs6000/mpc.md (mpccore-integer, mpccore-compare): Adjust.
+       * config/rs6000/power4.md (power4-integer, power4-compare):
+       Adjust.
+       * config/rs6000/power5.md (power5-integer, power5-compare):
+       Adjust.
+       * config/rs6000/power6.md (power6-shift, power6-var-rotate,
+       power6-delayed-compare, power6-var-delayed-compare): Adjust.
+       * config/rs6000/power7.md (power7-integer, power7-compare):
+       Adjust.
+       * config/rs6000/power8.md (power8-1cyc, power8-compare): Adjust.
+       Adjust comment.
+       * config/rs6000/rs64.md (rs64a-integer, rs64a-compare): Adjust.
+       * config/rs6000/titan.md (titan_fxu_shift_and_rotate): Adjust.
+
 2014-05-23  Segher Boessenkool  <segher@kernel.crashing.org>
 
        * config/rs6000/rs6000.md (type): Delete "idiv", "ldiv".  Add
index 8ddccbacde4c8fe8df5ddfdf7e72e5903b011fa9..30ac01df0512081463695ee3cea0d5cd606672d9 100644 (file)
@@ -36,8 +36,9 @@
   "iu_40x")
 
 (define_insn_reservation "ppc403-integer" 1
-  (and (eq_attr "type" "integer,insert,shift,trap,\
-                        var_shift_rotate,cntlz,exts,isel")
+  (and (ior (eq_attr "type" "integer,insert,trap,cntlz,exts,isel")
+           (and (eq_attr "type" "shift")
+                (eq_attr "dot" "no")))
        (eq_attr "cpu" "ppc403,ppc405"))
   "iu_40x")
 
@@ -52,8 +53,9 @@
   "iu_40x,iu_40x,iu_40x")
 
 (define_insn_reservation "ppc403-compare" 3
-  (and (eq_attr "type" "cmp,fast_compare,compare,delayed_compare,\
-                        var_delayed_compare")
+  (and (ior (eq_attr "type" "cmp,fast_compare,compare")
+           (and (eq_attr "type" "shift")
+                (eq_attr "dot" "yes")))
        (eq_attr "cpu" "ppc403,ppc405"))
   "iu_40x,nothing,bpu_40x")
 
index e6c28a7060ef7c1b61a5e0922b703a2edb28dd96..3a36ffb38cd0ff8f246ae3cc88cb7a063113cc93 100644 (file)
@@ -53,8 +53,7 @@
   "ppc440_issue,ppc440_l_pipe")
 
 (define_insn_reservation "ppc440-integer" 1
-  (and (eq_attr "type" "integer,insert,shift,\
-                        trap,var_shift_rotate,cntlz,exts,isel")
+  (and (eq_attr "type" "integer,insert,shift,trap,cntlz,exts,isel")
        (eq_attr "cpu" "ppc440"))
   "ppc440_issue,ppc440_i_pipe|ppc440_j_pipe")
 
index 5acd6682a1da6b51af9dabdd46dbee2e224f4928..41cd247b591d3a9c9b28a890e376bb434a053a1c 100644 (file)
@@ -63,7 +63,9 @@
    ppc476_lj_pipe")
 
 (define_insn_reservation "ppc476-simple-integer" 1
-  (and (eq_attr "type" "integer,insert,var_shift_rotate,exts,shift")
+  (and (ior (eq_attr "type" "integer,insert,exts")
+           (and (eq_attr "type" "shift")
+                (eq_attr "dot" "no")))
        (eq_attr "cpu" "ppc476"))
   "ppc476_issue,\
    ppc476_i_pipe|ppc476_lj_pipe")
    ppc476_i_pipe")
 
 (define_insn_reservation "ppc476-compare" 4
-  (and (eq_attr "type" "compare,delayed_compare,fast_compare,mfcr,mfcrf,\
-                        mtcr,mfjmpr,mtjmpr,var_delayed_compare")
+  (and (ior (eq_attr "type" "compare,fast_compare,mfcr,mfcrf,\
+                             mtcr,mfjmpr,mtjmpr")
+           (and (eq_attr "type" "shift")
+                (eq_attr "dot" "yes")))
        (eq_attr "cpu" "ppc476"))
   "ppc476_issue,\
    ppc476_i_pipe")
index 85892c88006b5069a84b1f545fc99bdcb35b0659..f6eca7dc2e00b1270652976bbae2dc513ee84b1a 100644 (file)
@@ -45,8 +45,9 @@
   "iu_ppc601+fpu_ppc601")
 
 (define_insn_reservation "ppc601-integer" 1
-  (and (eq_attr "type" "integer,insert,shift,\
-                        trap,var_shift_rotate,cntlz,exts,isel")
+  (and (ior (eq_attr "type" "integer,insert,trap,cntlz,exts,isel")
+           (and (eq_attr "type" "shift")
+                (eq_attr "dot" "no")))
        (eq_attr "cpu" "ppc601"))
   "iu_ppc601")
 
@@ -73,8 +74,9 @@
 ; compare executes on integer unit, but feeds insns which
 ; execute on the branch unit.
 (define_insn_reservation "ppc601-compare" 3
-  (and (eq_attr "type" "cmp,compare,delayed_compare,\
-                        var_delayed_compare")
+  (and (ior (eq_attr "type" "cmp,compare")
+           (and (eq_attr "type" "shift")
+                (eq_attr "dot" "yes")))
        (eq_attr "cpu" "ppc601"))
   "iu_ppc601,nothing,bpu_ppc601")
 
index 5f38741af19fe57ea2a854f1391b561d28ad3202..f64f4287c1b9f05191202e1d7a1cbd914ba827ad 100644 (file)
@@ -58,8 +58,9 @@
   "lsu_603")
 
 (define_insn_reservation "ppc603-integer" 1
-  (and (eq_attr "type" "integer,insert,shift,trap,\
-                        var_shift_rotate,cntlz,exts,isel")
+  (and (ior (eq_attr "type" "integer,insert,trap,cntlz,exts,isel")
+           (and (eq_attr "type" "shift")
+                (eq_attr "dot" "no")))
        (eq_attr "cpu" "ppc603"))
   "iu_603")
 
@@ -92,8 +93,9 @@
   "iu_603*37")
 
 (define_insn_reservation "ppc603-compare" 3
-  (and (eq_attr "type" "cmp,fast_compare,compare,delayed_compare,\
-                        var_delayed_compare")
+  (and (ior (eq_attr "type" "cmp,fast_compare,compare")
+           (and (eq_attr "type" "shift")
+                (eq_attr "dot" "yes")))
        (eq_attr "cpu" "ppc603"))
   "iu_603,nothing,bpu_603")
 
index 3ff4caf2b01d45d5a243e13369ff093756c84576..6d4ccb7c0d8225c80914cd5e15c713d2d70b97ab 100644 (file)
@@ -73,8 +73,9 @@
   "lsu_6xx")
   
 (define_insn_reservation "ppc604-integer" 1
-  (and (eq_attr "type" "integer,insert,shift,trap,\
-                        var_shift_rotate,cntlz,exts,isel")
+  (and (ior (eq_attr "type" "integer,insert,trap,cntlz,exts,isel")
+           (and (eq_attr "type" "shift")
+                (eq_attr "dot" "no")))
        (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
   "iu1_6xx|iu2_6xx")
 
   "mciu_6xx*36")
 
 (define_insn_reservation "ppc604-compare" 3
-  (and (eq_attr "type" "cmp,fast_compare,compare,delayed_compare,\
-                        var_delayed_compare")
+  (and (ior (eq_attr "type" "cmp,fast_compare,compare")
+           (and (eq_attr "type" "shift")
+                (eq_attr "dot" "yes")))
        (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
   "(iu1_6xx|iu2_6xx)")
 
index 3333fd9b0ad12d358b19cc192e9634af23ef7be2..39815e96d76b22ea73ff1267130cfd544d52c1cc 100644 (file)
@@ -73,8 +73,9 @@
   "ppc7450_du,lsu_7450")
 
 (define_insn_reservation "ppc7450-integer" 1
-  (and (eq_attr "type" "integer,insert,shift,\
-                        trap,var_shift_rotate,cntlz,exts,isel")
+  (and (ior (eq_attr "type" "integer,insert,trap,cntlz,exts,isel")
+           (and (eq_attr "type" "shift")
+                (eq_attr "dot" "no")))
        (eq_attr "cpu" "ppc7450"))
   "ppc7450_du,iu1_7450|iu2_7450|iu3_7450")
 
   "ppc7450_du,mciu_7450*23")
 
 (define_insn_reservation "ppc7450-compare" 2
-  (and (eq_attr "type" "cmp,fast_compare,compare,delayed_compare,\
-                        var_delayed_compare")
+  (and (ior (eq_attr "type" "cmp,fast_compare,compare")
+           (and (eq_attr "type" "shift")
+                (eq_attr "dot" "yes")))
        (eq_attr "cpu" "ppc7450"))
   "ppc7450_du,(iu1_7450|iu2_7450|iu3_7450)")
 
index 67f3d11c1fda2b77735f0c75d8a9df3401979690..f9a9fb88e59189937225f5b55303ce80f240b6b4 100644 (file)
@@ -61,8 +61,9 @@
   "ppc750_du,lsu_7xx")
 
 (define_insn_reservation "ppc750-integer" 1
-  (and (eq_attr "type" "integer,insert,shift,\
-                        trap,var_shift_rotate,cntlz,exts,isel")
+  (and (ior (eq_attr "type" "integer,insert,trap,cntlz,exts,isel")
+           (and (eq_attr "type" "shift")
+                (eq_attr "dot" "no")))
        (eq_attr "cpu" "ppc750,ppc7400"))
   "ppc750_du,iu1_7xx|iu2_7xx")
 
   "ppc750_du,iu1_7xx*19")
 
 (define_insn_reservation "ppc750-compare" 2
-  (and (eq_attr "type" "cmp,fast_compare,compare,delayed_compare,\
-                        var_delayed_compare")
+  (and (ior (eq_attr "type" "cmp,fast_compare,compare")
+           (and (eq_attr "type" "shift")
+                (eq_attr "dot" "yes")))
        (eq_attr "cpu" "ppc750,ppc7400"))
   "ppc750_du,(iu1_7xx|iu2_7xx)")
 
index 578cf8ea979f38910170e9e1a70ceb9a5afbebf3..fccddfe9a4e7fbf433c49dcfa400ddeefc3284cb 100644 (file)
@@ -84,9 +84,8 @@
 
 ;; Simple SU insns
 (define_insn_reservation "ppc8540_su" 1
-  (and (eq_attr "type" "integer,insert,cmp,compare,\
-                        delayed_compare,var_delayed_compare,fast_compare,\
-                        shift,trap,var_shift_rotate,cntlz,exts,isel")
+  (and (eq_attr "type" "integer,insert,cmp,compare,fast_compare,\
+                        shift,trap,cntlz,exts,isel")
        (eq_attr "cpu" "ppc8540,ppc8548"))
   "ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire")
 
index 1bf308eec3d82fc0f188759b4cf3894a9fad31c2..923524d72339b31fae416f6fe6cde12219ab968a 100644 (file)
 
 ;; Integer latency is 2 cycles
 (define_insn_reservation "cell-integer" 2
-  (and (ior (eq_attr "type" "integer,shift,trap,\
-                            var_shift_rotate,cntlz,exts,isel")
+  (and (ior (eq_attr "type" "integer,trap,cntlz,exts,isel")
+           (and (eq_attr "type" "shift")
+                (eq_attr "dot" "no"))
            (and (eq_attr "type" "insert")
                 (eq_attr "size" "64")))
        (eq_attr "cpu" "cell"))
 
 ;; add, addo, sub, subo, alter cr0, rldcli, rlwinm 
 (define_insn_reservation "cell-fast-cmp" 2
-  (and (and (eq_attr "type" "fast_compare,delayed_compare,compare,\
-                           var_delayed_compare")
-            (eq_attr "cpu" "cell"))
-        (eq_attr "cell_micro" "not"))
+  (and (ior (eq_attr "type" "fast_compare,compare")
+           (and (eq_attr "type" "shift")
+                (eq_attr "dot" "yes")))
+       (eq_attr "cpu" "cell")
+       (eq_attr "cell_micro" "not"))
   "slot01,fxu_cell")
 
 (define_insn_reservation "cell-cmp-microcoded" 9
-  (and (and (eq_attr "type" "fast_compare,delayed_compare,compare,\
-                           var_delayed_compare")
-            (eq_attr "cpu" "cell"))
-        (eq_attr "cell_micro" "always"))
+  (and (ior (eq_attr "type" "fast_compare,compare")
+           (and (eq_attr "type" "shift")
+                (eq_attr "dot" "yes")))
+       (eq_attr "cpu" "cell")
+       (eq_attr "cell_micro" "always"))
   "slot0+slot1,fxu_cell,fxu_cell*7")
 
 ;; mulld
index 2abdfdb8163a0db8154073c35784ac91326b3d73..26a449d4a05b37a34258d5a737576ac2e302c1b5 100644 (file)
@@ -83,7 +83,9 @@
 
 ;; Compares can be executed either one of the IU or SRU
 (define_insn_reservation "ppce300c3_cmp" 1
-  (and (eq_attr "type" "cmp,compare,delayed_compare,fast_compare")
+  (and (ior (eq_attr "type" "cmp,compare,fast_compare")
+           (and (eq_attr "type" "shift")
+                (eq_attr "dot" "yes")))
        (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
   "ppce300c3_decode,ppce300c3_issue+(ppce300c3_iu_stage0|ppce300c3_sru_stage0) \
         +ppce300c3_retire")
index 580c30d13695cac5abf2211fd25ad9068fb0262b..834e0d2ff69a89a8c2cff06038f7843a71c205ae 100644 (file)
@@ -70,9 +70,8 @@
 
 ;; Simple SU insns.
 (define_insn_reservation "e500mc_su" 1
-  (and (eq_attr "type" "integer,insert,cmp,compare,\
-                        delayed_compare,var_delayed_compare,fast_compare,\
-                        shift,trap,var_shift_rotate,cntlz,exts,isel")
+  (and (eq_attr "type" "integer,insert,cmp,compare,fast_compare,\
+                        shift,trap,cntlz,exts,isel")
        (eq_attr "cpu" "ppce500mc"))
   "e500mc_decode,e500mc_issue+e500mc_su_stage0+e500mc_retire")
 
index 8844113f32a708cdb21ef2124ea2a436cb758c39..026d016223c89180b6550b81c7f58e76037ba2eb 100644 (file)
 
 ;; Simple SU insns.
 (define_insn_reservation "e500mc64_su" 1
-  (and (eq_attr "type" "integer,insert,delayed_compare,\
-       shift,cntlz,exts")
+  (and (ior (eq_attr "type" "integer,insert,cntlz,exts")
+           (and (eq_attr "type" "shift")
+                (eq_attr "dot" "no")
+                (eq_attr "var_shift" "no")))
        (eq_attr "cpu" "ppce500mc64"))
   "e500mc64_decode,e500mc64_issue+e500mc64_su_stage0+e500mc64_retire")
 
 (define_insn_reservation "e500mc64_su2" 2
-  (and (eq_attr "type" "cmp,compare,delayed_compare,fast_compare,trap")
+  (and (ior (eq_attr "type" "cmp,compare,fast_compare,trap")
+           (and (eq_attr "type" "shift")
+                (eq_attr "dot" "yes")
+                (eq_attr "var_shift" "no")))
        (eq_attr "cpu" "ppce500mc64"))
   "e500mc64_decode,e500mc64_issue+e500mc64_su_stage0,e500mc64_retire")
 
 (define_insn_reservation "e500mc64_delayed" 2
-  (and (eq_attr "type" "var_shift_rotate,var_delayed_compare")
+  (and (eq_attr "type" "shift")
+       (eq_attr "var_shift" "yes")
        (eq_attr "cpu" "ppce500mc64"))
   "e500mc64_decode,e500mc64_issue+e500mc64_su_stage0,e500mc64_retire")
 
index 6b257d6578bfb523ebd1dd7958ee996840f77a56..edd0ef5006859f768ec69186ebc9c9e0e931fc1c 100644 (file)
@@ -56,8 +56,9 @@
 
 ;; SFX.
 (define_insn_reservation "e5500_sfx" 1
-  (and (eq_attr "type" "integer,insert,delayed_compare,\
-       shift,cntlz,exts")
+  (and (ior (eq_attr "type" "integer,insert,cntlz,exts")
+           (and (eq_attr "type" "shift")
+                (eq_attr "var_shift" "no")))
        (eq_attr "cpu" "ppce5500"))
   "e5500_decode,e5500_sfx")
 
@@ -67,7 +68,8 @@
   "e5500_decode,e5500_sfx")
 
 (define_insn_reservation "e5500_delayed" 2
-  (and (eq_attr "type" "var_shift_rotate,var_delayed_compare")
+  (and (eq_attr "type" "shift")
+       (eq_attr "var_shift" "yes")
        (eq_attr "cpu" "ppce5500"))
   "e5500_decode,e5500_sfx*2")
 
index 52565d9727eed38f348330097b76a00ef08b0e91..609d5641a3786cd33c04f50e7e3242f8ac6eed3d 100644 (file)
@@ -59,8 +59,9 @@
 
 ;; SFX.
 (define_insn_reservation "e6500_sfx" 1
-  (and (eq_attr "type" "integer,insert,delayed_compare,\
-       shift,cntlz,exts")
+  (and (ior (eq_attr "type" "integer,insert,cntlz,exts")
+           (and (eq_attr "type" "shift")
+                (eq_attr "var_shift" "no")))
        (eq_attr "cpu" "ppce6500"))
   "e6500_decode,e6500_sfx")
 
@@ -70,7 +71,8 @@
   "e6500_decode,e6500_sfx")
 
 (define_insn_reservation "e6500_delayed" 2
-  (and (eq_attr "type" "var_shift_rotate,var_delayed_compare")
+  (and (eq_attr "type" "shift")
+       (eq_attr "var_shift" "yes")
        (eq_attr "cpu" "ppce6500"))
   "e6500_decode,e6500_sfx*2")
 
index 7fe889c4be86485b82e903eeeffe106793bdc1c7..f83c752eef78836176b279f433e709394b42f95f 100644 (file)
@@ -41,8 +41,9 @@
   "lsu_mpc")
 
 (define_insn_reservation "mpccore-integer" 1
-  (and (eq_attr "type" "integer,insert,shift,trap,\
-                        var_shift_rotate,cntlz,exts,isel")
+  (and (ior (eq_attr "type" "integer,insert,trap,cntlz,exts,isel")
+           (and (eq_attr "type" "shift")
+                (eq_attr "dot" "no")))
        (eq_attr "cpu" "mpccore"))
   "iu_mpc")
 
@@ -68,8 +69,9 @@
   "mciu_mpc*6")
 
 (define_insn_reservation "mpccore-compare" 3
-  (and (eq_attr "type" "cmp,fast_compare,compare,delayed_compare,\
-                        var_delayed_compare")
+  (and (ior (eq_attr "type" "cmp,fast_compare,compare")
+           (and (eq_attr "type" "shift")
+                (eq_attr "dot" "yes")))
        (eq_attr "cpu" "mpccore"))
   "iu_mpc,nothing,bpu_mpc")
 
index 73eac1fd2fc94aa7ec2c87ff5107fc0b8db2b31c..6a1c108843e60fda99e51e9e0c820a7be5b0c6b7 100644 (file)
 
 ; Integer latency is 2 cycles
 (define_insn_reservation "power4-integer" 2
-  (and (ior (eq_attr "type" "integer,shift,trap,\
-                            var_shift_rotate,cntlz,exts,isel")
+  (and (ior (eq_attr "type" "integer,trap,cntlz,exts,isel")
+           (and (eq_attr "type" "shift")
+                (eq_attr "dot" "no"))
            (and (eq_attr "type" "insert")
                 (eq_attr "size" "64")))
        (eq_attr "cpu" "power4"))
   "iq_power4")
 
 (define_insn_reservation "power4-compare" 2
-  (and (eq_attr "type" "compare,delayed_compare,var_delayed_compare")
+  (and (ior (eq_attr "type" "compare")
+           (and (eq_attr "type" "shift")
+                (eq_attr "dot" "yes")))
        (eq_attr "cpu" "power4"))
   "(du1_power4+du2_power4|du2_power4+du3_power4|du3_power4+du4_power4),\
    ((iu1_power4,iu2_power4)\
index 8aa477a1c15e72b22ea91edaa0a32e18dd385ed6..4ebb6cf28d3bd121b4fbd9dd27647ea4aa568f67 100644 (file)
 
 ; Integer latency is 2 cycles
 (define_insn_reservation "power5-integer" 2
-  (and (ior (eq_attr "type" "integer,shift,trap,\
-                           var_shift_rotate,cntlz,exts,isel,popcnt")
+  (and (ior (eq_attr "type" "integer,trap,cntlz,exts,isel,popcnt")
+           (and (eq_attr "type" "shift")
+                (eq_attr "dot" "no"))
            (and (eq_attr "type" "insert")
                 (eq_attr "size" "64")))
        (eq_attr "cpu" "power5"))
   "iq_power5")
 
 (define_insn_reservation "power5-compare" 2
-  (and (eq_attr "type" "compare,delayed_compare,var_delayed_compare")
+  (and (ior (eq_attr "type" "compare")
+           (and (eq_attr "type" "shift")
+                (eq_attr "dot" "yes")))
        (eq_attr "cpu" "power5"))
   "du1_power5+du2_power5,iu1_power5,iu2_power5")
 
index 26e17f962ea2b872278a685bf3a5e1476ac201a9..b659645a76dfad571327970e94df9ce310b1a5c3 100644 (file)
 
 (define_insn_reservation "power6-shift" 1
   (and (eq_attr "type" "shift")
+       (eq_attr "var_shift" "no")
+       (eq_attr "dot" "no")
        (eq_attr "cpu" "power6"))
   "FXU_power6")
 
   "store_data_bypass_p")
 
 (define_insn_reservation "power6-var-rotate" 4
-  (and (eq_attr "type" "var_shift_rotate")
+  (and (eq_attr "type" "shift")
+       (eq_attr "var_shift" "yes")
+       (eq_attr "dot" "no")
        (eq_attr "cpu" "power6"))
   "FXU_power6")
 
   "store_data_bypass_p")
 
 (define_insn_reservation "power6-delayed-compare" 2 ; N/A
-  (and (eq_attr "type" "delayed_compare")
+  (and (eq_attr "type" "shift")
+       (eq_attr "var_shift" "no")
+       (eq_attr "dot" "yes")
        (eq_attr "cpu" "power6"))
   "FXU_power6")
 
 (define_insn_reservation "power6-var-delayed-compare" 4
-  (and (eq_attr "type" "var_delayed_compare")
+  (and (eq_attr "type" "shift")
+       (eq_attr "var_shift" "yes")
+       (eq_attr "dot" "yes")
        (eq_attr "cpu" "power6"))
   "FXU_power6")
 
index 5527829b84f946b23b6fbe4385d9e3a7f4032ac1..f4bd0b8c23fc1fd1f0c0d76bdacaec940d8fc7e0 100644 (file)
 
 ; FX Unit
 (define_insn_reservation "power7-integer" 1
-  (and (eq_attr "type" "integer,insert,shift,trap,\
-                        var_shift_rotate,exts,isel,popcnt")
+  (and (ior (eq_attr "type" "integer,insert,trap,exts,isel,popcnt")
+           (and (eq_attr "type" "shift")
+                (eq_attr "dot" "no")))
        (eq_attr "cpu" "power7"))
   "DU_power7,FXU_power7")
 
   "DU_power7,FXU_power7")
 
 (define_insn_reservation "power7-compare" 2
-  (and (eq_attr "type" "compare,delayed_compare,var_delayed_compare")
+  (and (ior (eq_attr "type" "compare")
+           (and (eq_attr "type" "shift")
+                (eq_attr "dot" "yes")))
        (eq_attr "cpu" "power7"))
   "DU2F_power7,FXU_power7,FXU_power7")
 
index 99c9ec705e556b8b10e124b9b6c36d354f11edbf..2d50d4a69c72f5489330400a2a5cc648078179a8 100644 (file)
 
 ; FX Unit
 (define_insn_reservation "power8-1cyc" 1
-  (and (eq_attr "type" "integer,insert,shift,trap,\
-                        var_shift_rotate,exts,isel")
+  (and (ior (eq_attr "type" "integer,insert,trap,exts,isel")
+           (and (eq_attr "type" "shift")
+                (eq_attr "dot" "no")))
        (eq_attr "cpu" "power8"))
   "DU_any_power8,FXU_power8")
 
   "DU_any_power8,FXU_power8")
 
 ; compare : rldicl./exts./etc
-; delayed_compare : rlwinm./slwi./etc
-; var_delayed_compare : rlwnm./slw./etc
+; shift with dot : rlwinm./slwi./rlwnm./slw./etc
 (define_insn_reservation "power8-compare" 2
-  (and (eq_attr "type" "compare,delayed_compare,var_delayed_compare")
+  (and (ior (eq_attr "type" "compare")
+           (and (eq_attr "type" "shift")
+                (eq_attr "dot" "yes")))
        (eq_attr "cpu" "power8"))
   "DU_cracked_power8,FXU_power8,FXU_power8")
 
index 46cf08e8a23aa20de282b8a850da455982af83d0..53a22deeb8fec36bc248a18e5cac7e0b54616618 100644 (file)
@@ -26188,7 +26188,6 @@ rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
                 {
                 case TYPE_CMP:
                 case TYPE_COMPARE:
-                case TYPE_DELAYED_COMPARE:
                 case TYPE_FPCOMPARE:
                 case TYPE_CR_LOGICAL:
                 case TYPE_DELAYED_CR:
@@ -26198,6 +26197,12 @@ rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
                    return cost + 2;
                  else
                    break;
+                case TYPE_SHIFT:
+                 if (get_attr_dot (dep_insn) == DOT_YES
+                     && get_attr_var_shift (dep_insn) == VAR_SHIFT_NO)
+                   return cost + 2;
+                 else
+                   break;
                default:
                  break;
                }
@@ -26228,18 +26233,17 @@ rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
                                == SIGN_EXTEND_YES ? 6 : 4;
                       break;
                     }
-                  case TYPE_VAR_SHIFT_ROTATE:
-                  case TYPE_VAR_DELAYED_COMPARE:
+                  case TYPE_SHIFT:
                     {
                       if (! store_data_bypass_p (dep_insn, insn))
-                        return 6;
+                        return get_attr_var_shift (dep_insn) == VAR_SHIFT_YES ?
+                               6 : 3;
                       break;
                    }
                   case TYPE_INTEGER:
                   case TYPE_COMPARE:
                   case TYPE_FAST_COMPARE:
                   case TYPE_EXTS:
-                  case TYPE_SHIFT:
                   case TYPE_INSERT:
                     {
                       if (! store_data_bypass_p (dep_insn, insn))
@@ -26292,18 +26296,17 @@ rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
                                == SIGN_EXTEND_YES ? 6 : 4;
                       break;
                     }
-                  case TYPE_VAR_SHIFT_ROTATE:
-                  case TYPE_VAR_DELAYED_COMPARE:
+                  case TYPE_SHIFT:
                     {
                       if (set_to_load_agen (dep_insn, insn))
-                        return 6;
+                        return get_attr_var_shift (dep_insn) == VAR_SHIFT_YES ?
+                               6 : 3;
                       break;
-                    }
+                   }
                   case TYPE_INTEGER:
                   case TYPE_COMPARE:
                   case TYPE_FAST_COMPARE:
                   case TYPE_EXTS:
-                  case TYPE_SHIFT:
                   case TYPE_INSERT:
                     {
                       if (set_to_load_agen (dep_insn, insn))
@@ -26477,7 +26480,10 @@ is_cracked_insn (rtx insn)
          || ((type == TYPE_FPLOAD || type == TYPE_FPSTORE)
              && get_attr_update (insn) == UPDATE_YES)
          || type == TYPE_DELAYED_CR
-         || type == TYPE_COMPARE || type == TYPE_DELAYED_COMPARE
+         || type == TYPE_COMPARE
+         || (type == TYPE_SHIFT
+             && get_attr_dot (insn) == DOT_YES
+             && get_attr_var_shift (insn) == VAR_SHIFT_NO)
          || (type == TYPE_MUL
              && get_attr_dot (insn) == DOT_YES)
          || type == TYPE_DIV
@@ -27307,12 +27313,9 @@ insn_must_be_first_in_group (rtx insn)
         {
         case TYPE_EXTS:
         case TYPE_CNTLZ:
-        case TYPE_SHIFT:
-        case TYPE_VAR_SHIFT_ROTATE:
         case TYPE_TRAP:
         case TYPE_MUL:
         case TYPE_INSERT:
-        case TYPE_DELAYED_COMPARE:
         case TYPE_FPCOMPARE:
         case TYPE_MFCR:
         case TYPE_MTCR:
@@ -27323,6 +27326,12 @@ insn_must_be_first_in_group (rtx insn)
         case TYPE_LOAD_L:
         case TYPE_STORE_C:
           return true;
+        case TYPE_SHIFT:
+          if (get_attr_dot (insn) == DOT_NO
+              || get_attr_var_shift (insn) == VAR_SHIFT_NO)
+            return true;
+          else
+            break;
         case TYPE_DIV:
           if (get_attr_size (insn) == SIZE_32)
             return true;
@@ -27351,8 +27360,6 @@ insn_must_be_first_in_group (rtx insn)
         case TYPE_MTCR:
         case TYPE_DIV:
         case TYPE_COMPARE:
-        case TYPE_DELAYED_COMPARE:
-        case TYPE_VAR_DELAYED_COMPARE:
         case TYPE_ISYNC:
         case TYPE_LOAD_L:
         case TYPE_STORE_C:
@@ -27360,6 +27367,7 @@ insn_must_be_first_in_group (rtx insn)
         case TYPE_MTJMPR:
           return true;
         case TYPE_MUL:
+        case TYPE_SHIFT:
           if (get_attr_dot (insn) == DOT_YES)
             return true;
           else
@@ -27392,8 +27400,6 @@ insn_must_be_first_in_group (rtx insn)
         case TYPE_MFCRF:
         case TYPE_MTCR:
         case TYPE_COMPARE:
-        case TYPE_DELAYED_COMPARE:
-        case TYPE_VAR_DELAYED_COMPARE:
         case TYPE_SYNC:
         case TYPE_ISYNC:
         case TYPE_LOAD_L:
@@ -27402,6 +27408,12 @@ insn_must_be_first_in_group (rtx insn)
         case TYPE_MFJMPR:
         case TYPE_MTJMPR:
           return true;
+        case TYPE_SHIFT:
+        case TYPE_MUL:
+          if (get_attr_dot (insn) == DOT_YES)
+            return true;
+          else
+            break;
         case TYPE_LOAD:
           if (get_attr_sign_extend (insn) == SIGN_EXTEND_YES
               || get_attr_update (insn) == UPDATE_YES)
@@ -27454,11 +27466,8 @@ insn_must_be_last_in_group (rtx insn)
       {
       case TYPE_EXTS:
       case TYPE_CNTLZ:
-      case TYPE_SHIFT:
-      case TYPE_VAR_SHIFT_ROTATE:
       case TYPE_TRAP:
       case TYPE_MUL:
-      case TYPE_DELAYED_COMPARE:
       case TYPE_FPCOMPARE:
       case TYPE_MFCR:
       case TYPE_MTCR:
@@ -27469,6 +27478,12 @@ insn_must_be_last_in_group (rtx insn)
       case TYPE_LOAD_L:
       case TYPE_STORE_C:
         return true;
+      case TYPE_SHIFT:
+        if (get_attr_dot (insn) == DOT_NO
+            || get_attr_var_shift (insn) == VAR_SHIFT_NO)
+          return true;
+        else
+          break;
       case TYPE_DIV:
         if (get_attr_size (insn) == SIZE_32)
           return true;
index 0de26c925c448b6d4af40dfafc4f4e248bc12f8f..c8709473f6dde2e2b604bfefd48c913fbb22ad70 100644 (file)
 ;; computations.
 (define_attr "type"
   "integer,two,three,
-   shift,var_shift_rotate,insert,
+   shift,insert,
    mul,halfmul,div,
    exts,cntlz,popcnt,isel,
    load,store,fpload,fpstore,vecload,vecstore,
    cmp,
    branch,jmpreg,mfjmpr,mtjmpr,trap,isync,sync,load_l,store_c,
-   compare,fast_compare,delayed_compare,var_delayed_compare,
+   compare,fast_compare,
    cr_logical,delayed_cr,mfcr,mfcrf,mtcr,
    fpcompare,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,
    brinc,
                (const_string "yes")
                (const_string "no")))
 
+;; Is this instruction using a shift amount from a register?
+;; This is used for shift insns.
+(define_attr "var_shift" "no,yes" (const_string "no"))
+
 ;; Define floating point instruction sub-types for use with Xfpu.md
 (define_attr "fp_type" "fp_default,fp_addsub_s,fp_addsub_d,fp_mul_s,fp_mul_d,fp_div_s,fp_div_d,fp_maddsub_s,fp_maddsub_d,fp_sqrt_s,fp_sqrt_d" (const_string "fp_default"))
 
 ;; If this instruction is microcoded on the CELL processor
 ; The default for load extended, the recorded instructions and rotate/shifts by a variable is always microcoded
 (define_attr "cell_micro" "not,conditional,always"
-  (if_then_else (ior (eq_attr "type" "compare,delayed_compare,var_shift_rotate,var_delayed_compare")
-                    (and (eq_attr "type" "mul")
+  (if_then_else (ior (eq_attr "type" "compare")
+                    (and (eq_attr "type" "shift,mul")
                          (eq_attr "dot" "yes"))
                     (and (eq_attr "type" "load")
-                         (eq_attr "sign_extend" "yes")))
+                         (eq_attr "sign_extend" "yes"))
+                    (and (eq_attr "type" "shift")
+                         (eq_attr "var_shift" "yes")))
                (const_string "always")
                (const_string "not")))
 
    #
    #
    #"
-  [(set_attr "type" "fast_compare,fast_compare,fast_compare,delayed_compare,\
+  [(set_attr "type" "fast_compare,fast_compare,fast_compare,shift,\
                     compare,compare,compare,compare")
+   (set_attr "dot" "yes")
    (set_attr "length" "4,4,4,4,8,8,8,8")])
 
 (define_insn "*andsi3_internal3_mc"
    #
    #
    #"
-  [(set_attr "type" "compare,fast_compare,fast_compare,delayed_compare,compare,\
+  [(set_attr "type" "compare,fast_compare,fast_compare,shift,compare,\
                     compare,compare,compare")
+   (set_attr "dot" "yes")
    (set_attr "length" "8,4,4,4,8,8,8,8")])
 
 (define_split
    #
    #
    #"
-  [(set_attr "type" "fast_compare,fast_compare,fast_compare,delayed_compare,\
+  [(set_attr "type" "fast_compare,fast_compare,fast_compare,shift,\
                     compare,compare,compare,compare")
+   (set_attr "dot" "yes")
    (set_attr "length" "4,4,4,4,8,8,8,8")])
 
 (define_insn "*andsi3_internal5_mc"
    #
    #
    #"
-  [(set_attr "type" "compare,fast_compare,fast_compare,delayed_compare,compare,\
+  [(set_attr "type" "compare,fast_compare,fast_compare,shift,compare,\
                     compare,compare,compare")
+   (set_attr "dot" "yes")
    (set_attr "length" "8,4,4,4,8,8,8,8")])
 
 (define_split
     operands[3] = GEN_INT (start + size);
   return \"rlwinm. %4,%1,%3,%s2,31\";
 }"
-  [(set_attr "type" "delayed_compare")
+  [(set_attr "type" "shift")
+   (set_attr "dot" "yes")
    (set_attr "length" "4,8")])
 
 (define_split
     operands[3] = GEN_INT (start + size);
   return \"rlwinm. %0,%1,%3,%s2,31\";
 }"
-  [(set_attr "type" "delayed_compare")
+  [(set_attr "type" "shift")
+   (set_attr "dot" "yes")
    (set_attr "length" "4,8")])
 
 (define_split
   "@
    rlwnm %0,%1,%2,0xffffffff
    rlwinm %0,%1,%h2,0xffffffff"
-  [(set_attr "type" "var_shift_rotate,integer")])
+  [(set_attr "type" "shift,integer")
+   (set_attr "var_shift" "yes,no")])
 
 (define_insn "*rotlsi3_64"
   [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
   "@
    rlwnm %0,%1,%2,0xffffffff
    rlwinm %0,%1,%h2,0xffffffff"
-  [(set_attr "type" "var_shift_rotate,integer")])
+  [(set_attr "type" "shift,integer")
+   (set_attr "var_shift" "yes,no")])
 
 (define_insn "*rotlsi3_internal2"
   [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
    rlwinm. %3,%1,%h2,0xffffffff
    #
    #"
-  [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
+  [(set_attr "type" "shift")
+   (set_attr "var_shift" "yes,no,yes,no")
+   (set_attr "dot" "yes")
    (set_attr "length" "4,4,8,8")])
 
 (define_split
    rlwinm. %0,%1,%h2,0xffffffff
    #
    #"
-  [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
+  [(set_attr "type" "shift")
+   (set_attr "var_shift" "yes,no,yes,no")
+   (set_attr "dot" "yes")
    (set_attr "length" "4,4,8,8")])
 
 (define_split
   "@
    rlwnm %0,%1,%2,%m3,%M3
    rlwinm %0,%1,%h2,%m3,%M3"
-  [(set_attr "type" "var_shift_rotate,integer")])
+  [(set_attr "type" "shift,integer")
+   (set_attr "var_shift" "yes,no")])
 
 (define_insn "*rotlsi3_internal5"
   [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
    rlwinm. %4,%1,%h2,%m3,%M3
    #
    #"
-  [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
+  [(set_attr "type" "shift")
+   (set_attr "var_shift" "yes,no,yes,no")
+   (set_attr "dot" "yes")
    (set_attr "length" "4,4,8,8")])
 
 (define_split
    rlwinm. %0,%1,%h2,%m3,%M3
    #
    #"
-  [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
+  [(set_attr "type" "shift")
+   (set_attr "var_shift" "yes,no,yes,no")
+   (set_attr "dot" "yes")
    (set_attr "length" "4,4,8,8")])
 
 (define_split
    rlwinm. %3,%1,%h2,0xff
    #
    #"
-  [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
+  [(set_attr "type" "shift")
+   (set_attr "var_shift" "yes,no,yes,no")
+   (set_attr "dot" "yes")
    (set_attr "length" "4,4,8,8")])
 
 (define_insn "*rotlsi3_internal8be"
    rlwinm. %3,%1,%h2,0xff
    #
    #"
-  [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
+  [(set_attr "type" "shift")
+   (set_attr "var_shift" "yes,no,yes,no")
+   (set_attr "dot" "yes")
    (set_attr "length" "4,4,8,8")])
 
 (define_split
    rlwinm. %0,%1,%h2,0xff
    #
    #"
-  [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
+  [(set_attr "type" "shift")
+   (set_attr "var_shift" "yes,no,yes,no")
+   (set_attr "dot" "yes")
    (set_attr "length" "4,4,8,8")])
 
 (define_insn "*rotlsi3_internal9be"
    rlwinm. %0,%1,%h2,0xff
    #
    #"
-  [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
+  [(set_attr "type" "shift")
+   (set_attr "var_shift" "yes,no,yes,no")
+   (set_attr "dot" "yes")
    (set_attr "length" "4,4,8,8")])
 
 (define_split
   "@
    rlwnm %0,%1,%2,0xffff
    rlwinm %0,%1,%h2,0xffff"
-  [(set_attr "type" "var_shift_rotate,integer")])
+  [(set_attr "type" "shift,integer")
+   (set_attr "var_shift" "yes,no")])
 
 (define_insn "*rotlsi3_internal10be"
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
   "@
    rlwnm %0,%1,%2,0xffff
    rlwinm %0,%1,%h2,0xffff"
-  [(set_attr "type" "var_shift_rotate,integer")])
+  [(set_attr "type" "shift,integer")
+   (set_attr "var_shift" "yes,no")])
 
 (define_insn "*rotlsi3_internal11le"
   [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
    rlwinm. %3,%1,%h2,0xffff
    #
    #"
-  [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
+  [(set_attr "type" "shift")
+   (set_attr "var_shift" "yes,no,yes,no")
+   (set_attr "dot" "yes")
    (set_attr "length" "4,4,8,8")])
 
 (define_insn "*rotlsi3_internal11be"
    rlwinm. %3,%1,%h2,0xffff
    #
    #"
-  [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
+  [(set_attr "type" "shift")
+   (set_attr "var_shift" "yes,no,yes,no")
+   (set_attr "dot" "yes")
    (set_attr "length" "4,4,8,8")])
 
 (define_split
    rlwinm. %0,%1,%h2,0xffff
    #
    #"
-  [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
+  [(set_attr "type" "shift")
+   (set_attr "var_shift" "yes,no,yes,no")
+   (set_attr "dot" "yes")
    (set_attr "length" "4,4,8,8")])
 
 (define_insn "*rotlsi3_internal12be"
    rlwinm. %0,%1,%h2,0xffff
    #
    #"
-  [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
+  [(set_attr "type" "shift")
+   (set_attr "var_shift" "yes,no,yes,no")
+   (set_attr "dot" "yes")
    (set_attr "length" "4,4,8,8")])
 
 (define_split
   "@
    slw %0,%1,%2
    slwi %0,%1,%h2"
-  [(set_attr "type" "var_shift_rotate,shift")])
+  [(set_attr "type" "shift")
+   (set_attr "var_shift" "yes,no")])
 
 (define_insn "*ashlsi3_64"
   [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
   "@
    slw %0,%1,%2
    slwi %0,%1,%h2"
-  [(set_attr "type" "var_shift_rotate,shift")])
+  [(set_attr "type" "shift")
+   (set_attr "var_shift" "yes,no")])
 
 (define_insn ""
   [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
    slwi. %3,%1,%h2
    #
    #"
-  [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
+  [(set_attr "type" "shift")
+   (set_attr "var_shift" "yes,no,yes,no")
+   (set_attr "dot" "yes")
    (set_attr "length" "4,4,8,8")])
 
 (define_split
    slwi. %0,%1,%h2
    #
    #"
-  [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
+  [(set_attr "type" "shift")
+   (set_attr "var_shift" "yes,no,yes,no")
+   (set_attr "dot" "yes")
    (set_attr "length" "4,4,8,8")])
 
 (define_split
   "@
    rlwinm. %4,%1,%h2,%m3,%M3
    #"
-  [(set_attr "type" "delayed_compare")
+  [(set_attr "type" "shift")
+   (set_attr "dot" "yes")
    (set_attr "length" "4,8")])
 
 (define_split
   "@
    rlwinm. %0,%1,%h2,%m3,%M3
    #"
-  [(set_attr "type" "delayed_compare")
+  [(set_attr "type" "shift")
+   (set_attr "dot" "yes")
    (set_attr "length" "4,8")])
 
 (define_split
   mr %0,%1
   srw %0,%1,%2
   srwi %0,%1,%h2"
-  [(set_attr "type" "integer,var_shift_rotate,shift")])
+  [(set_attr "type" "integer,shift,shift")
+   (set_attr "var_shift" "no,yes,no")])
 
 (define_insn "*lshrsi3_64"
   [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
   "@
   srw %0,%1,%2
   srwi %0,%1,%h2"
-  [(set_attr "type" "var_shift_rotate,shift")])
+  [(set_attr "type" "shift")
+   (set_attr "var_shift" "yes,no")])
 
 (define_insn ""
   [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
    #
    #
    #"
-  [(set_attr "type" "fast_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
+  [(set_attr "type" "fast_compare,shift,shift,shift,shift,shift")
+   (set_attr "var_shift" "no,yes,no,no,yes,no")
+   (set_attr "dot" "yes")
    (set_attr "length" "4,4,4,8,8,8")])
 
 (define_split
    #
    #
    #"
-  [(set_attr "type" "fast_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
+  [(set_attr "type" "fast_compare,shift,shift,shift,shift,shift")
+   (set_attr "var_shift" "no,yes,no,no,yes,no")
+   (set_attr "dot" "yes")
    (set_attr "length" "4,4,4,8,8,8")])
 
 (define_split
   "@
    rlwinm. %4,%1,%s2,%m3,%M3
    #"
-  [(set_attr "type" "delayed_compare")
+  [(set_attr "type" "shift")
+   (set_attr "dot" "yes")
    (set_attr "length" "4,8")])
 
 (define_split
   "@
    rlwinm. %0,%1,%s2,%m3,%M3
    #"
-  [(set_attr "type" "delayed_compare")
+  [(set_attr "type" "shift")
+   (set_attr "dot" "yes")
    (set_attr "length" "4,8")])
 
 (define_split
   "@
    rlwinm. %3,%1,%s2,0xff
    #"
-  [(set_attr "type" "delayed_compare")
+  [(set_attr "type" "shift")
+   (set_attr "dot" "yes")
    (set_attr "length" "4,8")])
 
 (define_insn "*lshiftrt_internal2be"
   "@
    rlwinm. %3,%1,%s2,0xff
    #"
-  [(set_attr "type" "delayed_compare")
+  [(set_attr "type" "shift")
+   (set_attr "dot" "yes")
    (set_attr "length" "4,8")])
 
 (define_split
   "@
    rlwinm. %0,%1,%s2,0xff
    #"
-  [(set_attr "type" "delayed_compare")
+  [(set_attr "type" "shift")
+   (set_attr "dot" "yes")
    (set_attr "length" "4,8")])
 
 (define_insn "*lshiftrt_internal3be"
   "@
    rlwinm. %0,%1,%s2,0xff
    #"
-  [(set_attr "type" "delayed_compare")
+  [(set_attr "type" "shift")
+   (set_attr "dot" "yes")
    (set_attr "length" "4,8")])
 
 (define_split
   "@
    rlwinm. %3,%1,%s2,0xffff
    #"
-  [(set_attr "type" "delayed_compare")
+  [(set_attr "type" "shift")
+   (set_attr "dot" "yes")
    (set_attr "length" "4,8")])
 
 (define_insn "*lshiftrt_internal5be"
   "@
    rlwinm. %3,%1,%s2,0xffff
    #"
-  [(set_attr "type" "delayed_compare")
+  [(set_attr "type" "shift")
+   (set_attr "dot" "yes")
    (set_attr "length" "4,8")])
 
 (define_split
   "@
    rlwinm. %0,%1,%s2,0xffff
    #"
-  [(set_attr "type" "delayed_compare")
+  [(set_attr "type" "shift")
+   (set_attr "dot" "yes")
    (set_attr "length" "4,8")])
 
 (define_insn "*lshiftrt_internal5be"
   "@
    rlwinm. %0,%1,%s2,0xffff
    #"
-  [(set_attr "type" "delayed_compare")
+  [(set_attr "type" "shift")
+   (set_attr "dot" "yes")
    (set_attr "length" "4,8")])
 
 (define_split
   "@
    sraw %0,%1,%2
    srawi %0,%1,%h2"
-  [(set_attr "type" "var_shift_rotate,shift")])
+  [(set_attr "type" "shift")
+   (set_attr "var_shift" "yes,no")])
 
 (define_insn "*ashrsi3_64"
   [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
   "@
    sraw %0,%1,%2
    srawi %0,%1,%h2"
-  [(set_attr "type" "var_shift_rotate,shift")])
+  [(set_attr "type" "shift")
+   (set_attr "var_shift" "yes,no")])
 
 (define_insn ""
   [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
    srawi. %3,%1,%h2
    #
    #"
-  [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
+  [(set_attr "type" "shift")
+   (set_attr "var_shift" "yes,no,yes,no")
+   (set_attr "dot" "yes")
    (set_attr "length" "4,4,8,8")])
 
 (define_split
    srawi. %0,%1,%h2
    #
    #"
-  [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
+  [(set_attr "type" "shift")
+   (set_attr "var_shift" "yes,no,yes,no")
+   (set_attr "dot" "yes")
    (set_attr "length" "4,4,8,8")])
 \f
 ;; Builtins to replace a division to generate FRE reciprocal estimate
   "@
    rldcl %0,%1,%2,0
    rldicl %0,%1,%H2,0"
-  [(set_attr "type" "var_shift_rotate,integer")])
+  [(set_attr "type" "shift,integer")
+   (set_attr "var_shift" "yes,no")])
 
 (define_insn "*rotldi3_internal2"
   [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
    rldicl. %3,%1,%H2,0
    #
    #"
-  [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
+  [(set_attr "type" "shift")
+   (set_attr "var_shift" "yes,no,yes,no")
+   (set_attr "dot" "yes")
    (set_attr "length" "4,4,8,8")])
 
 (define_split
    rldicl. %0,%1,%H2,0
    #
    #"
-  [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
+  [(set_attr "type" "shift")
+   (set_attr "var_shift" "yes,no,yes,no")
+   (set_attr "dot" "yes")
    (set_attr "length" "4,4,8,8")])
 
 (define_split
   "@
    rldc%B3 %0,%1,%2,%S3
    rldic%B3 %0,%1,%H2,%S3"
-  [(set_attr "type" "var_shift_rotate,integer")])
+  [(set_attr "type" "shift,integer")
+   (set_attr "var_shift" "yes,no")])
 
 (define_insn "*rotldi3_internal5"
   [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
    rldic%B3. %4,%1,%H2,%S3
    #
    #"
-  [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
+  [(set_attr "type" "shift")
+   (set_attr "var_shift" "yes,no,yes,no")
+   (set_attr "dot" "yes")
    (set_attr "length" "4,4,8,8")])
 
 (define_split
    rldic%B3. %0,%1,%H2,%S3
    #
    #"
-  [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
+  [(set_attr "type" "shift")
+   (set_attr "var_shift" "yes,no,yes,no")
+   (set_attr "dot" "yes")
    (set_attr "length" "4,4,8,8")])
 
 (define_split
   "@
    rldcl %0,%1,%2,56
    rldicl %0,%1,%H2,56"
-  [(set_attr "type" "var_shift_rotate,integer")])
+  [(set_attr "type" "shift,integer")
+   (set_attr "var_shift" "yes,no")])
 
 (define_insn "*rotldi3_internal7be"
   [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
   "@
    rldcl %0,%1,%2,56
    rldicl %0,%1,%H2,56"
-  [(set_attr "type" "var_shift_rotate,integer")])
+  [(set_attr "type" "shift,integer")
+   (set_attr "var_shift" "yes,no")])
 
 (define_insn "*rotldi3_internal8le"
   [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
    rldicl. %3,%1,%H2,56
    #
    #"
-  [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
+  [(set_attr "type" "shift")
+   (set_attr "var_shift" "yes,no,yes,no")
+   (set_attr "dot" "yes")
    (set_attr "length" "4,4,8,8")])
 
 (define_insn "*rotldi3_internal8be"
    rldicl. %3,%1,%H2,56
    #
    #"
-  [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
+  [(set_attr "type" "shift")
+   (set_attr "var_shift" "yes,no,yes,no")
+   (set_attr "dot" "yes")
    (set_attr "length" "4,4,8,8")])
 
 (define_split
    rldicl. %0,%1,%H2,56
    #
    #"
-  [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
+  [(set_attr "type" "shift")
+   (set_attr "var_shift" "yes,no,yes,no")
+   (set_attr "dot" "yes")
    (set_attr "length" "4,4,8,8")])
 
 (define_insn "*rotldi3_internal9be"
    rldicl. %0,%1,%H2,56
    #
    #"
-  [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
+  [(set_attr "type" "shift")
+   (set_attr "var_shift" "yes,no,yes,no")
+   (set_attr "dot" "yes")
    (set_attr "length" "4,4,8,8")])
 
 (define_split
   "@
    rldcl %0,%1,%2,48
    rldicl %0,%1,%H2,48"
-  [(set_attr "type" "var_shift_rotate,integer")])
+  [(set_attr "type" "shift,integer")
+   (set_attr "var_shift" "yes,no")])
 
 (define_insn "*rotldi3_internal10be"
   [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
   "@
    rldcl %0,%1,%2,48
    rldicl %0,%1,%H2,48"
-  [(set_attr "type" "var_shift_rotate,integer")])
+  [(set_attr "type" "shift,integer")
+   (set_attr "var_shift" "yes,no")])
 
 (define_insn "*rotldi3_internal11le"
   [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
    rldicl. %3,%1,%H2,48
    #
    #"
-  [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
+  [(set_attr "type" "shift")
+   (set_attr "var_shift" "yes,no,yes,no")
+   (set_attr "dot" "yes")
    (set_attr "length" "4,4,8,8")])
 
 (define_insn "*rotldi3_internal11be"
    rldicl. %3,%1,%H2,48
    #
    #"
-  [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
+  [(set_attr "type" "shift")
+   (set_attr "var_shift" "yes,no,yes,no")
+   (set_attr "dot" "yes")
    (set_attr "length" "4,4,8,8")])
 
 (define_split
    rldicl. %0,%1,%H2,48
    #
    #"
-  [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
+  [(set_attr "type" "shift")
+   (set_attr "var_shift" "yes,no,yes,no")
+   (set_attr "dot" "yes")
    (set_attr "length" "4,4,8,8")])
 
 (define_insn "*rotldi3_internal12be"
    rldicl. %0,%1,%H2,48
    #
    #"
-  [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
+  [(set_attr "type" "shift")
+   (set_attr "var_shift" "yes,no,yes,no")
+   (set_attr "dot" "yes")
    (set_attr "length" "4,4,8,8")])
 
 (define_split
   "@
    rldcl %0,%1,%2,32
    rldicl %0,%1,%H2,32"
-  [(set_attr "type" "var_shift_rotate,integer")])
+  [(set_attr "type" "shift,integer")
+   (set_attr "var_shift" "yes,no")])
 
 (define_insn "*rotldi3_internal13be"
   [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
   "@
    rldcl %0,%1,%2,32
    rldicl %0,%1,%H2,32"
-  [(set_attr "type" "var_shift_rotate,integer")])
+  [(set_attr "type" "shift,integer")
+   (set_attr "var_shift" "yes,no")])
 
 (define_insn "*rotldi3_internal14le"
   [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
    rldicl. %3,%1,%H2,32
    #
    #"
-  [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
+  [(set_attr "type" "shift")
+   (set_attr "var_shift" "yes,no,yes,no")
+   (set_attr "dot" "yes")
    (set_attr "length" "4,4,8,8")])
 
 (define_insn "*rotldi3_internal14be"
    rldicl. %3,%1,%H2,32
    #
    #"
-  [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
+  [(set_attr "type" "shift")
+   (set_attr "var_shift" "yes,no,yes,no")
+   (set_attr "dot" "yes")
    (set_attr "length" "4,4,8,8")])
 
 (define_split
    rldicl. %0,%1,%H2,32
    #
    #"
-  [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
+  [(set_attr "type" "shift")
+   (set_attr "var_shift" "yes,no,yes,no")
+   (set_attr "dot" "yes")
    (set_attr "length" "4,4,8,8")])
 
 (define_insn "*rotldi3_internal15be"
    rldicl. %0,%1,%H2,32
    #
    #"
-  [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
+  [(set_attr "type" "shift")
+   (set_attr "var_shift" "yes,no,yes,no")
+   (set_attr "dot" "yes")
    (set_attr "length" "4,4,8,8")])
 
 (define_split
   "@
    sld %0,%1,%2
    sldi %0,%1,%H2"
-  [(set_attr "type" "var_shift_rotate,shift")])
+  [(set_attr "type" "shift")
+   (set_attr "var_shift" "yes,no")])
 
 (define_insn "*ashldi3_internal2"
   [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
    sldi. %3,%1,%H2
    #
    #"
-  [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
+  [(set_attr "type" "shift")
+   (set_attr "var_shift" "yes,no,yes,no")
+   (set_attr "dot" "yes")
    (set_attr "length" "4,4,8,8")])
 
 (define_split
    sldi. %0,%1,%H2
    #
    #"
-  [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
+  [(set_attr "type" "shift")
+   (set_attr "var_shift" "yes,no,yes,no")
+   (set_attr "dot" "yes")
    (set_attr "length" "4,4,8,8")])
 
 (define_split
   "@
    srd %0,%1,%2
    srdi %0,%1,%H2"
-  [(set_attr "type" "var_shift_rotate,shift")])
+  [(set_attr "type" "shift")
+   (set_attr "var_shift" "yes,no")])
 
 (define_insn "*lshrdi3_internal2"
   [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
    srdi. %3,%1,%H2
    #
    #"
-  [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
+  [(set_attr "type" "shift")
+   (set_attr "var_shift" "yes,no,yes,no")
+   (set_attr "dot" "yes")
    (set_attr "length" "4,4,8,8")])
 
 (define_split
    srdi. %0,%1,%H2
    #
    #"
-  [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
+  [(set_attr "type" "shift")
+   (set_attr "var_shift" "yes,no,yes,no")
+   (set_attr "dot" "yes")
    (set_attr "length" "4,4,8,8")])
 
 (define_split
   "@
    srad %0,%1,%2
    sradi %0,%1,%H2"
-  [(set_attr "type" "var_shift_rotate,shift")])
+  [(set_attr "type" "shift")
+   (set_attr "var_shift" "yes,no")])
 
 (define_insn "*ashrdi3_internal2"
   [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
    sradi. %3,%1,%H2
    #
    #"
-  [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
+  [(set_attr "type" "shift")
+   (set_attr "var_shift" "yes,no,yes,no")
+   (set_attr "dot" "yes")
    (set_attr "length" "4,4,8,8")])
 
 (define_split
    sradi. %0,%1,%H2
    #
    #"
-  [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
+  [(set_attr "type" "shift")
+   (set_attr "var_shift" "yes,no,yes,no")
+   (set_attr "dot" "yes")
    (set_attr "length" "4,4,8,8")])
 
 (define_split
    #
    #
    #"
-  [(set_attr "type" "fast_compare,compare,delayed_compare,fast_compare,\
+  [(set_attr "type" "fast_compare,compare,shift,fast_compare,\
                     fast_compare,compare,compare,compare,compare,compare,\
                     compare,compare")
+   (set_attr "dot" "yes")
    (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
 
 (define_split
    #
    #
    #"
-  [(set_attr "type" "fast_compare,compare,delayed_compare,fast_compare,\
+  [(set_attr "type" "fast_compare,compare,shift,fast_compare,\
                     fast_compare,compare,compare,compare,compare,compare,\
                     compare,compare")
+   (set_attr "dot" "yes")
    (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
 
 (define_split
   "@
    mfcr %3%Q2\;rlwinm. %3,%3,%J1,1
    #"
-  [(set_attr "type" "delayed_compare")
+  [(set_attr "type" "shift")
+   (set_attr "dot" "yes")
    (set_attr "length" "8,16")])
 
 (define_split
 
   return \"mfcr %4%Q2\;rlwinm. %4,%4,%5,%6,%6\";
 }"
-  [(set_attr "type" "delayed_compare")
+  [(set_attr "type" "shift")
+   (set_attr "dot" "yes")
    (set_attr "length" "8,16")])
 
 (define_split
index 0260a1c9349202ddf9b63bc94c38bcca5c7ed6f1..82ace4a7b1c9579645bf7352da3c23518f8f5e93 100644 (file)
@@ -46,8 +46,9 @@
   "lsu_rs64")
 
 (define_insn_reservation "rs64a-integer" 1
-  (and (eq_attr "type" "integer,insert,shift,trap,\
-                        var_shift_rotate,cntlz,exts,isel")
+  (and (ior (eq_attr "type" "integer,insert,trap,cntlz,exts,isel")
+           (and (eq_attr "type" "shift")
+                (eq_attr "dot" "no")))
        (eq_attr "cpu" "rs64a"))
   "iu_rs64")
 
@@ -98,8 +99,9 @@
   "mciu_rs64*66")
 
 (define_insn_reservation "rs64a-compare" 3
-  (and (eq_attr "type" "cmp,fast_compare,compare,\
-                delayed_compare,var_delayed_compare")
+  (and (ior (eq_attr "type" "cmp,fast_compare,compare")
+           (and (eq_attr "type" "shift")
+                (eq_attr "dot" "yes")))
        (eq_attr "cpu" "rs64a"))
   "iu_rs64,nothing,bpu_rs64")
 
index 1d33c0f6474b58ad7175166532b8d546f50a42d4..7443d7cf5968c5d2af21460c3130846a062e3805 100644 (file)
@@ -51,7 +51,7 @@
 (define_bypass 2 "titan_mulhw" "titan_mulhw")
 
 (define_insn_reservation "titan_fxu_shift_and_rotate" 2
-  (and (eq_attr "type" "insert,shift,var_shift_rotate,cntlz")
+  (and (eq_attr "type" "insert,shift,cntlz")
        (eq_attr "cpu" "titan"))
   "titan_issue,titan_fxu_sh,nothing*2,titan_fxu_wb")