]> git.ipfire.org Git - thirdparty/kernel/stable-queue.git/commitdiff
4.9-stable patches
authorGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Mon, 11 Apr 2022 08:26:36 +0000 (10:26 +0200)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Mon, 11 Apr 2022 08:26:36 +0000 (10:26 +0200)
added patches:
irqchip-gic-v3-fix-gicr_ctlr.rwp-polling.patch

queue-4.9/irqchip-gic-v3-fix-gicr_ctlr.rwp-polling.patch [new file with mode: 0644]
queue-4.9/series

diff --git a/queue-4.9/irqchip-gic-v3-fix-gicr_ctlr.rwp-polling.patch b/queue-4.9/irqchip-gic-v3-fix-gicr_ctlr.rwp-polling.patch
new file mode 100644 (file)
index 0000000..ba6b9b9
--- /dev/null
@@ -0,0 +1,61 @@
+From 0df6664531a12cdd8fc873f0cac0dcb40243d3e9 Mon Sep 17 00:00:00 2001
+From: Marc Zyngier <maz@kernel.org>
+Date: Tue, 15 Mar 2022 16:50:32 +0000
+Subject: irqchip/gic-v3: Fix GICR_CTLR.RWP polling
+
+From: Marc Zyngier <maz@kernel.org>
+
+commit 0df6664531a12cdd8fc873f0cac0dcb40243d3e9 upstream.
+
+It turns out that our polling of RWP is totally wrong when checking
+for it in the redistributors, as we test the *distributor* bit index,
+whereas it is a different bit number in the RDs... Oopsie boo.
+
+This is embarassing. Not only because it is wrong, but also because
+it took *8 years* to notice the blunder...
+
+Just fix the damn thing.
+
+Fixes: 021f653791ad ("irqchip: gic-v3: Initial support for GICv3")
+Signed-off-by: Marc Zyngier <maz@kernel.org>
+Cc: stable@vger.kernel.org
+Reviewed-by: Andre Przywara <andre.przywara@arm.com>
+Reviewed-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
+Link: https://lore.kernel.org/r/20220315165034.794482-2-maz@kernel.org
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/irqchip/irq-gic-v3.c |    8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+--- a/drivers/irqchip/irq-gic-v3.c
++++ b/drivers/irqchip/irq-gic-v3.c
+@@ -92,11 +92,11 @@ static inline void __iomem *gic_dist_bas
+       return NULL;
+ }
+-static void gic_do_wait_for_rwp(void __iomem *base)
++static void gic_do_wait_for_rwp(void __iomem *base, u32 bit)
+ {
+       u32 count = 1000000;    /* 1s! */
+-      while (readl_relaxed(base + GICD_CTLR) & GICD_CTLR_RWP) {
++      while (readl_relaxed(base + GICD_CTLR) & bit) {
+               count--;
+               if (!count) {
+                       pr_err_ratelimited("RWP timeout, gone fishing\n");
+@@ -110,13 +110,13 @@ static void gic_do_wait_for_rwp(void __i
+ /* Wait for completion of a distributor change */
+ static void gic_dist_wait_for_rwp(void)
+ {
+-      gic_do_wait_for_rwp(gic_data.dist_base);
++      gic_do_wait_for_rwp(gic_data.dist_base, GICD_CTLR_RWP);
+ }
+ /* Wait for completion of a redistributor change */
+ static void gic_redist_wait_for_rwp(void)
+ {
+-      gic_do_wait_for_rwp(gic_data_rdist_rd_base());
++      gic_do_wait_for_rwp(gic_data_rdist_rd_base(), GICR_CTLR_RWP);
+ }
+ #ifdef CONFIG_ARM64
index 6be43e0efed0d76c72be90f384bb309e3a5e2ab6..c6ca7d75cfdf159ada92f21f3ca557268ac09cff 100644 (file)
@@ -194,3 +194,4 @@ mm-mempolicy-fix-mpol_new-leak-in-shared_policy_replace.patch
 x86-pm-save-the-msr-validity-status-at-context-setup.patch
 x86-speculation-restore-speculation-related-msrs-during-s3-resume.patch
 arm64-patch_text-fixup-last-cpu-should-be-master.patch
+irqchip-gic-v3-fix-gicr_ctlr.rwp-polling.patch