rs6000: Rework vector float comparison in rs6000_emit_vector_compare - p3

All kinds of vector float comparison operators have been
supported in a rtl comparison pattern as vector.md, we can
just emit an rtx comparison insn with the given comparison
operator in function rs6000_emit_vector_compare instead of
checking and handling the reverse condition cases.

This is part 3, it further checks for comparison opeators
LE/UNGT.  In rs6000_emit_vector_compare, UNGT is handled
with reversed code LE and inverting with one_cmpl_optab,
LE is handled with LT ior EQ, while in vector.md, we have
the support:

; le(a,b)   = ge(b,a)
; ungt(a,b) = ~le(a,b)

The associated test case shows it's an improvement.

gcc/ChangeLog:

	* config/rs6000/rs6000.cc (rs6000_emit_vector_compare): Emit rtx
	comparison for operators LE/UNGT of MODE_VECTOR_FLOAT directly.

gcc/testsuite/ChangeLog:

	* gcc.target/powerpc/vcond-fp.c: New test.

diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 793fb95b660b3588c80855e823a0cf5840262c69..9cde30853f76d4c5238fbfeacab0fc5d150d14c6 100644 (file)
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -16052,15 +16052,15 @@ rs6000_emit_vector_compare (enum rtx_code rcode,
      of raising invalid exception.  For EQ/GT/GE/UNORDERED/
      ORDERED/LTGT/UNEQ, they are handled equivalently as before;
      for NE/UNLE/UNLT, they are handled with reversed code
-     and inverting, it's the same as before.
+     and inverting, it's the same as before; for LE/UNGT, they
+     are handled with LE ior EQ previously, emitting directly
+     here will make use of GE later, it's slightly better;
 
      FIXME: Handle the remaining vector float comparison operators
      here.  */
   if (GET_MODE_CLASS (dmode) == MODE_VECTOR_FLOAT
       && rcode != LT
-      && rcode != LE
-      && rcode != UNGE
-      && rcode != UNGT)
+      && rcode != UNGE)
     {
       mask = gen_reg_rtx (dmode);
       emit_insn (gen_rtx_SET (mask, gen_rtx_fmt_ee (rcode, dmode, op0, op1)));
@@ -16089,7 +16089,6 @@ rs6000_emit_vector_compare (enum rtx_code rcode,
       break;
     case NE:
     case UNGE:
-    case UNGT:
       /* Invert condition and try again.
         e.g., A != B becomes ~(A==B).  */
       {

diff --git a/gcc/testsuite/gcc.target/powerpc/vcond-fp.c b/gcc/testsuite/gcc.target/powerpc/vcond-fp.c
new file mode 100644 (file)
index 0000000..2a9f056
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vcond-fp.c
@@ -0,0 +1,26 @@
+/* { dg-require-effective-target powerpc_vsx } */
+/* { dg-options "-O2 -ftree-vectorize -fno-vect-cost-model" } */
+/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */
+
+/* Test we use xvcmpge[sd]p rather than xvcmpeq[sd]p and xvcmpgt[sd]p
+   for UNGT and LE handlings.  */
+
+#define UNGT(a, b) (!__builtin_islessequal ((a), (b)))
+#define LE(a, b) (((a) <= (b)))
+
+#define TEST_VECT(NAME, TYPE)                                                  \
+  __attribute__ ((noipa)) void test_##NAME##_##TYPE (TYPE *x, TYPE *y,         \
+                                                    int *res, int n)          \
+  {                                                                            \
+    for (int i = 0; i < n; i++)                                                \
+      res[i] = NAME (x[i], y[i]);                                              \
+  }
+
+#define TEST(TYPE)                                                             \
+  TEST_VECT (UNGT, TYPE)                                                       \
+  TEST_VECT (LE, TYPE)
+
+TEST (float)
+TEST (double)
+
+/* { dg-final { scan-assembler-not {\mxvcmp(gt|eq)[sd]p\M} } } */