clk: tegra: Add AHB DMA clock entry

AHB DMA engine presents on Tegra20/30. Add missing clock entries, so that
driver for the AHB DMA controller could be implemented.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

diff --git a/drivers/clk/tegra/clk-id.h b/drivers/clk/tegra/clk-id.h
index 689f344377a7aad3604be95f457b27a7585547bb..c1661b47bbdac695f8801f044300c085b4c6fbe1 100644 (file)
--- a/drivers/clk/tegra/clk-id.h
+++ b/drivers/clk/tegra/clk-id.h
@@ -12,6 +12,7 @@ enum clk_id {
        tegra_clk_amx,
        tegra_clk_amx1,
        tegra_clk_apb2ape,
+       tegra_clk_ahbdma,
        tegra_clk_apbdma,
        tegra_clk_apbif,
        tegra_clk_ape,

diff --git a/drivers/clk/tegra/clk-tegra-periph.c b/drivers/clk/tegra/clk-tegra-periph.c
index c7694205573f9e80ce31348e4705ca06a6e4c1e5..f5232d6d203dce2e562b73f688b363413fd253ba 100644 (file)
--- a/drivers/clk/tegra/clk-tegra-periph.c
+++ b/drivers/clk/tegra/clk-tegra-periph.c
@@ -807,6 +807,7 @@ static struct tegra_periph_init_data gate_clks[] = {
        GATE("timer", "clk_m", 5, 0, tegra_clk_timer, CLK_IS_CRITICAL),
        GATE("isp", "clk_m", 23, 0, tegra_clk_isp, 0),
        GATE("vcp", "clk_m", 29, 0, tegra_clk_vcp, 0),
+       GATE("ahbdma", "hclk", 33, 0, tegra_clk_ahbdma, 0),
        GATE("apbdma", "clk_m", 34, 0, tegra_clk_apbdma, 0),
        GATE("kbc", "clk_32k", 36, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_kbc, 0),
        GATE("fuse", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse, 0),

diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index 2b839cb2443619645ef15452ed7ed0eb33d5fa01..02b7ab292e97d46687e769d6f7d57f2f15a1ef0d 100644 (file)
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -522,6 +522,7 @@ static struct tegra_devclk devclks[] __initdata = {
 };
 
 static struct tegra_clk tegra20_clks[tegra_clk_max] __initdata = {
+       [tegra_clk_ahbdma] = { .dt_id = TEGRA20_CLK_AHBDMA, .present = true },
        [tegra_clk_spdif_out] = { .dt_id = TEGRA20_CLK_SPDIF_OUT, .present = true },
        [tegra_clk_spdif_in] = { .dt_id = TEGRA20_CLK_SPDIF_IN, .present = true },
        [tegra_clk_sdmmc1] = { .dt_id = TEGRA20_CLK_SDMMC1, .present = true },

diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index 455502a42b20878622f646d8f7f1f4246643995d..40ffab0f94e1058381c000517abaa0ee5869dadd 100644 (file)
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -788,6 +788,7 @@ static struct tegra_clk tegra30_clks[tegra_clk_max] __initdata = {
        [tegra_clk_extern3] = { .dt_id = TEGRA30_CLK_EXTERN3, .present = true },
        [tegra_clk_disp1] = { .dt_id = TEGRA30_CLK_DISP1, .present = true },
        [tegra_clk_disp2] = { .dt_id = TEGRA30_CLK_DISP2, .present = true },
+       [tegra_clk_ahbdma] = { .dt_id = TEGRA30_CLK_AHBDMA, .present = true },
        [tegra_clk_apbdma] = { .dt_id = TEGRA30_CLK_APBDMA, .present = true },
        [tegra_clk_rtc] = { .dt_id = TEGRA30_CLK_RTC, .present = true },
        [tegra_clk_timer] = { .dt_id = TEGRA30_CLK_TIMER, .present = true },