]> git.ipfire.org Git - thirdparty/binutils-gdb.git/commitdiff
RISC-V: Add support for Zcmop extension
authorXiao Zeng <zengxiao@eswincomputing.com>
Wed, 12 Jun 2024 01:28:18 +0000 (09:28 +0800)
committerNelson Chu <nelson@rivosinc.com>
Tue, 6 Aug 2024 05:36:21 +0000 (13:36 +0800)
This implements the Zcmop (Compressed Zimop) extension, as of version 1.0.

View detailed information in:
<https://github.com/riscv/riscv-isa-manual/blob/main/src/zimop.adoc>

The Zcmop extension requires the Zca extension.

bfd/ChangeLog:

* elfxx-riscv.c (riscv_multi_subset_supports): Handle Zcmop.
(riscv_multi_subset_supports_ext): Ditto.

gas/ChangeLog:

* NEWS: Updated.
* testsuite/gas/riscv/march-help.l: Ditto.
* testsuite/gas/riscv/zcmop.d: New test.
* testsuite/gas/riscv/zcmop.s: New test.

include/ChangeLog:

* opcode/riscv-opc.h (DECLARE_INSN): New declarations for Zcmop.
(MATCH_C_MOP_1, MATCH_C_MOP_3, MATCH_C_MOP_5, MATCH_C_MOP_7,
MATCH_C_MOP_9, MATCH_C_MOP_11, MATCH_C_MOP_13, MATCH_C_MOP_15): Define.
(MASK_C_MOP_1, MASK_C_MOP_3, MASK_C_MOP_5, MASK_C_MOP_7,
MASK_C_MOP_9, MASK_C_MOP_11, MASK_C_MOP_13, MASK_C_MOP_15): Ditto.
* opcode/riscv.h (enum riscv_insn_class): Add INSN_CLASS_ZCMOP.

opcodes/ChangeLog:

* riscv-opc.c: Add Zcmop instructions.

bfd/elfxx-riscv.c
gas/NEWS
gas/testsuite/gas/riscv/imply.d
gas/testsuite/gas/riscv/imply.s
gas/testsuite/gas/riscv/march-help.l
gas/testsuite/gas/riscv/zcmop.d [new file with mode: 0644]
gas/testsuite/gas/riscv/zcmop.s [new file with mode: 0644]
include/opcode/riscv-opc.h
include/opcode/riscv.h
opcodes/riscv-opc.c

index 164a11c4cea46953b433170bd2f6e1ee5ff7e241..eee8114858ad828823d9c6a559553e12ffecc6b0 100644 (file)
@@ -1213,6 +1213,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
   {"zcd", "+d,+zca", check_implicit_always},
   {"zcf", "+f,+zca", check_implicit_always},
   {"zcmp", "+zca", check_implicit_always},
+  {"zcmop", "+zca", check_implicit_always},
 
   {"shcounterenw", "+h", check_implicit_always},
   {"shgatpa", "+h", check_implicit_always},
@@ -1421,6 +1422,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
   {"zcb",              ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
   {"zcf",              ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
   {"zcd",              ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
+  {"zcmop",            ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
   {"zcmp",             ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
   {NULL, 0, 0, 0, 0}
 };
@@ -2711,6 +2713,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
     case INSN_CLASS_ZCB_AND_ZMMUL:
       return (riscv_subset_supports (rps, "zcb")
              && riscv_subset_supports (rps, "zmmul"));
+    case INSN_CLASS_ZCMOP:
+      return riscv_subset_supports (rps, "zcmop");
     case INSN_CLASS_ZCMP:
       return riscv_subset_supports (rps, "zcmp");
     case INSN_CLASS_SVINVAL:
@@ -2987,6 +2991,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
       return _("zcb' and `zbb");
     case INSN_CLASS_ZCB_AND_ZMMUL:
       return _("zcb' and `zmmul', or `zcb' and `m");
+    case INSN_CLASS_ZCMOP:
+      return "zcmop";
     case INSN_CLASS_ZCMP:
       return "zcmp";
     case INSN_CLASS_SVINVAL:
index 96077f8664ddd719e142a80fa81a83360515a6f7..e0484bcd14ba1d18ff67b42c023f4d3723eb151e 100644 (file)
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -1,6 +1,6 @@
 -*- text -*-
 
-* Add support for RISC-V Zimop extension with version 1.0.
+* Add support for RISC-V Zimop, Zcmop extensions with version 1.0.
 
 Changes in 2.43:
 
index 0c726d3ab79f6cf8824259d32a115eddd70bb955..88b8c46bb897889954cc993ca64807a54d089b4a 100644 (file)
@@ -44,6 +44,7 @@ SYMBOL TABLE:
 [0-9a-f]+ l       .text        0+000 \$xrv32i2p1_f2p2_d2p2_zicsr2p0_zca1p0_zcd1p0
 [0-9a-f]+ l       .text        0+000 \$xrv32i2p1_f2p2_zicsr2p0_zca1p0_zcf1p0
 [0-9a-f]+ l       .text        0+000 \$xrv32i2p1_zca1p0_zcmp1p0
+[0-9a-f]+ l       .text        0+000 \$xrv32i2p1_zca1p0_zcmop1p0
 [0-9a-f]+ l       .text        0+000 \$xrv32i2p1_h1p0_zicsr2p0_shcounterenw1p0
 [0-9a-f]+ l       .text        0+000 \$xrv32i2p1_h1p0_zicsr2p0_shgatpa1p0
 [0-9a-f]+ l       .text        0+000 \$xrv32i2p1_h1p0_zicsr2p0_shtvala1p0
index 8eca66f7a893485f6047f4bafe0b500558f053b3..dabb08d8c8b25ed7801c6312dbe4c1f6ce0c3ee6 100644 (file)
@@ -47,6 +47,7 @@ imply zcb
 imply zcd
 imply zcf
 imply zcmp
+imply zcmop
 
 imply shcounterenw
 imply shgatpa
index cb8590a37a879263a69d4526423747ea1b6200b2..054c2e9667d18556eddc40c8fde519185a4d8796 100644 (file)
@@ -102,6 +102,7 @@ All available -march extensions for RISC-V:
        zcb                                     1.0
        zcf                                     1.0
        zcd                                     1.0
+       zcmop                                   1.0
        zcmp                                    1.0
        shcounterenw                            1.0
        shgatpa                                 1.0
diff --git a/gas/testsuite/gas/riscv/zcmop.d b/gas/testsuite/gas/riscv/zcmop.d
new file mode 100644 (file)
index 0000000..5f608c6
--- /dev/null
@@ -0,0 +1,16 @@
+#as: -march=rv64i_zcmop
+#objdump: -d
+
+.*:[   ]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[      ]+[0-9a-f]+:[   ]+6081[         ]+c.mop.1
+[      ]+[0-9a-f]+:[   ]+6181[         ]+c.mop.3
+[      ]+[0-9a-f]+:[   ]+6281[         ]+c.mop.5
+[      ]+[0-9a-f]+:[   ]+6381[         ]+c.mop.7
+[      ]+[0-9a-f]+:[   ]+6481[         ]+c.mop.9
+[      ]+[0-9a-f]+:[   ]+6581[         ]+c.mop.11
+[      ]+[0-9a-f]+:[   ]+6681[         ]+c.mop.13
+[      ]+[0-9a-f]+:[   ]+6781[         ]+c.mop.15
diff --git a/gas/testsuite/gas/riscv/zcmop.s b/gas/testsuite/gas/riscv/zcmop.s
new file mode 100644 (file)
index 0000000..4b02e69
--- /dev/null
@@ -0,0 +1,10 @@
+target:
+       # c.mop.n
+       c.mop.1
+       c.mop.3
+       c.mop.5
+       c.mop.7
+       c.mop.9
+       c.mop.11
+       c.mop.13
+       c.mop.15
index 9ef9c6f7b9f89fab9357784dc5dcd65c07d1326f..22e63baf2e3430d45a80a2738295a50304db5925 100644 (file)
 #define MASK_C_NOT 0xfc7f
 #define MATCH_C_MUL 0x9c41
 #define MASK_C_MUL 0xfc63
+/* Zcmop instructions.  */
+#define MATCH_C_MOP_1 0x6081
+#define MASK_C_MOP_1 0xffff
+#define MATCH_C_MOP_3 0x6181
+#define MASK_C_MOP_3 0xffff
+#define MATCH_C_MOP_5 0x6281
+#define MASK_C_MOP_5 0xffff
+#define MATCH_C_MOP_7 0x6381
+#define MASK_C_MOP_7 0xffff
+#define MATCH_C_MOP_9 0x6481
+#define MASK_C_MOP_9 0xffff
+#define MATCH_C_MOP_11 0x6581
+#define MASK_C_MOP_11 0xffff
+#define MATCH_C_MOP_13 0x6681
+#define MASK_C_MOP_13 0xffff
+#define MATCH_C_MOP_15 0x6781
+#define MASK_C_MOP_15 0xffff
 /* Zcmp instructions.  */
 #define MATCH_CM_PUSH 0xb802
 #define MASK_CM_PUSH 0xff03
@@ -4213,6 +4230,15 @@ DECLARE_INSN(c_lhu, MATCH_C_LHU, MASK_C_LHU)
 DECLARE_INSN(c_lh, MATCH_C_LH, MASK_C_LH)
 DECLARE_INSN(c_sb, MATCH_C_SB, MASK_C_SB)
 DECLARE_INSN(c_sh, MATCH_C_SH, MASK_C_SH)
+/* Zcmop instructions.  */
+DECLARE_INSN(c_mop_1, MATCH_C_MOP_1, MASK_C_MOP_1)
+DECLARE_INSN(c_mop_3, MATCH_C_MOP_3, MASK_C_MOP_3)
+DECLARE_INSN(c_mop_5, MATCH_C_MOP_5, MASK_C_MOP_5)
+DECLARE_INSN(c_mop_7, MATCH_C_MOP_7, MASK_C_MOP_7)
+DECLARE_INSN(c_mop_9, MATCH_C_MOP_9, MASK_C_MOP_9)
+DECLARE_INSN(c_mop_11, MATCH_C_MOP_11, MASK_C_MOP_11)
+DECLARE_INSN(c_mop_13, MATCH_C_MOP_13, MASK_C_MOP_13)
+DECLARE_INSN(c_mop_15, MATCH_C_MOP_15, MASK_C_MOP_15)
 /* Zcmp instructions.  */
 DECLARE_INSN(cm_push, MATCH_CM_PUSH, MASK_CM_PUSH)
 DECLARE_INSN(cm_pop, MATCH_CM_POP, MASK_CM_POP)
index 6793d99ce8e72ddeaac694b6cfcade57765fc376..9ccf0ec245421faff1164bdc9d3abf9892842de9 100644 (file)
@@ -487,6 +487,7 @@ enum riscv_insn_class
   INSN_CLASS_ZCB_AND_ZBA,
   INSN_CLASS_ZCB_AND_ZBB,
   INSN_CLASS_ZCB_AND_ZMMUL,
+  INSN_CLASS_ZCMOP,
   INSN_CLASS_ZCMP,
   INSN_CLASS_SVINVAL,
   INSN_CLASS_ZICBOM,
index 7e32627349171a19b9ff66b31c1c821a4432d14d..e6831bda9fdd101911097e21b09087b58ae633d2 100644 (file)
@@ -2171,6 +2171,16 @@ const struct riscv_opcode riscv_opcodes[] =
 {"c.zext.b",   0, INSN_CLASS_ZCB, "Cs",  MATCH_C_ZEXT_B, MASK_C_ZEXT_B, match_opcode, 0 },
 {"c.sext.w",  64, INSN_CLASS_ZCB, "d",  MATCH_C_ADDIW, MASK_C_ADDIW|MASK_RVC_IMM, match_rd_nonzero, INSN_ALIAS },
 
+/* Zcmop instructions.  */
+{"c.mop.1",     0,  INSN_CLASS_ZCMOP, "",  MATCH_C_MOP_1,  MASK_C_MOP_1, match_opcode, 0 },
+{"c.mop.3",     0,  INSN_CLASS_ZCMOP, "",  MATCH_C_MOP_3,  MASK_C_MOP_3, match_opcode, 0 },
+{"c.mop.5",     0,  INSN_CLASS_ZCMOP, "",  MATCH_C_MOP_5,  MASK_C_MOP_5, match_opcode, 0 },
+{"c.mop.7",     0,  INSN_CLASS_ZCMOP, "",  MATCH_C_MOP_7,  MASK_C_MOP_7, match_opcode, 0 },
+{"c.mop.9",     0,  INSN_CLASS_ZCMOP, "",  MATCH_C_MOP_9,  MASK_C_MOP_9, match_opcode, 0 },
+{"c.mop.11",    0,  INSN_CLASS_ZCMOP, "",  MATCH_C_MOP_11, MASK_C_MOP_11, match_opcode, 0 },
+{"c.mop.13",    0,  INSN_CLASS_ZCMOP, "",  MATCH_C_MOP_13, MASK_C_MOP_13, match_opcode, 0 },
+{"c.mop.15",    0,  INSN_CLASS_ZCMOP, "",  MATCH_C_MOP_15, MASK_C_MOP_15, match_opcode, 0 },
+
 /* Zcmp instructions.  */
 {"cm.push",    0,  INSN_CLASS_ZCMP, "{Wcr},Wcp",  MATCH_CM_PUSH, MASK_CM_PUSH, match_opcode, 0 },
 {"cm.pop",     0,  INSN_CLASS_ZCMP, "{Wcr},Wcp",  MATCH_CM_POP, MASK_CM_POP, match_opcode, 0 },