]> git.ipfire.org Git - thirdparty/u-boot.git/commitdiff
arm: zynq: Align model name with DT
authorMichal Simek <michal.simek@xilinx.com>
Mon, 27 May 2019 08:13:34 +0000 (10:13 +0200)
committerMichal Simek <michal.simek@xilinx.com>
Tue, 4 Jun 2019 12:20:53 +0000 (14:20 +0200)
All qspi configurations are marked as MINI QSPI which is wrong.
Use model property to distinguish different configurations.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
arch/arm/dts/zynq-cse-qspi-parallel.dts
arch/arm/dts/zynq-cse-qspi-single.dts
arch/arm/dts/zynq-cse-qspi-stacked.dts
arch/arm/dts/zynq-cse-qspi-x1-single.dts
arch/arm/dts/zynq-cse-qspi-x1-stacked.dts
arch/arm/dts/zynq-cse-qspi-x2-single.dts
arch/arm/dts/zynq-cse-qspi-x2-stacked.dts

index 7c90624ddb80ffeffa32c72b9f3f49d61f5278e8..12d8e801e293dbb72c782fccad6172e886d28e07 100644 (file)
@@ -7,6 +7,10 @@
 
 #include "zynq-cse-qspi.dtsi"
 
+/ {
+       model = "Zynq CSE QSPI PARALLEL Board";
+};
+
 &qspi {
        is-dual = <1>;
 };
index 0d680dfc06883f0562ab1d60d73b272415bd061f..ac6982a74e258930a6b4e60df8302a2650cb96aa 100644 (file)
@@ -7,6 +7,10 @@
 
 #include "zynq-cse-qspi.dtsi"
 
+/ {
+       model = "Zynq CSE QSPI SINGLE Board";
+};
+
 &flash0 {
        spi-rx-bus-width = <4>;
 };
index 5777049dd83af90e6db95372cc9c9c9367b9b344..e1b791ae73231d42b24a4c4b3ac274f14da6476f 100644 (file)
@@ -7,6 +7,10 @@
 
 #include "zynq-cse-qspi.dtsi"
 
+/ {
+       model = "Zynq CSE QSPI STACKED Board";
+};
+
 &qspi {
        is-dual = <0>;
        is-stacked = <1>;
index 8d5fd0ccfb7b01b96373fea350ce61bb800f9e4b..c14fb422b7fd342df23f34c84ca5f06cb624f4a4 100644 (file)
@@ -7,6 +7,10 @@
 
 #include "zynq-cse-qspi.dtsi"
 
+/ {
+       model = "Zynq CSE QSPI X1 SINGLE Board";
+};
+
 &flash0 {
        spi-rx-bus-width = <1>;
 };
index 5166341904a4830f46330b4226b00612878c4f0b..4f0a09e80bbb4b686fc39570944abfef1d7df348 100644 (file)
@@ -7,6 +7,10 @@
 
 #include "zynq-cse-qspi.dtsi"
 
+/ {
+       model = "Zynq CSE QSPI X1 STACKED Board";
+};
+
 &qspi {
        is-dual = <0>;
        is-stacked = <1>;
index ba0418766b4cfd5e0fa774a38061c22f61e0f017..11be06385da20db2c1c4bad782d2a4223daf5756 100644 (file)
@@ -7,6 +7,10 @@
 
 #include "zynq-cse-qspi.dtsi"
 
+/ {
+       model = "Zynq CSE QSPI X2 SINGLE Board";
+};
+
 &flash0 {
        spi-rx-bus-width = <2>;
 };
index 87d8891f9dcc17abef41349911b044373d85da51..3dc3fcc4bd10fa49db5131d5feef902eb81df92d 100644 (file)
@@ -7,6 +7,10 @@
 
 #include "zynq-cse-qspi.dtsi"
 
+/ {
+       model = "Zynq CSE QSPI X2 STACKED Board";
+};
+
 &qspi {
        is-dual = <0>;
        is-stacked = <1>;