aarch64: Add support for FEAT_SSVE_FEXPA

diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 59d950663a87274144cfced85ebbeae0af137735..11ee6c8af37ba7853faa3ec4d5b7f8f2a46f74f6 100644 (file)
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -10898,6 +10898,7 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
   {"sve2p2",           AARCH64_FEATURE (SVE2p2), AARCH64_FEATURE (SVE2p1)},
   {"sme2p2",           AARCH64_FEATURE (SME2p2), AARCH64_FEATURE (SME2p1)},
   {"gcie",             AARCH64_FEATURE (GCIE), AARCH64_NO_FEATURES},
+  {"ssve-fexpa",       AARCH64_FEATURE (SSVE_FEXPA), AARCH64_FEATURE (SME2)},
   {"sme-tmop",         AARCH64_FEATURE (SME_TMOP), AARCH64_FEATURE (SME2)},
   {"sme-mop4",         AARCH64_FEATURE (SME_MOP4), AARCH64_FEATURE (SME2)},
   {NULL,               AARCH64_NO_FEATURES, AARCH64_NO_FEATURES},
@@ -10914,6 +10915,8 @@ struct aarch64_virtual_dependency_table
 static const struct aarch64_virtual_dependency_table aarch64_dependencies[] = {
   {AARCH64_FEATURE (SVE2), AARCH64_FEATURE (SVE2_SSVE_AES)},
   {AARCH64_FEATURE (SSVE_AES), AARCH64_FEATURE (SVE2_SSVE_AES)},
+  {AARCH64_FEATURE (SVE), AARCH64_FEATURE (SVE_SSVE_FEXPA)},
+  {AARCH64_FEATURE (SSVE_FEXPA), AARCH64_FEATURE (SVE_SSVE_FEXPA)},
   {AARCH64_FEATURES (2, FP8FMA, SVE2), AARCH64_FEATURE (FP8FMA_SVE)},
   {AARCH64_FEATURE (SSVE_FP8FMA), AARCH64_FEATURE (FP8FMA_SVE)},
   {AARCH64_FEATURES (2, FP8DOT4, SVE2), AARCH64_FEATURE (FP8DOT4_SVE)},

diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
index 2f95f91a66eb82aa00b95910d48a180fa985c7d5..39e1e8cd613efcd75f65b8b879d66ee533938fbf 100644 (file)
--- a/gas/doc/c-aarch64.texi
+++ b/gas/doc/c-aarch64.texi
@@ -323,6 +323,8 @@ automatically cause those extensions to be disabled.
  @tab Enable Speculative Store Bypassing Safe state read and write.
 @item @code{ssve-aes} @tab @code{sme2}, @code{sve-aes}
  @tab Enable SVE AES instructions in streaming mode.
+@item @code{ssve-fexpa} @tab @code{sme2}
+ @tab Enable the SVE FEXPA instruction in streaming mode.
 @item @code{ssve-fp8dot2} @tab @code{sme2}, @code{fp8}
  @tab Enable the Streaming SVE FP8 2-way dot product instructions.
 @item @code{ssve-fp8dot4} @tab @code{sme2}, @code{fp8}

diff --git a/gas/testsuite/gas/aarch64/sve-fexpa.d b/gas/testsuite/gas/aarch64/sve-fexpa.d
new file mode 100644 (file)
index 0000000..c47c274
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve-fexpa.d
@@ -0,0 +1,19 @@
+#as: -march=armv8-a+sve
+#as: -march=armv8-a+ssve-fexpa
+#objdump: -dr
+
+.*:     file format .*
+
+
+Disassembly of section \.text:
+
+0+ <\.text>:
+ *[0-9a-f]+:   0460b800        fexpa   z0\.h, z0\.h
+ *[0-9a-f]+:   0460b81f        fexpa   z31\.h, z0\.h
+ *[0-9a-f]+:   0460bbe0        fexpa   z0\.h, z31\.h
+ *[0-9a-f]+:   04a0b800        fexpa   z0\.s, z0\.s
+ *[0-9a-f]+:   04a0b81f        fexpa   z31\.s, z0\.s
+ *[0-9a-f]+:   04a0bbe0        fexpa   z0\.s, z31\.s
+ *[0-9a-f]+:   04e0b800        fexpa   z0\.d, z0\.d
+ *[0-9a-f]+:   04e0b81f        fexpa   z31\.d, z0\.d
+ *[0-9a-f]+:   04e0bbe0        fexpa   z0\.d, z31\.d

diff --git a/gas/testsuite/gas/aarch64/sve-fexpa.s b/gas/testsuite/gas/aarch64/sve-fexpa.s
new file mode 100644 (file)
index 0000000..3018655
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve-fexpa.s
@@ -0,0 +1,9 @@
+       fexpa   z0.h, z0.h
+       fexpa   z31.h, z0.h
+       fexpa   z0.h, z31.h
+       fexpa   z0.s, z0.s
+       fexpa   z31.s, z0.s
+       fexpa   z0.s, z31.s
+       fexpa   z0.d, z0.d
+       fexpa   z31.d, z0.d
+       fexpa   z0.d, z31.d

diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index f3c6249afdb93d764560cc352e8024f10b88a1fc..5af991adb9b8cea20768eb332e27e7a1d51cb56c 100644 (file)
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -253,6 +253,8 @@ enum aarch64_feature_bit {
   AARCH64_FEATURE_PoPS,
   /* GICv5 (Generic Interrupt Controller) CPU Interface Extension.  */
   AARCH64_FEATURE_GCIE,
+  /* SVE FEXPA instruction in streaming mode.  */
+  AARCH64_FEATURE_SSVE_FEXPA,
   /* SME TMOP instructions.  */
   AARCH64_FEATURE_SME_TMOP,
   /* SME MOP4 instructions.  */
@@ -262,6 +264,8 @@ enum aarch64_feature_bit {
      by either of two (or more) sets of command line flags.  */
   /* +sve2 or +ssve-aes */
   AARCH64_FEATURE_SVE2_SSVE_AES,
+  /* +sve or +ssve-fexpa */
+  AARCH64_FEATURE_SVE_SSVE_FEXPA,
   /* +fp8fma+sve or +ssve-fp8fma  */
   AARCH64_FEATURE_FP8FMA_SVE,
   /* +fp8dot4+sve or +ssve-fp8dot4  */

diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 4f17226674cf0f29111c1345aa1b57c5a2338d47..90d79660e7a4b8711dead7159b0479b1d451c19e 100644 (file)
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -3031,6 +3031,8 @@ static const aarch64_feature_set aarch64_feature_sve2p2_sme2p2 =
   AARCH64_FEATURE (SVE2p2_SME2p2);
 static const aarch64_feature_set aarch64_feature_gcie =
   AARCH64_FEATURE (GCIE);
+static const aarch64_feature_set aarch64_feature_sve_ssve_fexpa =
+  AARCH64_FEATURE (SVE_SSVE_FEXPA);
 static const aarch64_feature_set aarch64_feature_sme_tmop =
   AARCH64_FEATURE (SME_TMOP);
 static const aarch64_feature_set aarch64_feature_sme_tmop_b16b16 =
@@ -3166,6 +3168,7 @@ static const aarch64_feature_set aarch64_feature_sme_mop4_i16i64 =
 #define SVE_SME2p2     &aarch64_feature_sve_sme2p2
 #define SVE2p2_SME2p2  &aarch64_feature_sve2p2_sme2p2
 #define GCIE           &aarch64_feature_gcie
+#define SVE_SSVE_FEXPA &aarch64_feature_sve_ssve_fexpa
 #define SME_TMOP       &aarch64_feature_sme_tmop
 #define SME_TMOP_B16B16        &aarch64_feature_sme_tmop_b16b16
 #define SME_TMOP_F16F16        &aarch64_feature_sme_tmop_f16f16
@@ -3468,6 +3471,9 @@ static const aarch64_feature_set aarch64_feature_sme_mop4_i16i64 =
     F_STRICT | FLAGS, 0, TIED, NULL }
 #define GCIE_INSN(NAME,OPCODE,MASK,OPS,QUALS,FLAGS) \
   { NAME, OPCODE, MASK, ic_system, 0, GCIE, OPS, QUALS, FLAGS, 0, 0, NULL }
+#define _SVE_SSVE_FEXPA_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
+  { NAME, OPCODE, MASK, CLASS, OP, SVE_SSVE_FEXPA, OPS, QUALS, \
+    FLAGS | F_STRICT, 0, TIED, NULL }
 #define SME_TMOP_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS,TIED) \
   { NAME, OPCODE, MASK, CLASS, 0, SME_TMOP, OPS, QUALS, \
     FLAGS | F_STRICT, 0, TIED, NULL }
@@ -5248,7 +5254,7 @@ const struct aarch64_opcode aarch64_opcode_table[] =
   _SVE_INSNC ("fdiv", 0x650d8000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 2),
   _SVE_INSNC ("fdivr", 0x650c8000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 2),
   _SVE_INSN ("fdup", 0x2539c000, 0xff3fe000, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_FPIMM8), OP_SVE_VU_HSD, F_HAS_ALIAS, 0),
-  _SVE_INSN ("fexpa", 0x0420b800, 0xff3ffc00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Zn), OP_SVE_VV_HSD, 0, 0),
+  _SVE_SSVE_FEXPA_INSN ("fexpa", 0x0420b800, 0xff3ffc00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Zn), OP_SVE_VV_HSD, 0, 0),
   _SVE_INSNC ("fmad", 0x65208000, 0xff20e000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zm_5, SVE_Za_16), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 0),
   _SVE_INSNC ("fmax", 0x65068000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 2),
   _SVE_INSNC ("fmax", 0x651e8000, 0xff3fe3c0, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_I1_ZERO_ONE), OP_SVE_VMVU_HSD, 0, C_SCAN_MOVPRFX, 2),