]> git.ipfire.org Git - thirdparty/kernel/stable-queue.git/commitdiff
Fixes for 6.15
authorSasha Levin <sashal@kernel.org>
Wed, 2 Jul 2025 03:03:32 +0000 (23:03 -0400)
committerSasha Levin <sashal@kernel.org>
Wed, 2 Jul 2025 03:03:32 +0000 (23:03 -0400)
Signed-off-by: Sasha Levin <sashal@kernel.org>
15 files changed:
queue-6.15/arm64-dts-qcom-commonize-x1-crd-dtsi.patch [new file with mode: 0644]
queue-6.15/arm64-dts-qcom-x1-crd-fix-vreg_l2j_1p2-voltage.patch [new file with mode: 0644]
queue-6.15/arm64-dts-qcom-x1e78100-t14s-fix-missing-hid-supplie.patch [new file with mode: 0644]
queue-6.15/arm64-dts-qcom-x1e78100-t14s-mark-l12b-and-l15b-alwa.patch [new file with mode: 0644]
queue-6.15/arm64-dts-qcom-x1e80100-crd-mark-l12b-and-l15b-alway.patch [new file with mode: 0644]
queue-6.15/crypto-powerpc-poly1305-add-depends-on-broken-for-no.patch [new file with mode: 0644]
queue-6.15/drm-amd-display-add-early-8b-10b-channel-equalizatio.patch [new file with mode: 0644]
queue-6.15/drm-amd-display-export-full-brightness-range-to-user.patch [new file with mode: 0644]
queue-6.15/drm-amd-display-fix-default-dc-and-ac-levels.patch [new file with mode: 0644]
queue-6.15/drm-amd-display-get-lttpr-ieee-oui-device-id-from-cl.patch [new file with mode: 0644]
queue-6.15/drm-amd-display-only-read-acpi-backlight-caps-once.patch [new file with mode: 0644]
queue-6.15/drm-amd-display-optimize-custom-brightness-curve.patch [new file with mode: 0644]
queue-6.15/drm-amdgpu-mes-add-missing-locking-in-helper-functio.patch [new file with mode: 0644]
queue-6.15/sched_ext-make-scx_group_set_weight-always-update-tg.patch [new file with mode: 0644]
queue-6.15/series

diff --git a/queue-6.15/arm64-dts-qcom-commonize-x1-crd-dtsi.patch b/queue-6.15/arm64-dts-qcom-commonize-x1-crd-dtsi.patch
new file mode 100644 (file)
index 0000000..8420ca0
--- /dev/null
@@ -0,0 +1,2607 @@
+From 8de6b57070e6b1de271026847f64e858376cbafc Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 3 Feb 2025 15:43:24 +0100
+Subject: arm64: dts: qcom: Commonize X1 CRD DTSI
+
+From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
+
+[ Upstream commit fbf5e007588f3f2bace84309b4a0d428ad619322 ]
+
+Certain X1 SKUs vary very noticeably, but the CRDs based on them don't.
+
+Commonize the existing X1E80100 DTSI to allow reuse.
+
+Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
+Link: https://lore.kernel.org/r/20250203-topic-x1p4_dts-v2-5-72cd4cdc767b@oss.qualcomm.com
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/arm64/boot/dts/qcom/x1-crd.dtsi      | 1275 +++++++++++++++++++++
+ arch/arm64/boot/dts/qcom/x1e80100-crd.dts | 1270 +-------------------
+ arch/arm64/boot/dts/qcom/x1e80100.dtsi    |    2 +-
+ 3 files changed, 1279 insertions(+), 1268 deletions(-)
+ create mode 100644 arch/arm64/boot/dts/qcom/x1-crd.dtsi
+
+diff --git a/arch/arm64/boot/dts/qcom/x1-crd.dtsi b/arch/arm64/boot/dts/qcom/x1-crd.dtsi
+new file mode 100644
+index 0000000000000..296b41409ad17
+--- /dev/null
++++ b/arch/arm64/boot/dts/qcom/x1-crd.dtsi
+@@ -0,0 +1,1275 @@
++// SPDX-License-Identifier: BSD-3-Clause
++/*
++ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
++ */
++
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/input/gpio-keys.h>
++#include <dt-bindings/input/input.h>
++#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
++#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
++
++#include "x1e80100-pmics.dtsi"
++
++/ {
++      model = "Qualcomm Technologies, Inc. X1E80100 CRD";
++      compatible = "qcom,x1e80100-crd", "qcom,x1e80100";
++
++      aliases {
++              serial0 = &uart21;
++      };
++
++      wcd938x: audio-codec {
++              compatible = "qcom,wcd9385-codec";
++
++              pinctrl-names = "default";
++              pinctrl-0 = <&wcd_default>;
++
++              qcom,micbias1-microvolt = <1800000>;
++              qcom,micbias2-microvolt = <1800000>;
++              qcom,micbias3-microvolt = <1800000>;
++              qcom,micbias4-microvolt = <1800000>;
++              qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>;
++              qcom,mbhc-headset-vthreshold-microvolt = <1700000>;
++              qcom,mbhc-headphone-vthreshold-microvolt = <50000>;
++              qcom,rx-device = <&wcd_rx>;
++              qcom,tx-device = <&wcd_tx>;
++
++              reset-gpios = <&tlmm 191 GPIO_ACTIVE_LOW>;
++
++              vdd-buck-supply = <&vreg_l15b_1p8>;
++              vdd-rxtx-supply = <&vreg_l15b_1p8>;
++              vdd-io-supply = <&vreg_l15b_1p8>;
++              vdd-mic-bias-supply = <&vreg_bob1>;
++
++              #sound-dai-cells = <1>;
++      };
++
++      chosen {
++              stdout-path = "serial0:115200n8";
++      };
++
++      gpio-keys {
++              compatible = "gpio-keys";
++
++              pinctrl-0 = <&hall_int_n_default>;
++              pinctrl-names = "default";
++
++              switch-lid {
++                      gpios = <&tlmm 92 GPIO_ACTIVE_LOW>;
++                      linux,input-type = <EV_SW>;
++                      linux,code = <SW_LID>;
++                      wakeup-source;
++                      wakeup-event-action = <EV_ACT_DEASSERTED>;
++              };
++      };
++
++      pmic-glink {
++              compatible = "qcom,x1e80100-pmic-glink",
++                           "qcom,sm8550-pmic-glink",
++                           "qcom,pmic-glink";
++              #address-cells = <1>;
++              #size-cells = <0>;
++              orientation-gpios = <&tlmm 121 GPIO_ACTIVE_HIGH>,
++                                  <&tlmm 123 GPIO_ACTIVE_HIGH>,
++                                  <&tlmm 125 GPIO_ACTIVE_HIGH>;
++
++              /* Left-side rear port */
++              connector@0 {
++                      compatible = "usb-c-connector";
++                      reg = <0>;
++                      power-role = "dual";
++                      data-role = "dual";
++
++                      ports {
++                              #address-cells = <1>;
++                              #size-cells = <0>;
++
++                              port@0 {
++                                      reg = <0>;
++
++                                      pmic_glink_ss0_hs_in: endpoint {
++                                              remote-endpoint = <&usb_1_ss0_dwc3_hs>;
++                                      };
++                              };
++
++                              port@1 {
++                                      reg = <1>;
++
++                                      pmic_glink_ss0_ss_in: endpoint {
++                                              remote-endpoint = <&usb_1_ss0_qmpphy_out>;
++                                      };
++                              };
++                      };
++              };
++
++              /* Left-side front port */
++              connector@1 {
++                      compatible = "usb-c-connector";
++                      reg = <1>;
++                      power-role = "dual";
++                      data-role = "dual";
++
++                      ports {
++                              #address-cells = <1>;
++                              #size-cells = <0>;
++
++                              port@0 {
++                                      reg = <0>;
++
++                                      pmic_glink_ss1_hs_in: endpoint {
++                                              remote-endpoint = <&usb_1_ss1_dwc3_hs>;
++                                      };
++                              };
++
++                              port@1 {
++                                      reg = <1>;
++
++                                      pmic_glink_ss1_ss_in: endpoint {
++                                              remote-endpoint = <&usb_1_ss1_qmpphy_out>;
++                                      };
++                              };
++                      };
++              };
++
++              /* Right-side port */
++              connector@2 {
++                      compatible = "usb-c-connector";
++                      reg = <2>;
++                      power-role = "dual";
++                      data-role = "dual";
++
++                      ports {
++                              #address-cells = <1>;
++                              #size-cells = <0>;
++
++                              port@0 {
++                                      reg = <0>;
++
++                                      pmic_glink_ss2_hs_in: endpoint {
++                                              remote-endpoint = <&usb_1_ss2_dwc3_hs>;
++                                      };
++                              };
++
++                              port@1 {
++                                      reg = <1>;
++
++                                      pmic_glink_ss2_ss_in: endpoint {
++                                              remote-endpoint = <&usb_1_ss2_qmpphy_out>;
++                                      };
++                              };
++                      };
++              };
++      };
++
++      reserved-memory {
++              linux,cma {
++                      compatible = "shared-dma-pool";
++                      size = <0x0 0x8000000>;
++                      reusable;
++                      linux,cma-default;
++              };
++      };
++
++      sound {
++              compatible = "qcom,x1e80100-sndcard";
++              model = "X1E80100-CRD";
++              audio-routing = "WooferLeft IN", "WSA WSA_SPK1 OUT",
++                              "TweeterLeft IN", "WSA WSA_SPK2 OUT",
++                              "WooferRight IN", "WSA2 WSA_SPK2 OUT",
++                              "TweeterRight IN", "WSA2 WSA_SPK2 OUT",
++                              "IN1_HPHL", "HPHL_OUT",
++                              "IN2_HPHR", "HPHR_OUT",
++                              "AMIC2", "MIC BIAS2",
++                              "VA DMIC0", "MIC BIAS3",
++                              "VA DMIC1", "MIC BIAS3",
++                              "VA DMIC2", "MIC BIAS1",
++                              "VA DMIC3", "MIC BIAS1",
++                              "VA DMIC0", "VA MIC BIAS3",
++                              "VA DMIC1", "VA MIC BIAS3",
++                              "VA DMIC2", "VA MIC BIAS1",
++                              "VA DMIC3", "VA MIC BIAS1",
++                              "TX SWR_INPUT1", "ADC2_OUTPUT";
++
++              wcd-playback-dai-link {
++                      link-name = "WCD Playback";
++
++                      cpu {
++                              sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>;
++                      };
++
++                      codec {
++                              sound-dai = <&wcd938x 0>, <&swr1 0>, <&lpass_rxmacro 0>;
++                      };
++
++                      platform {
++                              sound-dai = <&q6apm>;
++                      };
++              };
++
++              wcd-capture-dai-link {
++                      link-name = "WCD Capture";
++
++                      cpu {
++                              sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>;
++                      };
++
++                      codec {
++                              sound-dai = <&wcd938x 1>, <&swr2 1>, <&lpass_txmacro 0>;
++                      };
++
++                      platform {
++                              sound-dai = <&q6apm>;
++                      };
++              };
++
++              wsa-dai-link {
++                      link-name = "WSA Playback";
++
++                      cpu {
++                              sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>;
++                      };
++
++                      codec {
++                              sound-dai = <&left_woofer>, <&left_tweeter>,
++                                          <&swr0 0>, <&lpass_wsamacro 0>,
++                                          <&right_woofer>, <&right_tweeter>,
++                                          <&swr3 0>, <&lpass_wsa2macro 0>;
++                      };
++
++                      platform {
++                              sound-dai = <&q6apm>;
++                      };
++              };
++
++              va-dai-link {
++                      link-name = "VA Capture";
++
++                      cpu {
++                              sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>;
++                      };
++
++                      codec {
++                              sound-dai = <&lpass_vamacro 0>;
++                      };
++
++                      platform {
++                              sound-dai = <&q6apm>;
++                      };
++              };
++      };
++
++      vreg_edp_3p3: regulator-edp-3p3 {
++              compatible = "regulator-fixed";
++
++              regulator-name = "VREG_EDP_3P3";
++              regulator-min-microvolt = <3300000>;
++              regulator-max-microvolt = <3300000>;
++
++              gpio = <&tlmm 70 GPIO_ACTIVE_HIGH>;
++              enable-active-high;
++
++              pinctrl-0 = <&edp_reg_en>;
++              pinctrl-names = "default";
++
++              regulator-boot-on;
++      };
++
++      vreg_misc_3p3: regulator-misc-3p3 {
++              compatible = "regulator-fixed";
++
++              regulator-name = "VREG_MISC_3P3";
++              regulator-min-microvolt = <3300000>;
++              regulator-max-microvolt = <3300000>;
++
++              gpio = <&pm8550ve_8_gpios 6 GPIO_ACTIVE_HIGH>;
++              enable-active-high;
++
++              pinctrl-names = "default";
++              pinctrl-0 = <&misc_3p3_reg_en>;
++
++              regulator-boot-on;
++              regulator-always-on;
++      };
++
++      vreg_nvme: regulator-nvme {
++              compatible = "regulator-fixed";
++
++              regulator-name = "VREG_NVME_3P3";
++              regulator-min-microvolt = <3300000>;
++              regulator-max-microvolt = <3300000>;
++
++              gpio = <&tlmm 18 GPIO_ACTIVE_HIGH>;
++              enable-active-high;
++
++              pinctrl-names = "default";
++              pinctrl-0 = <&nvme_reg_en>;
++
++              regulator-boot-on;
++      };
++
++      vph_pwr: regulator-vph-pwr {
++              compatible = "regulator-fixed";
++
++              regulator-name = "vph_pwr";
++              regulator-min-microvolt = <3700000>;
++              regulator-max-microvolt = <3700000>;
++
++              regulator-always-on;
++              regulator-boot-on;
++      };
++
++      vreg_wwan: regulator-wwan {
++              compatible = "regulator-fixed";
++
++              regulator-name = "SDX_VPH_PWR";
++              regulator-min-microvolt = <3300000>;
++              regulator-max-microvolt = <3300000>;
++
++              gpio = <&tlmm 221 GPIO_ACTIVE_HIGH>;
++              enable-active-high;
++
++              pinctrl-0 = <&wwan_sw_en>;
++              pinctrl-names = "default";
++
++              regulator-boot-on;
++      };
++};
++
++&apps_rsc {
++      regulators-0 {
++              compatible = "qcom,pm8550-rpmh-regulators";
++              qcom,pmic-id = "b";
++
++              vdd-bob1-supply = <&vph_pwr>;
++              vdd-bob2-supply = <&vph_pwr>;
++              vdd-l1-l4-l10-supply = <&vreg_s4c_1p8>;
++              vdd-l2-l13-l14-supply = <&vreg_bob1>;
++              vdd-l5-l16-supply = <&vreg_bob1>;
++              vdd-l6-l7-supply = <&vreg_bob2>;
++              vdd-l8-l9-supply = <&vreg_bob1>;
++              vdd-l12-supply = <&vreg_s5j_1p2>;
++              vdd-l15-supply = <&vreg_s4c_1p8>;
++              vdd-l17-supply = <&vreg_bob2>;
++
++              vreg_bob1: bob1 {
++                      regulator-name = "vreg_bob1";
++                      regulator-min-microvolt = <3008000>;
++                      regulator-max-microvolt = <3960000>;
++                      regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
++              };
++
++              vreg_bob2: bob2 {
++                      regulator-name = "vreg_bob2";
++                      regulator-min-microvolt = <2504000>;
++                      regulator-max-microvolt = <3008000>;
++                      regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
++              };
++
++              vreg_l1b_1p8: ldo1 {
++                      regulator-name = "vreg_l1b_1p8";
++                      regulator-min-microvolt = <1800000>;
++                      regulator-max-microvolt = <1800000>;
++                      regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
++              };
++
++              vreg_l2b_3p0: ldo2 {
++                      regulator-name = "vreg_l2b_3p0";
++                      regulator-min-microvolt = <3072000>;
++                      regulator-max-microvolt = <3100000>;
++                      regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
++              };
++
++              vreg_l4b_1p8: ldo4 {
++                      regulator-name = "vreg_l4b_1p8";
++                      regulator-min-microvolt = <1800000>;
++                      regulator-max-microvolt = <1800000>;
++                      regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
++              };
++
++              vreg_l5b_3p0: ldo5 {
++                      regulator-name = "vreg_l5b_3p0";
++                      regulator-min-microvolt = <3000000>;
++                      regulator-max-microvolt = <3000000>;
++                      regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
++              };
++
++              vreg_l6b_1p8: ldo6 {
++                      regulator-name = "vreg_l6b_1p8";
++                      regulator-min-microvolt = <1800000>;
++                      regulator-max-microvolt = <2960000>;
++                      regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
++              };
++
++              vreg_l7b_2p8: ldo7 {
++                      regulator-name = "vreg_l7b_2p8";
++                      regulator-min-microvolt = <2800000>;
++                      regulator-max-microvolt = <2800000>;
++                      regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
++              };
++
++              vreg_l8b_3p0: ldo8 {
++                      regulator-name = "vreg_l8b_3p0";
++                      regulator-min-microvolt = <3072000>;
++                      regulator-max-microvolt = <3072000>;
++                      regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
++              };
++
++              vreg_l9b_2p9: ldo9 {
++                      regulator-name = "vreg_l9b_2p9";
++                      regulator-min-microvolt = <2960000>;
++                      regulator-max-microvolt = <2960000>;
++                      regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
++              };
++
++              vreg_l10b_1p8: ldo10 {
++                      regulator-name = "vreg_l10b_1p8";
++                      regulator-min-microvolt = <1800000>;
++                      regulator-max-microvolt = <1800000>;
++                      regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
++              };
++
++              vreg_l12b_1p2: ldo12 {
++                      regulator-name = "vreg_l12b_1p2";
++                      regulator-min-microvolt = <1200000>;
++                      regulator-max-microvolt = <1200000>;
++                      regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
++              };
++
++              vreg_l13b_3p0: ldo13 {
++                      regulator-name = "vreg_l13b_3p0";
++                      regulator-min-microvolt = <3072000>;
++                      regulator-max-microvolt = <3100000>;
++                      regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
++              };
++
++              vreg_l14b_3p0: ldo14 {
++                      regulator-name = "vreg_l14b_3p0";
++                      regulator-min-microvolt = <3072000>;
++                      regulator-max-microvolt = <3072000>;
++                      regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
++              };
++
++              vreg_l15b_1p8: ldo15 {
++                      regulator-name = "vreg_l15b_1p8";
++                      regulator-min-microvolt = <1800000>;
++                      regulator-max-microvolt = <1800000>;
++                      regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
++              };
++
++              vreg_l16b_2p9: ldo16 {
++                      regulator-name = "vreg_l16b_2p9";
++                      regulator-min-microvolt = <2912000>;
++                      regulator-max-microvolt = <2912000>;
++                      regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
++              };
++
++              vreg_l17b_2p5: ldo17 {
++                      regulator-name = "vreg_l17b_2p5";
++                      regulator-min-microvolt = <2504000>;
++                      regulator-max-microvolt = <2504000>;
++                      regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
++              };
++      };
++
++      regulators-1 {
++              compatible = "qcom,pm8550ve-rpmh-regulators";
++              qcom,pmic-id = "c";
++
++              vdd-l1-supply = <&vreg_s5j_1p2>;
++              vdd-l2-supply = <&vreg_s1f_0p7>;
++              vdd-l3-supply = <&vreg_s1f_0p7>;
++              vdd-s4-supply = <&vph_pwr>;
++
++              vreg_s4c_1p8: smps4 {
++                      regulator-name = "vreg_s4c_1p8";
++                      regulator-min-microvolt = <1856000>;
++                      regulator-max-microvolt = <2000000>;
++                      regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
++              };
++
++              vreg_l1c_1p2: ldo1 {
++                      regulator-name = "vreg_l1c_1p2";
++                      regulator-min-microvolt = <1200000>;
++                      regulator-max-microvolt = <1200000>;
++                      regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
++              };
++
++              vreg_l2c_0p8: ldo2 {
++                      regulator-name = "vreg_l2c_0p8";
++                      regulator-min-microvolt = <880000>;
++                      regulator-max-microvolt = <920000>;
++                      regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
++              };
++
++              vreg_l3c_0p8: ldo3 {
++                      regulator-name = "vreg_l3c_0p8";
++                      regulator-min-microvolt = <880000>;
++                      regulator-max-microvolt = <920000>;
++                      regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
++              };
++      };
++
++      regulators-2 {
++              compatible = "qcom,pmc8380-rpmh-regulators";
++              qcom,pmic-id = "d";
++
++              vdd-l1-supply = <&vreg_s1f_0p7>;
++              vdd-l2-supply = <&vreg_s1f_0p7>;
++              vdd-l3-supply = <&vreg_s4c_1p8>;
++              vdd-s1-supply = <&vph_pwr>;
++
++              vreg_l1d_0p8: ldo1 {
++                      regulator-name = "vreg_l1d_0p8";
++                      regulator-min-microvolt = <880000>;
++                      regulator-max-microvolt = <920000>;
++                      regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
++              };
++
++              vreg_l2d_0p9: ldo2 {
++                      regulator-name = "vreg_l2d_0p9";
++                      regulator-min-microvolt = <912000>;
++                      regulator-max-microvolt = <920000>;
++                      regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
++              };
++
++              vreg_l3d_1p8: ldo3 {
++                      regulator-name = "vreg_l3d_1p8";
++                      regulator-min-microvolt = <1800000>;
++                      regulator-max-microvolt = <1800000>;
++                      regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
++              };
++      };
++
++      regulators-3 {
++              compatible = "qcom,pmc8380-rpmh-regulators";
++              qcom,pmic-id = "e";
++
++              vdd-l2-supply = <&vreg_s1f_0p7>;
++              vdd-l3-supply = <&vreg_s5j_1p2>;
++
++              vreg_l2e_0p8: ldo2 {
++                      regulator-name = "vreg_l2e_0p8";
++                      regulator-min-microvolt = <880000>;
++                      regulator-max-microvolt = <920000>;
++                      regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
++              };
++
++              vreg_l3e_1p2: ldo3 {
++                      regulator-name = "vreg_l3e_1p2";
++                      regulator-min-microvolt = <1200000>;
++                      regulator-max-microvolt = <1200000>;
++                      regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
++              };
++      };
++
++      regulators-4 {
++              compatible = "qcom,pmc8380-rpmh-regulators";
++              qcom,pmic-id = "f";
++
++              vdd-l1-supply = <&vreg_s5j_1p2>;
++              vdd-l2-supply = <&vreg_s5j_1p2>;
++              vdd-l3-supply = <&vreg_s5j_1p2>;
++              vdd-s1-supply = <&vph_pwr>;
++
++              vreg_s1f_0p7: smps1 {
++                      regulator-name = "vreg_s1f_0p7";
++                      regulator-min-microvolt = <700000>;
++                      regulator-max-microvolt = <1100000>;
++                      regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
++              };
++
++              vreg_l1f_1p0: ldo1 {
++                      regulator-name = "vreg_l1f_1p0";
++                      regulator-min-microvolt = <1024000>;
++                      regulator-max-microvolt = <1024000>;
++                      regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
++              };
++
++              vreg_l2f_1p0: ldo2 {
++                      regulator-name = "vreg_l2f_1p0";
++                      regulator-min-microvolt = <1024000>;
++                      regulator-max-microvolt = <1024000>;
++                      regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
++              };
++
++              vreg_l3f_1p0: ldo3 {
++                      regulator-name = "vreg_l3f_1p0";
++                      regulator-min-microvolt = <1024000>;
++                      regulator-max-microvolt = <1024000>;
++                      regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
++              };
++      };
++
++      regulators-6 {
++              compatible = "qcom,pm8550ve-rpmh-regulators";
++              qcom,pmic-id = "i";
++
++              vdd-l1-supply = <&vreg_s4c_1p8>;
++              vdd-l2-supply = <&vreg_s5j_1p2>;
++              vdd-l3-supply = <&vreg_s1f_0p7>;
++              vdd-s1-supply = <&vph_pwr>;
++              vdd-s2-supply = <&vph_pwr>;
++
++              vreg_s1i_0p9: smps1 {
++                      regulator-name = "vreg_s1i_0p9";
++                      regulator-min-microvolt = <900000>;
++                      regulator-max-microvolt = <920000>;
++                      regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
++              };
++
++              vreg_s2i_1p0: smps2 {
++                      regulator-name = "vreg_s2i_1p0";
++                      regulator-min-microvolt = <1000000>;
++                      regulator-max-microvolt = <1100000>;
++                      regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
++              };
++
++              vreg_l1i_1p8: ldo1 {
++                      regulator-name = "vreg_l1i_1p8";
++                      regulator-min-microvolt = <1800000>;
++                      regulator-max-microvolt = <1800000>;
++                      regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
++              };
++
++              vreg_l2i_1p2: ldo2 {
++                      regulator-name = "vreg_l2i_1p2";
++                      regulator-min-microvolt = <1200000>;
++                      regulator-max-microvolt = <1200000>;
++                      regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
++              };
++
++              vreg_l3i_0p8: ldo3 {
++                      regulator-name = "vreg_l3i_0p8";
++                      regulator-min-microvolt = <880000>;
++                      regulator-max-microvolt = <920000>;
++                      regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
++              };
++      };
++
++      regulators-7 {
++              compatible = "qcom,pm8550ve-rpmh-regulators";
++              qcom,pmic-id = "j";
++
++              vdd-l1-supply = <&vreg_s1f_0p7>;
++              vdd-l2-supply = <&vreg_s5j_1p2>;
++              vdd-l3-supply = <&vreg_s1f_0p7>;
++              vdd-s5-supply = <&vph_pwr>;
++
++              vreg_s5j_1p2: smps5 {
++                      regulator-name = "vreg_s5j_1p2";
++                      regulator-min-microvolt = <1256000>;
++                      regulator-max-microvolt = <1304000>;
++                      regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
++              };
++
++              vreg_l1j_0p8: ldo1 {
++                      regulator-name = "vreg_l1j_0p8";
++                      regulator-min-microvolt = <880000>;
++                      regulator-max-microvolt = <920000>;
++                      regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
++              };
++
++              vreg_l2j_1p2: ldo2 {
++                      regulator-name = "vreg_l2j_1p2";
++                      regulator-min-microvolt = <1200000>;
++                      regulator-max-microvolt = <1200000>;
++                      regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
++              };
++
++              vreg_l3j_0p8: ldo3 {
++                      regulator-name = "vreg_l3j_0p8";
++                      regulator-min-microvolt = <880000>;
++                      regulator-max-microvolt = <920000>;
++                      regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
++              };
++      };
++};
++
++&gpu {
++      status = "okay";
++};
++
++&i2c0 {
++      clock-frequency = <400000>;
++
++      status = "okay";
++
++      touchpad@15 {
++              compatible = "hid-over-i2c";
++              reg = <0x15>;
++
++              hid-descr-addr = <0x1>;
++              interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>;
++
++              vdd-supply = <&vreg_misc_3p3>;
++              vddl-supply = <&vreg_l12b_1p2>;
++
++              pinctrl-0 = <&tpad_default>;
++              pinctrl-names = "default";
++
++              wakeup-source;
++      };
++
++      keyboard@3a {
++              compatible = "hid-over-i2c";
++              reg = <0x3a>;
++
++              hid-descr-addr = <0x1>;
++              interrupts-extended = <&tlmm 67 IRQ_TYPE_LEVEL_LOW>;
++
++              vdd-supply = <&vreg_misc_3p3>;
++              vddl-supply = <&vreg_l12b_1p2>;
++
++              pinctrl-0 = <&kybd_default>;
++              pinctrl-names = "default";
++
++              wakeup-source;
++      };
++};
++
++&i2c8 {
++      clock-frequency = <400000>;
++
++      status = "okay";
++
++      touchscreen@10 {
++              compatible = "hid-over-i2c";
++              reg = <0x10>;
++
++              hid-descr-addr = <0x1>;
++              interrupts-extended = <&tlmm 51 IRQ_TYPE_LEVEL_LOW>;
++
++              vdd-supply = <&vreg_misc_3p3>;
++              vddl-supply = <&vreg_l15b_1p8>;
++
++              pinctrl-0 = <&ts0_default>;
++              pinctrl-names = "default";
++      };
++};
++
++&lpass_tlmm {
++      spkr_01_sd_n_active: spkr-01-sd-n-active-state {
++              pins = "gpio12";
++              function = "gpio";
++              drive-strength = <16>;
++              bias-disable;
++              output-low;
++      };
++
++      spkr_23_sd_n_active: spkr-23-sd-n-active-state {
++              pins = "gpio13";
++              function = "gpio";
++              drive-strength = <16>;
++              bias-disable;
++              output-low;
++      };
++};
++
++&lpass_vamacro {
++      pinctrl-0 = <&dmic01_default>, <&dmic23_default>;
++      pinctrl-names = "default";
++
++      vdd-micb-supply = <&vreg_l1b_1p8>;
++      qcom,dmic-sample-rate = <4800000>;
++};
++
++&mdss {
++      status = "okay";
++};
++
++&mdss_dp3 {
++      compatible = "qcom,x1e80100-dp";
++      /delete-property/ #sound-dai-cells;
++
++      status = "okay";
++
++      aux-bus {
++              panel {
++                      compatible = "samsung,atna45af01", "samsung,atna33xc20";
++                      enable-gpios = <&pmc8380_3_gpios 4 GPIO_ACTIVE_HIGH>;
++                      power-supply = <&vreg_edp_3p3>;
++
++                      pinctrl-0 = <&edp_bl_en>;
++                      pinctrl-names = "default";
++
++                      port {
++                              edp_panel_in: endpoint {
++                                      remote-endpoint = <&mdss_dp3_out>;
++                              };
++                      };
++              };
++      };
++
++      ports {
++              port@1 {
++                      reg = <1>;
++                      mdss_dp3_out: endpoint {
++                              data-lanes = <0 1 2 3>;
++                              link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
++
++                              remote-endpoint = <&edp_panel_in>;
++                      };
++              };
++      };
++};
++
++&mdss_dp3_phy {
++      vdda-phy-supply = <&vreg_l3j_0p8>;
++      vdda-pll-supply = <&vreg_l2j_1p2>;
++
++      status = "okay";
++};
++
++&pcie4 {
++      perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
++      wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
++
++      pinctrl-0 = <&pcie4_default>;
++      pinctrl-names = "default";
++
++      status = "okay";
++};
++
++&pcie4_phy {
++      vdda-phy-supply = <&vreg_l3i_0p8>;
++      vdda-pll-supply = <&vreg_l3e_1p2>;
++
++      status = "okay";
++};
++
++&pcie5 {
++      perst-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>;
++      wake-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;
++
++      vddpe-3v3-supply = <&vreg_wwan>;
++
++      pinctrl-0 = <&pcie5_default>;
++      pinctrl-names = "default";
++
++      status = "okay";
++};
++
++&pcie5_phy {
++      vdda-phy-supply = <&vreg_l3i_0p8>;
++      vdda-pll-supply = <&vreg_l3e_1p2>;
++
++      status = "okay";
++};
++
++&pcie6a {
++      perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
++      wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
++
++      vddpe-3v3-supply = <&vreg_nvme>;
++
++      pinctrl-names = "default";
++      pinctrl-0 = <&pcie6a_default>;
++
++      status = "okay";
++};
++
++&pcie6a_phy {
++      vdda-phy-supply = <&vreg_l1d_0p8>;
++      vdda-pll-supply = <&vreg_l2j_1p2>;
++
++      status = "okay";
++};
++
++&pm8550ve_8_gpios {
++      misc_3p3_reg_en: misc-3p3-reg-en-state {
++              pins = "gpio6";
++              function = "normal";
++              bias-disable;
++              input-disable;
++              output-enable;
++              drive-push-pull;
++              power-source = <1>; /* 1.8 V */
++              qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>;
++      };
++};
++
++&pmc8380_3_gpios {
++      edp_bl_en: edp-bl-en-state {
++              pins = "gpio4";
++              function = "normal";
++              power-source = <1>; /* 1.8V */
++              input-disable;
++              output-enable;
++      };
++};
++
++&qupv3_0 {
++      status = "okay";
++};
++
++&qupv3_1 {
++      status = "okay";
++};
++
++&qupv3_2 {
++      status = "okay";
++};
++
++&remoteproc_adsp {
++      firmware-name = "qcom/x1e80100/adsp.mbn",
++                      "qcom/x1e80100/adsp_dtb.mbn";
++
++      status = "okay";
++};
++
++&remoteproc_cdsp {
++      firmware-name = "qcom/x1e80100/cdsp.mbn",
++                      "qcom/x1e80100/cdsp_dtb.mbn";
++
++      status = "okay";
++};
++
++&smb2360_0 {
++      status = "okay";
++};
++
++&smb2360_0_eusb2_repeater {
++      vdd18-supply = <&vreg_l3d_1p8>;
++      vdd3-supply = <&vreg_l2b_3p0>;
++};
++
++&smb2360_1 {
++      status = "okay";
++};
++
++&smb2360_1_eusb2_repeater {
++      vdd18-supply = <&vreg_l3d_1p8>;
++      vdd3-supply = <&vreg_l14b_3p0>;
++};
++
++&smb2360_2 {
++      status = "okay";
++};
++
++&smb2360_2_eusb2_repeater {
++      vdd18-supply = <&vreg_l3d_1p8>;
++      vdd3-supply = <&vreg_l8b_3p0>;
++};
++
++&swr0 {
++      status = "okay";
++
++      pinctrl-0 = <&wsa_swr_active>, <&spkr_01_sd_n_active>;
++      pinctrl-names = "default";
++
++      /* WSA8845, Left Woofer */
++      left_woofer: speaker@0,0 {
++              compatible = "sdw20217020400";
++              reg = <0 0>;
++              reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>;
++              #sound-dai-cells = <0>;
++              sound-name-prefix = "WooferLeft";
++              vdd-1p8-supply = <&vreg_l15b_1p8>;
++              vdd-io-supply = <&vreg_l12b_1p2>;
++              qcom,port-mapping = <1 2 3 7 10 13>;
++      };
++
++      /* WSA8845, Left Tweeter */
++      left_tweeter: speaker@0,1 {
++              compatible = "sdw20217020400";
++              reg = <0 1>;
++              reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>;
++              #sound-dai-cells = <0>;
++              sound-name-prefix = "TweeterLeft";
++              vdd-1p8-supply = <&vreg_l15b_1p8>;
++              vdd-io-supply = <&vreg_l12b_1p2>;
++              qcom,port-mapping = <4 5 6 7 11 13>;
++      };
++};
++
++&swr1 {
++      status = "okay";
++
++      /* WCD9385 RX */
++      wcd_rx: codec@0,4 {
++              compatible = "sdw20217010d00";
++              reg = <0 4>;
++              qcom,rx-port-mapping = <1 2 3 4 5>;
++      };
++};
++
++&swr2 {
++      status = "okay";
++
++      /* WCD9385 TX */
++      wcd_tx: codec@0,3 {
++              compatible = "sdw20217010d00";
++              reg = <0 3>;
++              qcom,tx-port-mapping = <2 2 3 4>;
++      };
++};
++
++&swr3 {
++      status = "okay";
++
++      pinctrl-0 = <&wsa2_swr_active>, <&spkr_23_sd_n_active>;
++      pinctrl-names = "default";
++
++      /* WSA8845, Right Woofer */
++      right_woofer: speaker@0,0 {
++              compatible = "sdw20217020400";
++              reg = <0 0>;
++              reset-gpios = <&lpass_tlmm 13 GPIO_ACTIVE_LOW>;
++              #sound-dai-cells = <0>;
++              sound-name-prefix = "WooferRight";
++              vdd-1p8-supply = <&vreg_l15b_1p8>;
++              vdd-io-supply = <&vreg_l12b_1p2>;
++              qcom,port-mapping = <1 2 3 7 10 13>;
++      };
++
++      /* WSA8845, Right Tweeter */
++      right_tweeter: speaker@0,1 {
++              compatible = "sdw20217020400";
++              reg = <0 1>;
++              reset-gpios = <&lpass_tlmm 13 GPIO_ACTIVE_LOW>;
++              #sound-dai-cells = <0>;
++              sound-name-prefix = "TweeterRight";
++              vdd-1p8-supply = <&vreg_l15b_1p8>;
++              vdd-io-supply = <&vreg_l12b_1p2>;
++              qcom,port-mapping = <4 5 6 7 11 13>;
++      };
++};
++
++&tlmm {
++      gpio-reserved-ranges = <34 2>, /* Unused */
++                             <44 4>, /* SPI (TPM) */
++                             <238 1>; /* UFS Reset */
++
++      edp_reg_en: edp-reg-en-state {
++              pins = "gpio70";
++              function = "gpio";
++              drive-strength = <16>;
++              bias-disable;
++      };
++
++      hall_int_n_default: hall-int-n-state {
++              pins = "gpio92";
++              function = "gpio";
++              bias-disable;
++      };
++
++      kybd_default: kybd-default-state {
++              pins = "gpio67";
++              function = "gpio";
++              bias-disable;
++      };
++
++      nvme_reg_en: nvme-reg-en-state {
++              pins = "gpio18";
++              function = "gpio";
++              drive-strength = <2>;
++              bias-disable;
++      };
++
++      pcie4_default: pcie4-default-state {
++              clkreq-n-pins {
++                      pins = "gpio147";
++                      function = "pcie4_clk";
++                      drive-strength = <2>;
++                      bias-pull-up;
++              };
++
++              perst-n-pins {
++                      pins = "gpio146";
++                      function = "gpio";
++                      drive-strength = <2>;
++                      bias-disable;
++              };
++
++              wake-n-pins {
++                      pins = "gpio148";
++                      function = "gpio";
++                      drive-strength = <2>;
++                      bias-pull-up;
++              };
++      };
++
++      pcie5_default: pcie5-default-state {
++              clkreq-n-pins {
++                      pins = "gpio150";
++                      function = "pcie5_clk";
++                      drive-strength = <2>;
++                      bias-pull-up;
++              };
++
++              perst-n-pins {
++                      pins = "gpio149";
++                      function = "gpio";
++                      drive-strength = <2>;
++                      bias-disable;
++              };
++
++              wake-n-pins {
++                      pins = "gpio151";
++                      function = "gpio";
++                      drive-strength = <2>;
++                      bias-pull-up;
++              };
++      };
++
++      pcie6a_default: pcie6a-default-state {
++              clkreq-n-pins {
++                      pins = "gpio153";
++                      function = "pcie6a_clk";
++                      drive-strength = <2>;
++                      bias-pull-up;
++              };
++
++              perst-n-pins {
++                      pins = "gpio152";
++                      function = "gpio";
++                      drive-strength = <2>;
++                      bias-disable;
++              };
++
++              wake-n-pins {
++                      pins = "gpio154";
++                      function = "gpio";
++                      drive-strength = <2>;
++                      bias-pull-up;
++              };
++      };
++
++      tpad_default: tpad-default-state {
++              pins = "gpio3";
++              function = "gpio";
++              bias-disable;
++      };
++
++      ts0_default: ts0-default-state {
++              int-n-pins {
++                      pins = "gpio51";
++                      function = "gpio";
++                      bias-disable;
++              };
++
++              reset-n-pins {
++                      pins = "gpio48";
++                      function = "gpio";
++                      output-high;
++                      drive-strength = <16>;
++              };
++      };
++
++      wcd_default: wcd-reset-n-active-state {
++              pins = "gpio191";
++              function = "gpio";
++              drive-strength = <16>;
++              bias-disable;
++              output-low;
++      };
++
++      wwan_sw_en: wwan-sw-en-state {
++              pins = "gpio221";
++              function = "gpio";
++              drive-strength = <4>;
++              bias-disable;
++      };
++};
++
++&uart21 {
++      compatible = "qcom,geni-debug-uart";
++      status = "okay";
++};
++
++&usb_1_ss0_hsphy {
++      vdd-supply = <&vreg_l3j_0p8>;
++      vdda12-supply = <&vreg_l2j_1p2>;
++
++      phys = <&smb2360_0_eusb2_repeater>;
++
++      status = "okay";
++};
++
++&usb_1_ss0_qmpphy {
++      vdda-phy-supply = <&vreg_l2j_1p2>;
++      vdda-pll-supply = <&vreg_l1j_0p8>;
++
++      status = "okay";
++};
++
++&usb_1_ss0 {
++      status = "okay";
++};
++
++&usb_1_ss0_dwc3 {
++      dr_mode = "host";
++};
++
++&usb_1_ss0_dwc3_hs {
++      remote-endpoint = <&pmic_glink_ss0_hs_in>;
++};
++
++&usb_1_ss0_qmpphy_out {
++      remote-endpoint = <&pmic_glink_ss0_ss_in>;
++};
++
++&usb_1_ss1_hsphy {
++      vdd-supply = <&vreg_l3j_0p8>;
++      vdda12-supply = <&vreg_l2j_1p2>;
++
++      phys = <&smb2360_1_eusb2_repeater>;
++
++      status = "okay";
++};
++
++&usb_1_ss1_qmpphy {
++      vdda-phy-supply = <&vreg_l2j_1p2>;
++      vdda-pll-supply = <&vreg_l2d_0p9>;
++
++      status = "okay";
++};
++
++&usb_1_ss1 {
++      status = "okay";
++};
++
++&usb_1_ss1_dwc3 {
++      dr_mode = "host";
++};
++
++&usb_1_ss1_dwc3_hs {
++      remote-endpoint = <&pmic_glink_ss1_hs_in>;
++};
++
++&usb_1_ss1_qmpphy_out {
++      remote-endpoint = <&pmic_glink_ss1_ss_in>;
++};
++
++&usb_1_ss2_hsphy {
++      vdd-supply = <&vreg_l3j_0p8>;
++      vdda12-supply = <&vreg_l2j_1p2>;
++
++      phys = <&smb2360_2_eusb2_repeater>;
++
++      status = "okay";
++};
++
++&usb_1_ss2_qmpphy {
++      vdda-phy-supply = <&vreg_l2j_1p2>;
++      vdda-pll-supply = <&vreg_l2d_0p9>;
++
++      status = "okay";
++};
++
++&usb_1_ss2 {
++      status = "okay";
++};
++
++&usb_1_ss2_dwc3 {
++      dr_mode = "host";
++};
++
++&usb_1_ss2_dwc3_hs {
++      remote-endpoint = <&pmic_glink_ss2_hs_in>;
++};
++
++&usb_1_ss2_qmpphy_out {
++      remote-endpoint = <&pmic_glink_ss2_ss_in>;
++};
+diff --git a/arch/arm64/boot/dts/qcom/x1e80100-crd.dts b/arch/arm64/boot/dts/qcom/x1e80100-crd.dts
+index ff5b3472fafd3..976b8e44b5763 100644
+--- a/arch/arm64/boot/dts/qcom/x1e80100-crd.dts
++++ b/arch/arm64/boot/dts/qcom/x1e80100-crd.dts
+@@ -5,1278 +5,14 @@
+ /dts-v1/;
+-#include <dt-bindings/gpio/gpio.h>
+-#include <dt-bindings/input/gpio-keys.h>
+-#include <dt-bindings/input/input.h>
+-#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
+-#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+-
+ #include "x1e80100.dtsi"
+-#include "x1e80100-pmics.dtsi"
++#include "x1-crd.dtsi"
+ / {
+       model = "Qualcomm Technologies, Inc. X1E80100 CRD";
+       compatible = "qcom,x1e80100-crd", "qcom,x1e80100";
+-
+-      aliases {
+-              serial0 = &uart21;
+-      };
+-
+-      wcd938x: audio-codec {
+-              compatible = "qcom,wcd9385-codec";
+-
+-              pinctrl-names = "default";
+-              pinctrl-0 = <&wcd_default>;
+-
+-              qcom,micbias1-microvolt = <1800000>;
+-              qcom,micbias2-microvolt = <1800000>;
+-              qcom,micbias3-microvolt = <1800000>;
+-              qcom,micbias4-microvolt = <1800000>;
+-              qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>;
+-              qcom,mbhc-headset-vthreshold-microvolt = <1700000>;
+-              qcom,mbhc-headphone-vthreshold-microvolt = <50000>;
+-              qcom,rx-device = <&wcd_rx>;
+-              qcom,tx-device = <&wcd_tx>;
+-
+-              reset-gpios = <&tlmm 191 GPIO_ACTIVE_LOW>;
+-
+-              vdd-buck-supply = <&vreg_l15b_1p8>;
+-              vdd-rxtx-supply = <&vreg_l15b_1p8>;
+-              vdd-io-supply = <&vreg_l15b_1p8>;
+-              vdd-mic-bias-supply = <&vreg_bob1>;
+-
+-              #sound-dai-cells = <1>;
+-      };
+-
+-      chosen {
+-              stdout-path = "serial0:115200n8";
+-      };
+-
+-      gpio-keys {
+-              compatible = "gpio-keys";
+-
+-              pinctrl-0 = <&hall_int_n_default>;
+-              pinctrl-names = "default";
+-
+-              switch-lid {
+-                      gpios = <&tlmm 92 GPIO_ACTIVE_LOW>;
+-                      linux,input-type = <EV_SW>;
+-                      linux,code = <SW_LID>;
+-                      wakeup-source;
+-                      wakeup-event-action = <EV_ACT_DEASSERTED>;
+-              };
+-      };
+-
+-      pmic-glink {
+-              compatible = "qcom,x1e80100-pmic-glink",
+-                           "qcom,sm8550-pmic-glink",
+-                           "qcom,pmic-glink";
+-              #address-cells = <1>;
+-              #size-cells = <0>;
+-              orientation-gpios = <&tlmm 121 GPIO_ACTIVE_HIGH>,
+-                                  <&tlmm 123 GPIO_ACTIVE_HIGH>,
+-                                  <&tlmm 125 GPIO_ACTIVE_HIGH>;
+-
+-              /* Left-side rear port */
+-              connector@0 {
+-                      compatible = "usb-c-connector";
+-                      reg = <0>;
+-                      power-role = "dual";
+-                      data-role = "dual";
+-
+-                      ports {
+-                              #address-cells = <1>;
+-                              #size-cells = <0>;
+-
+-                              port@0 {
+-                                      reg = <0>;
+-
+-                                      pmic_glink_ss0_hs_in: endpoint {
+-                                              remote-endpoint = <&usb_1_ss0_dwc3_hs>;
+-                                      };
+-                              };
+-
+-                              port@1 {
+-                                      reg = <1>;
+-
+-                                      pmic_glink_ss0_ss_in: endpoint {
+-                                              remote-endpoint = <&usb_1_ss0_qmpphy_out>;
+-                                      };
+-                              };
+-                      };
+-              };
+-
+-              /* Left-side front port */
+-              connector@1 {
+-                      compatible = "usb-c-connector";
+-                      reg = <1>;
+-                      power-role = "dual";
+-                      data-role = "dual";
+-
+-                      ports {
+-                              #address-cells = <1>;
+-                              #size-cells = <0>;
+-
+-                              port@0 {
+-                                      reg = <0>;
+-
+-                                      pmic_glink_ss1_hs_in: endpoint {
+-                                              remote-endpoint = <&usb_1_ss1_dwc3_hs>;
+-                                      };
+-                              };
+-
+-                              port@1 {
+-                                      reg = <1>;
+-
+-                                      pmic_glink_ss1_ss_in: endpoint {
+-                                              remote-endpoint = <&usb_1_ss1_qmpphy_out>;
+-                                      };
+-                              };
+-                      };
+-              };
+-
+-              /* Right-side port */
+-              connector@2 {
+-                      compatible = "usb-c-connector";
+-                      reg = <2>;
+-                      power-role = "dual";
+-                      data-role = "dual";
+-
+-                      ports {
+-                              #address-cells = <1>;
+-                              #size-cells = <0>;
+-
+-                              port@0 {
+-                                      reg = <0>;
+-
+-                                      pmic_glink_ss2_hs_in: endpoint {
+-                                              remote-endpoint = <&usb_1_ss2_dwc3_hs>;
+-                                      };
+-                              };
+-
+-                              port@1 {
+-                                      reg = <1>;
+-
+-                                      pmic_glink_ss2_ss_in: endpoint {
+-                                              remote-endpoint = <&usb_1_ss2_qmpphy_out>;
+-                                      };
+-                              };
+-                      };
+-              };
+-      };
+-
+-      reserved-memory {
+-              linux,cma {
+-                      compatible = "shared-dma-pool";
+-                      size = <0x0 0x8000000>;
+-                      reusable;
+-                      linux,cma-default;
+-              };
+-      };
+-
+-      sound {
+-              compatible = "qcom,x1e80100-sndcard";
+-              model = "X1E80100-CRD";
+-              audio-routing = "WooferLeft IN", "WSA WSA_SPK1 OUT",
+-                              "TweeterLeft IN", "WSA WSA_SPK2 OUT",
+-                              "WooferRight IN", "WSA2 WSA_SPK2 OUT",
+-                              "TweeterRight IN", "WSA2 WSA_SPK2 OUT",
+-                              "IN1_HPHL", "HPHL_OUT",
+-                              "IN2_HPHR", "HPHR_OUT",
+-                              "AMIC2", "MIC BIAS2",
+-                              "VA DMIC0", "MIC BIAS3",
+-                              "VA DMIC1", "MIC BIAS3",
+-                              "VA DMIC2", "MIC BIAS1",
+-                              "VA DMIC3", "MIC BIAS1",
+-                              "VA DMIC0", "VA MIC BIAS3",
+-                              "VA DMIC1", "VA MIC BIAS3",
+-                              "VA DMIC2", "VA MIC BIAS1",
+-                              "VA DMIC3", "VA MIC BIAS1",
+-                              "TX SWR_INPUT1", "ADC2_OUTPUT";
+-
+-              wcd-playback-dai-link {
+-                      link-name = "WCD Playback";
+-
+-                      cpu {
+-                              sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>;
+-                      };
+-
+-                      codec {
+-                              sound-dai = <&wcd938x 0>, <&swr1 0>, <&lpass_rxmacro 0>;
+-                      };
+-
+-                      platform {
+-                              sound-dai = <&q6apm>;
+-                      };
+-              };
+-
+-              wcd-capture-dai-link {
+-                      link-name = "WCD Capture";
+-
+-                      cpu {
+-                              sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>;
+-                      };
+-
+-                      codec {
+-                              sound-dai = <&wcd938x 1>, <&swr2 1>, <&lpass_txmacro 0>;
+-                      };
+-
+-                      platform {
+-                              sound-dai = <&q6apm>;
+-                      };
+-              };
+-
+-              wsa-dai-link {
+-                      link-name = "WSA Playback";
+-
+-                      cpu {
+-                              sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>;
+-                      };
+-
+-                      codec {
+-                              sound-dai = <&left_woofer>, <&left_tweeter>,
+-                                          <&swr0 0>, <&lpass_wsamacro 0>,
+-                                          <&right_woofer>, <&right_tweeter>,
+-                                          <&swr3 0>, <&lpass_wsa2macro 0>;
+-                      };
+-
+-                      platform {
+-                              sound-dai = <&q6apm>;
+-                      };
+-              };
+-
+-              va-dai-link {
+-                      link-name = "VA Capture";
+-
+-                      cpu {
+-                              sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>;
+-                      };
+-
+-                      codec {
+-                              sound-dai = <&lpass_vamacro 0>;
+-                      };
+-
+-                      platform {
+-                              sound-dai = <&q6apm>;
+-                      };
+-              };
+-      };
+-
+-      vreg_edp_3p3: regulator-edp-3p3 {
+-              compatible = "regulator-fixed";
+-
+-              regulator-name = "VREG_EDP_3P3";
+-              regulator-min-microvolt = <3300000>;
+-              regulator-max-microvolt = <3300000>;
+-
+-              gpio = <&tlmm 70 GPIO_ACTIVE_HIGH>;
+-              enable-active-high;
+-
+-              pinctrl-0 = <&edp_reg_en>;
+-              pinctrl-names = "default";
+-
+-              regulator-boot-on;
+-      };
+-
+-      vreg_misc_3p3: regulator-misc-3p3 {
+-              compatible = "regulator-fixed";
+-
+-              regulator-name = "VREG_MISC_3P3";
+-              regulator-min-microvolt = <3300000>;
+-              regulator-max-microvolt = <3300000>;
+-
+-              gpio = <&pm8550ve_8_gpios 6 GPIO_ACTIVE_HIGH>;
+-              enable-active-high;
+-
+-              pinctrl-names = "default";
+-              pinctrl-0 = <&misc_3p3_reg_en>;
+-
+-              regulator-boot-on;
+-              regulator-always-on;
+-      };
+-
+-      vreg_nvme: regulator-nvme {
+-              compatible = "regulator-fixed";
+-
+-              regulator-name = "VREG_NVME_3P3";
+-              regulator-min-microvolt = <3300000>;
+-              regulator-max-microvolt = <3300000>;
+-
+-              gpio = <&tlmm 18 GPIO_ACTIVE_HIGH>;
+-              enable-active-high;
+-
+-              pinctrl-names = "default";
+-              pinctrl-0 = <&nvme_reg_en>;
+-
+-              regulator-boot-on;
+-      };
+-
+-      vph_pwr: regulator-vph-pwr {
+-              compatible = "regulator-fixed";
+-
+-              regulator-name = "vph_pwr";
+-              regulator-min-microvolt = <3700000>;
+-              regulator-max-microvolt = <3700000>;
+-
+-              regulator-always-on;
+-              regulator-boot-on;
+-      };
+-
+-      vreg_wwan: regulator-wwan {
+-              compatible = "regulator-fixed";
+-
+-              regulator-name = "SDX_VPH_PWR";
+-              regulator-min-microvolt = <3300000>;
+-              regulator-max-microvolt = <3300000>;
+-
+-              gpio = <&tlmm 221 GPIO_ACTIVE_HIGH>;
+-              enable-active-high;
+-
+-              pinctrl-0 = <&wwan_sw_en>;
+-              pinctrl-names = "default";
+-
+-              regulator-boot-on;
+-      };
+-};
+-
+-&apps_rsc {
+-      regulators-0 {
+-              compatible = "qcom,pm8550-rpmh-regulators";
+-              qcom,pmic-id = "b";
+-
+-              vdd-bob1-supply = <&vph_pwr>;
+-              vdd-bob2-supply = <&vph_pwr>;
+-              vdd-l1-l4-l10-supply = <&vreg_s4c_1p8>;
+-              vdd-l2-l13-l14-supply = <&vreg_bob1>;
+-              vdd-l5-l16-supply = <&vreg_bob1>;
+-              vdd-l6-l7-supply = <&vreg_bob2>;
+-              vdd-l8-l9-supply = <&vreg_bob1>;
+-              vdd-l12-supply = <&vreg_s5j_1p2>;
+-              vdd-l15-supply = <&vreg_s4c_1p8>;
+-              vdd-l17-supply = <&vreg_bob2>;
+-
+-              vreg_bob1: bob1 {
+-                      regulator-name = "vreg_bob1";
+-                      regulator-min-microvolt = <3008000>;
+-                      regulator-max-microvolt = <3960000>;
+-                      regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+-              };
+-
+-              vreg_bob2: bob2 {
+-                      regulator-name = "vreg_bob2";
+-                      regulator-min-microvolt = <2504000>;
+-                      regulator-max-microvolt = <3008000>;
+-                      regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+-              };
+-
+-              vreg_l1b_1p8: ldo1 {
+-                      regulator-name = "vreg_l1b_1p8";
+-                      regulator-min-microvolt = <1800000>;
+-                      regulator-max-microvolt = <1800000>;
+-                      regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+-              };
+-
+-              vreg_l2b_3p0: ldo2 {
+-                      regulator-name = "vreg_l2b_3p0";
+-                      regulator-min-microvolt = <3072000>;
+-                      regulator-max-microvolt = <3100000>;
+-                      regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+-              };
+-
+-              vreg_l4b_1p8: ldo4 {
+-                      regulator-name = "vreg_l4b_1p8";
+-                      regulator-min-microvolt = <1800000>;
+-                      regulator-max-microvolt = <1800000>;
+-                      regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+-              };
+-
+-              vreg_l5b_3p0: ldo5 {
+-                      regulator-name = "vreg_l5b_3p0";
+-                      regulator-min-microvolt = <3000000>;
+-                      regulator-max-microvolt = <3000000>;
+-                      regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+-              };
+-
+-              vreg_l6b_1p8: ldo6 {
+-                      regulator-name = "vreg_l6b_1p8";
+-                      regulator-min-microvolt = <1800000>;
+-                      regulator-max-microvolt = <2960000>;
+-                      regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+-              };
+-
+-              vreg_l7b_2p8: ldo7 {
+-                      regulator-name = "vreg_l7b_2p8";
+-                      regulator-min-microvolt = <2800000>;
+-                      regulator-max-microvolt = <2800000>;
+-                      regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+-              };
+-
+-              vreg_l8b_3p0: ldo8 {
+-                      regulator-name = "vreg_l8b_3p0";
+-                      regulator-min-microvolt = <3072000>;
+-                      regulator-max-microvolt = <3072000>;
+-                      regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+-              };
+-
+-              vreg_l9b_2p9: ldo9 {
+-                      regulator-name = "vreg_l9b_2p9";
+-                      regulator-min-microvolt = <2960000>;
+-                      regulator-max-microvolt = <2960000>;
+-                      regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+-              };
+-
+-              vreg_l10b_1p8: ldo10 {
+-                      regulator-name = "vreg_l10b_1p8";
+-                      regulator-min-microvolt = <1800000>;
+-                      regulator-max-microvolt = <1800000>;
+-                      regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+-              };
+-
+-              vreg_l12b_1p2: ldo12 {
+-                      regulator-name = "vreg_l12b_1p2";
+-                      regulator-min-microvolt = <1200000>;
+-                      regulator-max-microvolt = <1200000>;
+-                      regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+-              };
+-
+-              vreg_l13b_3p0: ldo13 {
+-                      regulator-name = "vreg_l13b_3p0";
+-                      regulator-min-microvolt = <3072000>;
+-                      regulator-max-microvolt = <3100000>;
+-                      regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+-              };
+-
+-              vreg_l14b_3p0: ldo14 {
+-                      regulator-name = "vreg_l14b_3p0";
+-                      regulator-min-microvolt = <3072000>;
+-                      regulator-max-microvolt = <3072000>;
+-                      regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+-              };
+-
+-              vreg_l15b_1p8: ldo15 {
+-                      regulator-name = "vreg_l15b_1p8";
+-                      regulator-min-microvolt = <1800000>;
+-                      regulator-max-microvolt = <1800000>;
+-                      regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+-              };
+-
+-              vreg_l16b_2p9: ldo16 {
+-                      regulator-name = "vreg_l16b_2p9";
+-                      regulator-min-microvolt = <2912000>;
+-                      regulator-max-microvolt = <2912000>;
+-                      regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+-              };
+-
+-              vreg_l17b_2p5: ldo17 {
+-                      regulator-name = "vreg_l17b_2p5";
+-                      regulator-min-microvolt = <2504000>;
+-                      regulator-max-microvolt = <2504000>;
+-                      regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+-              };
+-      };
+-
+-      regulators-1 {
+-              compatible = "qcom,pm8550ve-rpmh-regulators";
+-              qcom,pmic-id = "c";
+-
+-              vdd-l1-supply = <&vreg_s5j_1p2>;
+-              vdd-l2-supply = <&vreg_s1f_0p7>;
+-              vdd-l3-supply = <&vreg_s1f_0p7>;
+-              vdd-s4-supply = <&vph_pwr>;
+-
+-              vreg_s4c_1p8: smps4 {
+-                      regulator-name = "vreg_s4c_1p8";
+-                      regulator-min-microvolt = <1856000>;
+-                      regulator-max-microvolt = <2000000>;
+-                      regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+-              };
+-
+-              vreg_l1c_1p2: ldo1 {
+-                      regulator-name = "vreg_l1c_1p2";
+-                      regulator-min-microvolt = <1200000>;
+-                      regulator-max-microvolt = <1200000>;
+-                      regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+-              };
+-
+-              vreg_l2c_0p8: ldo2 {
+-                      regulator-name = "vreg_l2c_0p8";
+-                      regulator-min-microvolt = <880000>;
+-                      regulator-max-microvolt = <920000>;
+-                      regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+-              };
+-
+-              vreg_l3c_0p8: ldo3 {
+-                      regulator-name = "vreg_l3c_0p8";
+-                      regulator-min-microvolt = <880000>;
+-                      regulator-max-microvolt = <920000>;
+-                      regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+-              };
+-      };
+-
+-      regulators-2 {
+-              compatible = "qcom,pmc8380-rpmh-regulators";
+-              qcom,pmic-id = "d";
+-
+-              vdd-l1-supply = <&vreg_s1f_0p7>;
+-              vdd-l2-supply = <&vreg_s1f_0p7>;
+-              vdd-l3-supply = <&vreg_s4c_1p8>;
+-              vdd-s1-supply = <&vph_pwr>;
+-
+-              vreg_l1d_0p8: ldo1 {
+-                      regulator-name = "vreg_l1d_0p8";
+-                      regulator-min-microvolt = <880000>;
+-                      regulator-max-microvolt = <920000>;
+-                      regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+-              };
+-
+-              vreg_l2d_0p9: ldo2 {
+-                      regulator-name = "vreg_l2d_0p9";
+-                      regulator-min-microvolt = <912000>;
+-                      regulator-max-microvolt = <920000>;
+-                      regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+-              };
+-
+-              vreg_l3d_1p8: ldo3 {
+-                      regulator-name = "vreg_l3d_1p8";
+-                      regulator-min-microvolt = <1800000>;
+-                      regulator-max-microvolt = <1800000>;
+-                      regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+-              };
+-      };
+-
+-      regulators-3 {
+-              compatible = "qcom,pmc8380-rpmh-regulators";
+-              qcom,pmic-id = "e";
+-
+-              vdd-l2-supply = <&vreg_s1f_0p7>;
+-              vdd-l3-supply = <&vreg_s5j_1p2>;
+-
+-              vreg_l2e_0p8: ldo2 {
+-                      regulator-name = "vreg_l2e_0p8";
+-                      regulator-min-microvolt = <880000>;
+-                      regulator-max-microvolt = <920000>;
+-                      regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+-              };
+-
+-              vreg_l3e_1p2: ldo3 {
+-                      regulator-name = "vreg_l3e_1p2";
+-                      regulator-min-microvolt = <1200000>;
+-                      regulator-max-microvolt = <1200000>;
+-                      regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+-              };
+-      };
+-
+-      regulators-4 {
+-              compatible = "qcom,pmc8380-rpmh-regulators";
+-              qcom,pmic-id = "f";
+-
+-              vdd-l1-supply = <&vreg_s5j_1p2>;
+-              vdd-l2-supply = <&vreg_s5j_1p2>;
+-              vdd-l3-supply = <&vreg_s5j_1p2>;
+-              vdd-s1-supply = <&vph_pwr>;
+-
+-              vreg_s1f_0p7: smps1 {
+-                      regulator-name = "vreg_s1f_0p7";
+-                      regulator-min-microvolt = <700000>;
+-                      regulator-max-microvolt = <1100000>;
+-                      regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+-              };
+-
+-              vreg_l1f_1p0: ldo1 {
+-                      regulator-name = "vreg_l1f_1p0";
+-                      regulator-min-microvolt = <1024000>;
+-                      regulator-max-microvolt = <1024000>;
+-                      regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+-              };
+-
+-              vreg_l2f_1p0: ldo2 {
+-                      regulator-name = "vreg_l2f_1p0";
+-                      regulator-min-microvolt = <1024000>;
+-                      regulator-max-microvolt = <1024000>;
+-                      regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+-              };
+-
+-              vreg_l3f_1p0: ldo3 {
+-                      regulator-name = "vreg_l3f_1p0";
+-                      regulator-min-microvolt = <1024000>;
+-                      regulator-max-microvolt = <1024000>;
+-                      regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+-              };
+-      };
+-
+-      regulators-6 {
+-              compatible = "qcom,pm8550ve-rpmh-regulators";
+-              qcom,pmic-id = "i";
+-
+-              vdd-l1-supply = <&vreg_s4c_1p8>;
+-              vdd-l2-supply = <&vreg_s5j_1p2>;
+-              vdd-l3-supply = <&vreg_s1f_0p7>;
+-              vdd-s1-supply = <&vph_pwr>;
+-              vdd-s2-supply = <&vph_pwr>;
+-
+-              vreg_s1i_0p9: smps1 {
+-                      regulator-name = "vreg_s1i_0p9";
+-                      regulator-min-microvolt = <900000>;
+-                      regulator-max-microvolt = <920000>;
+-                      regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+-              };
+-
+-              vreg_s2i_1p0: smps2 {
+-                      regulator-name = "vreg_s2i_1p0";
+-                      regulator-min-microvolt = <1000000>;
+-                      regulator-max-microvolt = <1100000>;
+-                      regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+-              };
+-
+-              vreg_l1i_1p8: ldo1 {
+-                      regulator-name = "vreg_l1i_1p8";
+-                      regulator-min-microvolt = <1800000>;
+-                      regulator-max-microvolt = <1800000>;
+-                      regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+-              };
+-
+-              vreg_l2i_1p2: ldo2 {
+-                      regulator-name = "vreg_l2i_1p2";
+-                      regulator-min-microvolt = <1200000>;
+-                      regulator-max-microvolt = <1200000>;
+-                      regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+-              };
+-
+-              vreg_l3i_0p8: ldo3 {
+-                      regulator-name = "vreg_l3i_0p8";
+-                      regulator-min-microvolt = <880000>;
+-                      regulator-max-microvolt = <920000>;
+-                      regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+-              };
+-      };
+-
+-      regulators-7 {
+-              compatible = "qcom,pm8550ve-rpmh-regulators";
+-              qcom,pmic-id = "j";
+-
+-              vdd-l1-supply = <&vreg_s1f_0p7>;
+-              vdd-l2-supply = <&vreg_s5j_1p2>;
+-              vdd-l3-supply = <&vreg_s1f_0p7>;
+-              vdd-s5-supply = <&vph_pwr>;
+-
+-              vreg_s5j_1p2: smps5 {
+-                      regulator-name = "vreg_s5j_1p2";
+-                      regulator-min-microvolt = <1256000>;
+-                      regulator-max-microvolt = <1304000>;
+-                      regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+-              };
+-
+-              vreg_l1j_0p8: ldo1 {
+-                      regulator-name = "vreg_l1j_0p8";
+-                      regulator-min-microvolt = <880000>;
+-                      regulator-max-microvolt = <920000>;
+-                      regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+-              };
+-
+-              vreg_l2j_1p2: ldo2 {
+-                      regulator-name = "vreg_l2j_1p2";
+-                      regulator-min-microvolt = <1200000>;
+-                      regulator-max-microvolt = <1200000>;
+-                      regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+-              };
+-
+-              vreg_l3j_0p8: ldo3 {
+-                      regulator-name = "vreg_l3j_0p8";
+-                      regulator-min-microvolt = <880000>;
+-                      regulator-max-microvolt = <920000>;
+-                      regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+-              };
+-      };
+-};
+-
+-&gpu {
+-      status = "okay";
+-
+-      zap-shader {
+-              firmware-name = "qcom/x1e80100/gen70500_zap.mbn";
+-      };
+-};
+-
+-&i2c0 {
+-      clock-frequency = <400000>;
+-
+-      status = "okay";
+-
+-      touchpad@15 {
+-              compatible = "hid-over-i2c";
+-              reg = <0x15>;
+-
+-              hid-descr-addr = <0x1>;
+-              interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>;
+-
+-              vdd-supply = <&vreg_misc_3p3>;
+-              vddl-supply = <&vreg_l12b_1p2>;
+-
+-              pinctrl-0 = <&tpad_default>;
+-              pinctrl-names = "default";
+-
+-              wakeup-source;
+-      };
+-
+-      keyboard@3a {
+-              compatible = "hid-over-i2c";
+-              reg = <0x3a>;
+-
+-              hid-descr-addr = <0x1>;
+-              interrupts-extended = <&tlmm 67 IRQ_TYPE_LEVEL_LOW>;
+-
+-              vdd-supply = <&vreg_misc_3p3>;
+-              vddl-supply = <&vreg_l12b_1p2>;
+-
+-              pinctrl-0 = <&kybd_default>;
+-              pinctrl-names = "default";
+-
+-              wakeup-source;
+-      };
+-};
+-
+-&i2c8 {
+-      clock-frequency = <400000>;
+-
+-      status = "okay";
+-
+-      touchscreen@10 {
+-              compatible = "hid-over-i2c";
+-              reg = <0x10>;
+-
+-              hid-descr-addr = <0x1>;
+-              interrupts-extended = <&tlmm 51 IRQ_TYPE_LEVEL_LOW>;
+-
+-              vdd-supply = <&vreg_misc_3p3>;
+-              vddl-supply = <&vreg_l15b_1p8>;
+-
+-              pinctrl-0 = <&ts0_default>;
+-              pinctrl-names = "default";
+-      };
+-};
+-
+-&lpass_tlmm {
+-      spkr_01_sd_n_active: spkr-01-sd-n-active-state {
+-              pins = "gpio12";
+-              function = "gpio";
+-              drive-strength = <16>;
+-              bias-disable;
+-              output-low;
+-      };
+-
+-      spkr_23_sd_n_active: spkr-23-sd-n-active-state {
+-              pins = "gpio13";
+-              function = "gpio";
+-              drive-strength = <16>;
+-              bias-disable;
+-              output-low;
+-      };
+-};
+-
+-&lpass_vamacro {
+-      pinctrl-0 = <&dmic01_default>, <&dmic23_default>;
+-      pinctrl-names = "default";
+-
+-      vdd-micb-supply = <&vreg_l1b_1p8>;
+-      qcom,dmic-sample-rate = <4800000>;
+-};
+-
+-&mdss {
+-      status = "okay";
+-};
+-
+-&mdss_dp3 {
+-      compatible = "qcom,x1e80100-dp";
+-      /delete-property/ #sound-dai-cells;
+-
+-      status = "okay";
+-
+-      aux-bus {
+-              panel {
+-                      compatible = "samsung,atna45af01", "samsung,atna33xc20";
+-                      enable-gpios = <&pmc8380_3_gpios 4 GPIO_ACTIVE_HIGH>;
+-                      power-supply = <&vreg_edp_3p3>;
+-
+-                      pinctrl-0 = <&edp_bl_en>;
+-                      pinctrl-names = "default";
+-
+-                      port {
+-                              edp_panel_in: endpoint {
+-                                      remote-endpoint = <&mdss_dp3_out>;
+-                              };
+-                      };
+-              };
+-      };
+-
+-      ports {
+-              port@1 {
+-                      reg = <1>;
+-                      mdss_dp3_out: endpoint {
+-                              data-lanes = <0 1 2 3>;
+-                              link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
+-
+-                              remote-endpoint = <&edp_panel_in>;
+-                      };
+-              };
+-      };
+-};
+-
+-&mdss_dp3_phy {
+-      vdda-phy-supply = <&vreg_l3j_0p8>;
+-      vdda-pll-supply = <&vreg_l2j_1p2>;
+-
+-      status = "okay";
+-};
+-
+-&pcie4 {
+-      perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
+-      wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
+-
+-      pinctrl-0 = <&pcie4_default>;
+-      pinctrl-names = "default";
+-
+-      status = "okay";
+-};
+-
+-&pcie4_phy {
+-      vdda-phy-supply = <&vreg_l3i_0p8>;
+-      vdda-pll-supply = <&vreg_l3e_1p2>;
+-
+-      status = "okay";
+-};
+-
+-&pcie5 {
+-      perst-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>;
+-      wake-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;
+-
+-      vddpe-3v3-supply = <&vreg_wwan>;
+-
+-      pinctrl-0 = <&pcie5_default>;
+-      pinctrl-names = "default";
+-
+-      status = "okay";
+-};
+-
+-&pcie5_phy {
+-      vdda-phy-supply = <&vreg_l3i_0p8>;
+-      vdda-pll-supply = <&vreg_l3e_1p2>;
+-
+-      status = "okay";
+-};
+-
+-&pcie6a {
+-      perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
+-      wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
+-
+-      vddpe-3v3-supply = <&vreg_nvme>;
+-
+-      pinctrl-names = "default";
+-      pinctrl-0 = <&pcie6a_default>;
+-
+-      status = "okay";
+-};
+-
+-&pcie6a_phy {
+-      vdda-phy-supply = <&vreg_l1d_0p8>;
+-      vdda-pll-supply = <&vreg_l2j_1p2>;
+-
+-      status = "okay";
+-};
+-
+-&pm8550ve_8_gpios {
+-      misc_3p3_reg_en: misc-3p3-reg-en-state {
+-              pins = "gpio6";
+-              function = "normal";
+-              bias-disable;
+-              input-disable;
+-              output-enable;
+-              drive-push-pull;
+-              power-source = <1>; /* 1.8 V */
+-              qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>;
+-      };
+-};
+-
+-&pmc8380_3_gpios {
+-      edp_bl_en: edp-bl-en-state {
+-              pins = "gpio4";
+-              function = "normal";
+-              power-source = <1>; /* 1.8V */
+-              input-disable;
+-              output-enable;
+-      };
+-};
+-
+-&qupv3_0 {
+-      status = "okay";
+-};
+-
+-&qupv3_1 {
+-      status = "okay";
+-};
+-
+-&qupv3_2 {
+-      status = "okay";
+-};
+-
+-&remoteproc_adsp {
+-      firmware-name = "qcom/x1e80100/adsp.mbn",
+-                      "qcom/x1e80100/adsp_dtb.mbn";
+-
+-      status = "okay";
+-};
+-
+-&remoteproc_cdsp {
+-      firmware-name = "qcom/x1e80100/cdsp.mbn",
+-                      "qcom/x1e80100/cdsp_dtb.mbn";
+-
+-      status = "okay";
+-};
+-
+-&smb2360_0 {
+-      status = "okay";
+-};
+-
+-&smb2360_0_eusb2_repeater {
+-      vdd18-supply = <&vreg_l3d_1p8>;
+-      vdd3-supply = <&vreg_l2b_3p0>;
+-};
+-
+-&smb2360_1 {
+-      status = "okay";
+-};
+-
+-&smb2360_1_eusb2_repeater {
+-      vdd18-supply = <&vreg_l3d_1p8>;
+-      vdd3-supply = <&vreg_l14b_3p0>;
+-};
+-
+-&smb2360_2 {
+-      status = "okay";
+-};
+-
+-&smb2360_2_eusb2_repeater {
+-      vdd18-supply = <&vreg_l3d_1p8>;
+-      vdd3-supply = <&vreg_l8b_3p0>;
+-};
+-
+-&swr0 {
+-      status = "okay";
+-
+-      pinctrl-0 = <&wsa_swr_active>, <&spkr_01_sd_n_active>;
+-      pinctrl-names = "default";
+-
+-      /* WSA8845, Left Woofer */
+-      left_woofer: speaker@0,0 {
+-              compatible = "sdw20217020400";
+-              reg = <0 0>;
+-              reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>;
+-              #sound-dai-cells = <0>;
+-              sound-name-prefix = "WooferLeft";
+-              vdd-1p8-supply = <&vreg_l15b_1p8>;
+-              vdd-io-supply = <&vreg_l12b_1p2>;
+-              qcom,port-mapping = <1 2 3 7 10 13>;
+-      };
+-
+-      /* WSA8845, Left Tweeter */
+-      left_tweeter: speaker@0,1 {
+-              compatible = "sdw20217020400";
+-              reg = <0 1>;
+-              reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>;
+-              #sound-dai-cells = <0>;
+-              sound-name-prefix = "TweeterLeft";
+-              vdd-1p8-supply = <&vreg_l15b_1p8>;
+-              vdd-io-supply = <&vreg_l12b_1p2>;
+-              qcom,port-mapping = <4 5 6 7 11 13>;
+-      };
+-};
+-
+-&swr1 {
+-      status = "okay";
+-
+-      /* WCD9385 RX */
+-      wcd_rx: codec@0,4 {
+-              compatible = "sdw20217010d00";
+-              reg = <0 4>;
+-              qcom,rx-port-mapping = <1 2 3 4 5>;
+-      };
+-};
+-
+-&swr2 {
+-      status = "okay";
+-
+-      /* WCD9385 TX */
+-      wcd_tx: codec@0,3 {
+-              compatible = "sdw20217010d00";
+-              reg = <0 3>;
+-              qcom,tx-port-mapping = <2 2 3 4>;
+-      };
+-};
+-
+-&swr3 {
+-      status = "okay";
+-
+-      pinctrl-0 = <&wsa2_swr_active>, <&spkr_23_sd_n_active>;
+-      pinctrl-names = "default";
+-
+-      /* WSA8845, Right Woofer */
+-      right_woofer: speaker@0,0 {
+-              compatible = "sdw20217020400";
+-              reg = <0 0>;
+-              reset-gpios = <&lpass_tlmm 13 GPIO_ACTIVE_LOW>;
+-              #sound-dai-cells = <0>;
+-              sound-name-prefix = "WooferRight";
+-              vdd-1p8-supply = <&vreg_l15b_1p8>;
+-              vdd-io-supply = <&vreg_l12b_1p2>;
+-              qcom,port-mapping = <1 2 3 7 10 13>;
+-      };
+-
+-      /* WSA8845, Right Tweeter */
+-      right_tweeter: speaker@0,1 {
+-              compatible = "sdw20217020400";
+-              reg = <0 1>;
+-              reset-gpios = <&lpass_tlmm 13 GPIO_ACTIVE_LOW>;
+-              #sound-dai-cells = <0>;
+-              sound-name-prefix = "TweeterRight";
+-              vdd-1p8-supply = <&vreg_l15b_1p8>;
+-              vdd-io-supply = <&vreg_l12b_1p2>;
+-              qcom,port-mapping = <4 5 6 7 11 13>;
+-      };
+-};
+-
+-&tlmm {
+-      gpio-reserved-ranges = <34 2>, /* Unused */
+-                             <44 4>, /* SPI (TPM) */
+-                             <238 1>; /* UFS Reset */
+-
+-      edp_reg_en: edp-reg-en-state {
+-              pins = "gpio70";
+-              function = "gpio";
+-              drive-strength = <16>;
+-              bias-disable;
+-      };
+-
+-      hall_int_n_default: hall-int-n-state {
+-              pins = "gpio92";
+-              function = "gpio";
+-              bias-disable;
+-      };
+-
+-      kybd_default: kybd-default-state {
+-              pins = "gpio67";
+-              function = "gpio";
+-              bias-disable;
+-      };
+-
+-      nvme_reg_en: nvme-reg-en-state {
+-              pins = "gpio18";
+-              function = "gpio";
+-              drive-strength = <2>;
+-              bias-disable;
+-      };
+-
+-      pcie4_default: pcie4-default-state {
+-              clkreq-n-pins {
+-                      pins = "gpio147";
+-                      function = "pcie4_clk";
+-                      drive-strength = <2>;
+-                      bias-pull-up;
+-              };
+-
+-              perst-n-pins {
+-                      pins = "gpio146";
+-                      function = "gpio";
+-                      drive-strength = <2>;
+-                      bias-disable;
+-              };
+-
+-              wake-n-pins {
+-                      pins = "gpio148";
+-                      function = "gpio";
+-                      drive-strength = <2>;
+-                      bias-pull-up;
+-              };
+-      };
+-
+-      pcie5_default: pcie5-default-state {
+-              clkreq-n-pins {
+-                      pins = "gpio150";
+-                      function = "pcie5_clk";
+-                      drive-strength = <2>;
+-                      bias-pull-up;
+-              };
+-
+-              perst-n-pins {
+-                      pins = "gpio149";
+-                      function = "gpio";
+-                      drive-strength = <2>;
+-                      bias-disable;
+-              };
+-
+-              wake-n-pins {
+-                      pins = "gpio151";
+-                      function = "gpio";
+-                      drive-strength = <2>;
+-                      bias-pull-up;
+-              };
+-      };
+-
+-      pcie6a_default: pcie6a-default-state {
+-              clkreq-n-pins {
+-                      pins = "gpio153";
+-                      function = "pcie6a_clk";
+-                      drive-strength = <2>;
+-                      bias-pull-up;
+-              };
+-
+-              perst-n-pins {
+-                      pins = "gpio152";
+-                      function = "gpio";
+-                      drive-strength = <2>;
+-                      bias-disable;
+-              };
+-
+-              wake-n-pins {
+-                      pins = "gpio154";
+-                      function = "gpio";
+-                      drive-strength = <2>;
+-                      bias-pull-up;
+-              };
+-      };
+-
+-      tpad_default: tpad-default-state {
+-              pins = "gpio3";
+-              function = "gpio";
+-              bias-disable;
+-      };
+-
+-      ts0_default: ts0-default-state {
+-              int-n-pins {
+-                      pins = "gpio51";
+-                      function = "gpio";
+-                      bias-disable;
+-              };
+-
+-              reset-n-pins {
+-                      pins = "gpio48";
+-                      function = "gpio";
+-                      output-high;
+-                      drive-strength = <16>;
+-              };
+-      };
+-
+-      wcd_default: wcd-reset-n-active-state {
+-              pins = "gpio191";
+-              function = "gpio";
+-              drive-strength = <16>;
+-              bias-disable;
+-              output-low;
+-      };
+-
+-      wwan_sw_en: wwan-sw-en-state {
+-              pins = "gpio221";
+-              function = "gpio";
+-              drive-strength = <4>;
+-              bias-disable;
+-      };
+-};
+-
+-&uart21 {
+-      compatible = "qcom,geni-debug-uart";
+-      status = "okay";
+-};
+-
+-&usb_1_ss0_hsphy {
+-      vdd-supply = <&vreg_l3j_0p8>;
+-      vdda12-supply = <&vreg_l2j_1p2>;
+-
+-      phys = <&smb2360_0_eusb2_repeater>;
+-
+-      status = "okay";
+-};
+-
+-&usb_1_ss0_qmpphy {
+-      vdda-phy-supply = <&vreg_l2j_1p2>;
+-      vdda-pll-supply = <&vreg_l1j_0p8>;
+-
+-      status = "okay";
+-};
+-
+-&usb_1_ss0 {
+-      status = "okay";
+-};
+-
+-&usb_1_ss0_dwc3 {
+-      dr_mode = "host";
+-};
+-
+-&usb_1_ss0_dwc3_hs {
+-      remote-endpoint = <&pmic_glink_ss0_hs_in>;
+-};
+-
+-&usb_1_ss0_qmpphy_out {
+-      remote-endpoint = <&pmic_glink_ss0_ss_in>;
+-};
+-
+-&usb_1_ss1_hsphy {
+-      vdd-supply = <&vreg_l3j_0p8>;
+-      vdda12-supply = <&vreg_l2j_1p2>;
+-
+-      phys = <&smb2360_1_eusb2_repeater>;
+-
+-      status = "okay";
+-};
+-
+-&usb_1_ss1_qmpphy {
+-      vdda-phy-supply = <&vreg_l2j_1p2>;
+-      vdda-pll-supply = <&vreg_l2d_0p9>;
+-
+-      status = "okay";
+-};
+-
+-&usb_1_ss1 {
+-      status = "okay";
+-};
+-
+-&usb_1_ss1_dwc3 {
+-      dr_mode = "host";
+-};
+-
+-&usb_1_ss1_dwc3_hs {
+-      remote-endpoint = <&pmic_glink_ss1_hs_in>;
+-};
+-
+-&usb_1_ss1_qmpphy_out {
+-      remote-endpoint = <&pmic_glink_ss1_ss_in>;
+-};
+-
+-&usb_1_ss2_hsphy {
+-      vdd-supply = <&vreg_l3j_0p8>;
+-      vdda12-supply = <&vreg_l2j_1p2>;
+-
+-      phys = <&smb2360_2_eusb2_repeater>;
+-
+-      status = "okay";
+-};
+-
+-&usb_1_ss2_qmpphy {
+-      vdda-phy-supply = <&vreg_l2j_1p2>;
+-      vdda-pll-supply = <&vreg_l2d_0p9>;
+-
+-      status = "okay";
+-};
+-
+-&usb_1_ss2 {
+-      status = "okay";
+-};
+-
+-&usb_1_ss2_dwc3 {
+-      dr_mode = "host";
+-};
+-
+-&usb_1_ss2_dwc3_hs {
+-      remote-endpoint = <&pmic_glink_ss2_hs_in>;
+ };
+-&usb_1_ss2_qmpphy_out {
+-      remote-endpoint = <&pmic_glink_ss2_ss_in>;
++&gpu_zap_shader {
++      firmware-name = "qcom/x1e80100/gen70500_zap.mbn";
+ };
+diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
+index 607d32f68c340..a25783c85e163 100644
+--- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
++++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
+@@ -3748,7 +3748,7 @@ gpu: gpu@3d00000 {
+                       status = "disabled";
+-                      zap-shader {
++                      gpu_zap_shader: zap-shader {
+                               memory-region = <&gpu_microcode_mem>;
+                       };
+-- 
+2.39.5
+
diff --git a/queue-6.15/arm64-dts-qcom-x1-crd-fix-vreg_l2j_1p2-voltage.patch b/queue-6.15/arm64-dts-qcom-x1-crd-fix-vreg_l2j_1p2-voltage.patch
new file mode 100644 (file)
index 0000000..04ab507
--- /dev/null
@@ -0,0 +1,44 @@
+From d0c2ffeab1fa3bbf3bfe2aa9ceefc21104d0237f Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 23 Apr 2025 09:30:07 +0200
+Subject: arm64: dts: qcom: x1-crd: Fix vreg_l2j_1p2 voltage
+
+From: Stephan Gerhold <stephan.gerhold@linaro.org>
+
+[ Upstream commit 5ce920e6a8db40e4b094c0d863cbd19fdcfbbb7a ]
+
+In the ACPI DSDT table, PPP_RESOURCE_ID_LDO2_J is configured with 1256000
+uV instead of the 1200000 uV we have currently in the device tree. Use the
+same for consistency and correctness.
+
+Cc: stable@vger.kernel.org
+Fixes: bd50b1f5b6f3 ("arm64: dts: qcom: x1e80100: Add Compute Reference Device")
+Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org>
+Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
+Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
+Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
+Link: https://lore.kernel.org/r/20250423-x1e-vreg-l2j-voltage-v1-1-24b6a2043025@linaro.org
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/arm64/boot/dts/qcom/x1-crd.dtsi | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/qcom/x1-crd.dtsi b/arch/arm64/boot/dts/qcom/x1-crd.dtsi
+index 780852fb87360..60f0b32baded3 100644
+--- a/arch/arm64/boot/dts/qcom/x1-crd.dtsi
++++ b/arch/arm64/boot/dts/qcom/x1-crd.dtsi
+@@ -674,8 +674,8 @@ vreg_l1j_0p8: ldo1 {
+               vreg_l2j_1p2: ldo2 {
+                       regulator-name = "vreg_l2j_1p2";
+-                      regulator-min-microvolt = <1200000>;
+-                      regulator-max-microvolt = <1200000>;
++                      regulator-min-microvolt = <1256000>;
++                      regulator-max-microvolt = <1256000>;
+                       regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+               };
+-- 
+2.39.5
+
diff --git a/queue-6.15/arm64-dts-qcom-x1e78100-t14s-fix-missing-hid-supplie.patch b/queue-6.15/arm64-dts-qcom-x1e78100-t14s-fix-missing-hid-supplie.patch
new file mode 100644 (file)
index 0000000..1b232ab
--- /dev/null
@@ -0,0 +1,134 @@
+From 2d3a663dd90ebab673ee10ebf3161e5af90523c4 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 1 Jul 2025 21:58:48 -0400
+Subject: arm64: dts: qcom: x1e78100-t14s: fix missing HID supplies
+
+[ Upstream commit 55e52d055393f11ba0193975d3db87af36f4b273 ]
+
+Add the missing HID supplies to avoid relying on other consumers to keep
+them on.
+
+This also avoids the following warnings on boot:
+
+       i2c_hid_of 0-0010: supply vdd not found, using dummy regulator
+       i2c_hid_of 0-0010: supply vddl not found, using dummy regulator
+       i2c_hid_of 1-0015: supply vdd not found, using dummy regulator
+       i2c_hid_of 1-002c: supply vdd not found, using dummy regulator
+       i2c_hid_of 1-0015: supply vddl not found, using dummy regulator
+       i2c_hid_of 1-002c: supply vddl not found, using dummy regulator
+       i2c_hid_of 1-003a: supply vdd not found, using dummy regulator
+       i2c_hid_of 1-003a: supply vddl not found, using dummy regulator
+
+Note that VCC3B is also used for things like the modem which are not yet
+described so mark the regulator as always-on for now.
+
+Fixes: 7d1cbe2f4985 ("arm64: dts: qcom: Add X1E78100 ThinkPad T14s Gen 6")
+Cc: stable@vger.kernel.org     # 6.12
+Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
+Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
+Link: https://lore.kernel.org/r/20250314145440.11371-9-johan+linaro@kernel.org
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ .../qcom/x1e78100-lenovo-thinkpad-t14s.dts    | 43 +++++++++++++++++++
+ 1 file changed, 43 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dts b/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dts
+index 7f756ce48d2f6..999d966b44869 100644
+--- a/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dts
++++ b/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dts
+@@ -9,6 +9,7 @@
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/input/gpio-keys.h>
+ #include <dt-bindings/input/input.h>
++#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
+ #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+ #include "x1e80100.dtsi"
+@@ -153,6 +154,23 @@ vreg_edp_3p3: regulator-edp-3p3 {
+               regulator-boot-on;
+       };
++      vreg_misc_3p3: regulator-misc-3p3 {
++              compatible = "regulator-fixed";
++
++              regulator-name = "VCC3B";
++              regulator-min-microvolt = <3300000>;
++              regulator-max-microvolt = <3300000>;
++
++              gpio = <&pm8550ve_8_gpios 6 GPIO_ACTIVE_HIGH>;
++              enable-active-high;
++
++              pinctrl-0 = <&misc_3p3_reg_en>;
++              pinctrl-names = "default";
++
++              regulator-boot-on;
++              regulator-always-on;
++      };
++
+       vreg_nvme: regulator-nvme {
+               compatible = "regulator-fixed";
+@@ -580,6 +598,9 @@ touchpad@15 {
+               hid-descr-addr = <0x1>;
+               interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>;
++              vdd-supply = <&vreg_misc_3p3>;
++              vddl-supply = <&vreg_l12b_1p2>;
++
+               wakeup-source;
+       };
+@@ -591,6 +612,9 @@ touchpad@2c {
+               hid-descr-addr = <0x20>;
+               interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>;
++              vdd-supply = <&vreg_misc_3p3>;
++              vddl-supply = <&vreg_l12b_1p2>;
++
+               wakeup-source;
+       };
+@@ -602,6 +626,9 @@ keyboard@3a {
+               hid-descr-addr = <0x1>;
+               interrupts-extended = <&tlmm 67 IRQ_TYPE_LEVEL_LOW>;
++              vdd-supply = <&vreg_misc_3p3>;
++              vddl-supply = <&vreg_l15b_1p8>;
++
+               pinctrl-0 = <&kybd_default>;
+               pinctrl-names = "default";
+@@ -670,6 +697,9 @@ touchscreen@10 {
+               hid-descr-addr = <0x1>;
+               interrupts-extended = <&tlmm 51 IRQ_TYPE_LEVEL_LOW>;
++              vdd-supply = <&vreg_misc_3p3>;
++              vddl-supply = <&vreg_l15b_1p8>;
++
+               pinctrl-0 = <&ts0_default>;
+               pinctrl-names = "default";
+       };
+@@ -789,6 +819,19 @@ edp_bl_en: edp-bl-en-state {
+       };
+ };
++&pm8550ve_8_gpios {
++      misc_3p3_reg_en: misc-3p3-reg-en-state {
++              pins = "gpio6";
++              function = "normal";
++              bias-disable;
++              drive-push-pull;
++              input-disable;
++              output-enable;
++              power-source = <1>; /* 1.8 V */
++              qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>;
++      };
++};
++
+ &qupv3_0 {
+       status = "okay";
+ };
+-- 
+2.39.5
+
diff --git a/queue-6.15/arm64-dts-qcom-x1e78100-t14s-mark-l12b-and-l15b-alwa.patch b/queue-6.15/arm64-dts-qcom-x1e78100-t14s-mark-l12b-and-l15b-alwa.patch
new file mode 100644 (file)
index 0000000..b36e7c8
--- /dev/null
@@ -0,0 +1,47 @@
+From 39068a3dab2cde051c2f19a4b45bb4068ba7b538 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 1 Jul 2025 21:17:43 -0400
+Subject: arm64: dts: qcom: x1e78100-t14s: mark l12b and l15b always-on
+
+[ Upstream commit 673fa129e558c5f1196adb27d97ac90ddfe4f19c ]
+
+The l12b and l15b supplies are used by components that are not (fully)
+described (and some never will be) and must never be disabled.
+
+Mark the regulators as always-on to prevent them from being disabled,
+for example, when consumers probe defer or suspend.
+
+Fixes: 7d1cbe2f4985 ("arm64: dts: qcom: Add X1E78100 ThinkPad T14s Gen 6")
+Cc: stable@vger.kernel.org     # 6.12
+Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
+Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
+Link: https://lore.kernel.org/r/20250314145440.11371-3-johan+linaro@kernel.org
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dts | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dts b/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dts
+index b2c2347f54fa6..7f756ce48d2f6 100644
+--- a/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dts
++++ b/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dts
+@@ -344,6 +344,7 @@ vreg_l12b_1p2: ldo12 {
+                       regulator-min-microvolt = <1200000>;
+                       regulator-max-microvolt = <1200000>;
+                       regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
++                      regulator-always-on;
+               };
+               vreg_l13b_3p0: ldo13 {
+@@ -365,6 +366,7 @@ vreg_l15b_1p8: ldo15 {
+                       regulator-min-microvolt = <1800000>;
+                       regulator-max-microvolt = <1800000>;
+                       regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
++                      regulator-always-on;
+               };
+               vreg_l17b_2p5: ldo17 {
+-- 
+2.39.5
+
diff --git a/queue-6.15/arm64-dts-qcom-x1e80100-crd-mark-l12b-and-l15b-alway.patch b/queue-6.15/arm64-dts-qcom-x1e80100-crd-mark-l12b-and-l15b-alway.patch
new file mode 100644 (file)
index 0000000..b16f509
--- /dev/null
@@ -0,0 +1,52 @@
+From 8a26d7679769ea2ffb27b033755a8076fa723a55 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 14 Mar 2025 15:54:33 +0100
+Subject: arm64: dts: qcom: x1e80100-crd: mark l12b and l15b always-on
+
+From: Johan Hovold <johan+linaro@kernel.org>
+
+[ Upstream commit abf89bc4bb09c16a53d693b09ea85225cf57ff39 ]
+
+The l12b and l15b supplies are used by components that are not (fully)
+described (and some never will be) and must never be disabled.
+
+Mark the regulators as always-on to prevent them from being disabled,
+for example, when consumers probe defer or suspend.
+
+Fixes: bd50b1f5b6f3 ("arm64: dts: qcom: x1e80100: Add Compute Reference Device")
+Cc: stable@vger.kernel.org     # 6.8
+Cc: Abel Vesa <abel.vesa@linaro.org>
+Cc: Rajendra Nayak <quic_rjendra@quicinc.com>
+Cc: Sibi Sankar <quic_sibis@quicinc.com>
+Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
+Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
+Link: https://lore.kernel.org/r/20250314145440.11371-2-johan+linaro@kernel.org
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/arm64/boot/dts/qcom/x1-crd.dtsi | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/qcom/x1-crd.dtsi b/arch/arm64/boot/dts/qcom/x1-crd.dtsi
+index 296b41409ad17..780852fb87360 100644
+--- a/arch/arm64/boot/dts/qcom/x1-crd.dtsi
++++ b/arch/arm64/boot/dts/qcom/x1-crd.dtsi
+@@ -434,6 +434,7 @@ vreg_l12b_1p2: ldo12 {
+                       regulator-min-microvolt = <1200000>;
+                       regulator-max-microvolt = <1200000>;
+                       regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
++                      regulator-always-on;
+               };
+               vreg_l13b_3p0: ldo13 {
+@@ -455,6 +456,7 @@ vreg_l15b_1p8: ldo15 {
+                       regulator-min-microvolt = <1800000>;
+                       regulator-max-microvolt = <1800000>;
+                       regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
++                      regulator-always-on;
+               };
+               vreg_l16b_2p9: ldo16 {
+-- 
+2.39.5
+
diff --git a/queue-6.15/crypto-powerpc-poly1305-add-depends-on-broken-for-no.patch b/queue-6.15/crypto-powerpc-poly1305-add-depends-on-broken-for-no.patch
new file mode 100644 (file)
index 0000000..63685da
--- /dev/null
@@ -0,0 +1,38 @@
+From b8f35b28ac3bcdaf3a578151df91d831a7a1f6ce Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 20 May 2025 10:39:29 +0800
+Subject: crypto: powerpc/poly1305 - add depends on BROKEN for now
+
+From: Eric Biggers <ebiggers@google.com>
+
+[ Upstream commit bc8169003b41e89fe7052e408cf9fdbecb4017fe ]
+
+As discussed in the thread containing
+https://lore.kernel.org/linux-crypto/20250510053308.GB505731@sol/, the
+Power10-optimized Poly1305 code is currently not safe to call in softirq
+context.  Disable it for now.  It can be re-enabled once it is fixed.
+
+Fixes: ba8f8624fde2 ("crypto: poly1305-p10 - Glue code for optmized Poly1305 implementation for ppc64le")
+Cc: stable@vger.kernel.org
+Signed-off-by: Eric Biggers <ebiggers@google.com>
+Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/powerpc/crypto/Kconfig | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/powerpc/crypto/Kconfig b/arch/powerpc/crypto/Kconfig
+index 370db8192ce62..7b785c8664f5d 100644
+--- a/arch/powerpc/crypto/Kconfig
++++ b/arch/powerpc/crypto/Kconfig
+@@ -110,6 +110,7 @@ config CRYPTO_CHACHA20_P10
+ config CRYPTO_POLY1305_P10
+       tristate "Hash functions: Poly1305 (P10 or later)"
+       depends on PPC64 && CPU_LITTLE_ENDIAN && VSX
++      depends on BROKEN # Needs to be fixed to work in softirq context
+       select CRYPTO_HASH
+       select CRYPTO_LIB_POLY1305_GENERIC
+       help
+-- 
+2.39.5
+
diff --git a/queue-6.15/drm-amd-display-add-early-8b-10b-channel-equalizatio.patch b/queue-6.15/drm-amd-display-add-early-8b-10b-channel-equalizatio.patch
new file mode 100644 (file)
index 0000000..5912d2a
--- /dev/null
@@ -0,0 +1,187 @@
+From eaae566ecd7ebfb4e2d25344bc3bbdc2027b79d1 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 4 Dec 2023 16:30:39 +0800
+Subject: drm/amd/display: Add early 8b/10b channel equalization test pattern
+ sequence
+
+From: Michael Strauss <michael.strauss@amd.com>
+
+[ Upstream commit 8989cb919b27cd0d2aadb7f1d144cedbb12e6fca ]
+
+[WHY]
+Early EQ pattern sequence is required for some LTTPR + old dongle
+combinations.
+
+[HOW]
+If DP_EARLY_8B10B_TPS2 chip cap is set, this new sequence programs phy
+to output TPS2 before initiating link training and writes TPS1 to
+LTTPR training pattern register as instructed by vendor.
+
+Add function to get embedded LTTPR target address offset.
+
+Reviewed-by: Wenjing Liu <wenjing.liu@amd.com>
+Signed-off-by: Michael Strauss <michael.strauss@amd.com>
+Signed-off-by: TungYu Lu <tungyu.lu@amd.com>
+Signed-off-by: Ray Wu <ray.wu@amd.com>
+Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ .../dc/link/protocols/link_dp_capability.c    |  8 +++
+ .../dc/link/protocols/link_dp_capability.h    |  3 ++
+ .../dc/link/protocols/link_dp_training.c      |  1 -
+ .../link/protocols/link_dp_training_8b_10b.c  | 52 +++++++++++++++++--
+ .../amd/display/include/link_service_types.h  |  2 +
+ 5 files changed, 62 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
+index 21ee0d96c9d48..9d49e77a24a1f 100644
+--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
++++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
+@@ -158,6 +158,14 @@ uint8_t dp_parse_lttpr_repeater_count(uint8_t lttpr_repeater_count)
+       return 0; // invalid value
+ }
++uint32_t dp_get_closest_lttpr_offset(uint8_t lttpr_count)
++{
++      /* Calculate offset for LTTPR closest to DPTX which is highest in the chain
++       * Offset is 0 for single LTTPR cases as base LTTPR DPCD addresses target LTTPR 1
++       */
++      return DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE * (lttpr_count - 1);
++}
++
+ uint32_t link_bw_kbps_from_raw_frl_link_rate_data(uint8_t bw)
+ {
+       switch (bw) {
+diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.h b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.h
+index 0ce0af3ddbebe..940b147cc5d42 100644
+--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.h
++++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.h
+@@ -48,6 +48,9 @@ enum dc_status dp_retrieve_lttpr_cap(struct dc_link *link);
+ /* Convert PHY repeater count read from DPCD uint8_t. */
+ uint8_t dp_parse_lttpr_repeater_count(uint8_t lttpr_repeater_count);
++/* Calculate embedded LTTPR address offset for vendor-specific behaviour */
++uint32_t dp_get_closest_lttpr_offset(uint8_t lttpr_count);
++
+ bool dp_is_sink_present(struct dc_link *link);
+ bool dp_is_lttpr_present(struct dc_link *link);
+diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c
+index ef358afdfb65b..2dc1a660e5045 100644
+--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c
++++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c
+@@ -785,7 +785,6 @@ void override_training_settings(
+               lt_settings->lttpr_mode = LTTPR_MODE_NON_LTTPR;
+       dp_get_lttpr_mode_override(link, &lt_settings->lttpr_mode);
+-
+ }
+ enum dc_dp_training_pattern decide_cr_training_pattern(
+diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c
+index 5a5d48fadbf27..66d0fb1b9b9d2 100644
+--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c
++++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c
+@@ -142,6 +142,14 @@ void decide_8b_10b_training_settings(
+       lt_settings->lttpr_mode = dp_decide_8b_10b_lttpr_mode(link);
+       lt_settings->cr_pattern_time = get_cr_training_aux_rd_interval(link, link_setting, lt_settings->lttpr_mode);
+       dp_hw_to_dpcd_lane_settings(lt_settings, lt_settings->hw_lane_settings, lt_settings->dpcd_lane_settings);
++
++      /* Some embedded LTTPRs rely on receiving TPS2 before LT to interop reliably with sensitive VGA dongles
++       * This allows these LTTPRs to minimize freq/phase and skew variation during lock and deskew sequences
++       */
++      if ((link->chip_caps & AMD_EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK) ==
++                      AMD_EXT_DISPLAY_PATH_CAPS__DP_EARLY_8B10B_TPS2) {
++              lt_settings->lttpr_early_tps2 = true;
++      }
+ }
+ enum lttpr_mode dp_decide_8b_10b_lttpr_mode(struct dc_link *link)
+@@ -173,6 +181,42 @@ enum lttpr_mode dp_decide_8b_10b_lttpr_mode(struct dc_link *link)
+       return LTTPR_MODE_NON_LTTPR;
+ }
++static void set_link_settings_and_perform_early_tps2_retimer_pre_lt_sequence(struct dc_link *link,
++      const struct link_resource *link_res,
++      struct link_training_settings *lt_settings,
++      uint32_t lttpr_count)
++{
++      /* Vendor-specific LTTPR early TPS2 sequence:
++      * 1. Output TPS2
++      * 2. Wait 400us
++      * 3. Set link settings as usual
++      * 4. Write TPS1 to DP_TRAINING_PATTERN_SET_PHY_REPEATERx targeting LTTPR closest to host
++      * 5. Wait 1ms
++      * 6. Begin link training as usual
++      * */
++
++      uint32_t closest_lttpr_address_offset = dp_get_closest_lttpr_offset(lttpr_count);
++
++      union dpcd_training_pattern dpcd_pattern = {0};
++
++      dpcd_pattern.v1_4.TRAINING_PATTERN_SET = 1;
++      dpcd_pattern.v1_4.SCRAMBLING_DISABLE = 1;
++
++      DC_LOG_HW_LINK_TRAINING("%s\n GPU sends TPS2. Wait 400us.\n", __func__);
++
++      dp_set_hw_training_pattern(link, link_res, DP_TRAINING_PATTERN_SEQUENCE_2, DPRX);
++
++      dp_set_hw_lane_settings(link, link_res, lt_settings, DPRX);
++
++      udelay(400);
++
++      dpcd_set_link_settings(link, lt_settings);
++
++      core_link_write_dpcd(link, DP_TRAINING_PATTERN_SET_PHY_REPEATER1 + closest_lttpr_address_offset, &dpcd_pattern.raw, 1);
++
++      udelay(1000);
++      }
++
+ enum link_training_result perform_8b_10b_clock_recovery_sequence(
+       struct dc_link *link,
+       const struct link_resource *link_res,
+@@ -383,7 +427,7 @@ enum link_training_result dp_perform_8b_10b_link_training(
+ {
+       enum link_training_result status = LINK_TRAINING_SUCCESS;
+-      uint8_t repeater_cnt;
++      uint8_t repeater_cnt = dp_parse_lttpr_repeater_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt);
+       uint8_t repeater_id;
+       uint8_t lane = 0;
+@@ -391,14 +435,16 @@ enum link_training_result dp_perform_8b_10b_link_training(
+               start_clock_recovery_pattern_early(link, link_res, lt_settings, DPRX);
+       /* 1. set link rate, lane count and spread. */
+-      dpcd_set_link_settings(link, lt_settings);
++      if (lt_settings->lttpr_early_tps2)
++              set_link_settings_and_perform_early_tps2_retimer_pre_lt_sequence(link, link_res, lt_settings, repeater_cnt);
++      else
++              dpcd_set_link_settings(link, lt_settings);
+       if (lt_settings->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) {
+               /* 2. perform link training (set link training done
+                *  to false is done as well)
+                */
+-              repeater_cnt = dp_parse_lttpr_repeater_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt);
+               for (repeater_id = repeater_cnt; (repeater_id > 0 && status == LINK_TRAINING_SUCCESS);
+                               repeater_id--) {
+diff --git a/drivers/gpu/drm/amd/display/include/link_service_types.h b/drivers/gpu/drm/amd/display/include/link_service_types.h
+index 1867aac57cf2c..da74ed66c8f9d 100644
+--- a/drivers/gpu/drm/amd/display/include/link_service_types.h
++++ b/drivers/gpu/drm/amd/display/include/link_service_types.h
+@@ -89,6 +89,8 @@ struct link_training_settings {
+       bool enhanced_framing;
+       enum lttpr_mode lttpr_mode;
++      bool lttpr_early_tps2;
++
+       /* disallow different lanes to have different lane settings */
+       bool disallow_per_lane_settings;
+       /* dpcd lane settings will always use the same hw lane settings
+-- 
+2.39.5
+
diff --git a/queue-6.15/drm-amd-display-export-full-brightness-range-to-user.patch b/queue-6.15/drm-amd-display-export-full-brightness-range-to-user.patch
new file mode 100644 (file)
index 0000000..1beeff8
--- /dev/null
@@ -0,0 +1,133 @@
+From 7808a569951cb4f078d5a423ba56d1779a9f89e1 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 29 May 2025 09:46:32 -0500
+Subject: drm/amd/display: Export full brightness range to userspace
+
+From: Mario Limonciello <mario.limonciello@amd.com>
+
+[WHY]
+Userspace currently is offered a range from 0-0xFF but the PWM is
+programmed from 0-0xFFFF.  This can be limiting to some software
+that wants to apply greater granularity.
+
+[HOW]
+Convert internally to firmware values only when mapping custom
+brightness curves because these are in 0-0xFF range. Advertise full
+PWM range to userspace.
+
+Cc: Mario Limonciello <mario.limonciello@amd.com>
+Cc: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Roman Li <roman.li@amd.com>
+Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
+Signed-off-by: Alex Hung <alex.hung@amd.com>
+Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+(cherry picked from commit 8dbd72cb790058ce52279af38a43c2b302fdd3e5)
+Cc: stable@vger.kernel.org
+---
+ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 41 ++++++++++++-------
+ 1 file changed, 27 insertions(+), 14 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+index a9a719f051f90..c5c2f82448f21 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -4655,9 +4655,23 @@ static int get_brightness_range(const struct amdgpu_dm_backlight_caps *caps,
+       return 1;
+ }
++/* Rescale from [min..max] to [0..AMDGPU_MAX_BL_LEVEL] */
++static inline u32 scale_input_to_fw(int min, int max, u64 input)
++{
++      return DIV_ROUND_CLOSEST_ULL(input * AMDGPU_MAX_BL_LEVEL, max - min);
++}
++
++/* Rescale from [0..AMDGPU_MAX_BL_LEVEL] to [min..max] */
++static inline u32 scale_fw_to_input(int min, int max, u64 input)
++{
++      return min + DIV_ROUND_CLOSEST_ULL(input * (max - min), AMDGPU_MAX_BL_LEVEL);
++}
++
+ static void convert_custom_brightness(const struct amdgpu_dm_backlight_caps *caps,
+-                                    uint32_t *brightness)
++                                    unsigned int min, unsigned int max,
++                                    uint32_t *user_brightness)
+ {
++      u32 brightness = scale_input_to_fw(min, max, *user_brightness);
+       u8 prev_signal = 0, prev_lum = 0;
+       int i = 0;
+@@ -4668,7 +4682,7 @@ static void convert_custom_brightness(const struct amdgpu_dm_backlight_caps *cap
+               return;
+       /* choose start to run less interpolation steps */
+-      if (caps->luminance_data[caps->data_points/2].input_signal > *brightness)
++      if (caps->luminance_data[caps->data_points/2].input_signal > brightness)
+               i = caps->data_points/2;
+       do {
+               u8 signal = caps->luminance_data[i].input_signal;
+@@ -4679,17 +4693,18 @@ static void convert_custom_brightness(const struct amdgpu_dm_backlight_caps *cap
+                * brightness < signal: interpolate between previous and current luminance numerator
+                * brightness > signal: find next data point
+                */
+-              if (*brightness > signal) {
++              if (brightness > signal) {
+                       prev_signal = signal;
+                       prev_lum = lum;
+                       i++;
+                       continue;
+               }
+-              if (*brightness < signal)
++              if (brightness < signal)
+                       lum = prev_lum + DIV_ROUND_CLOSEST((lum - prev_lum) *
+-                                                         (*brightness - prev_signal),
++                                                         (brightness - prev_signal),
+                                                          signal - prev_signal);
+-              *brightness = DIV_ROUND_CLOSEST(lum * *brightness, 101);
++              *user_brightness = scale_fw_to_input(min, max,
++                                                   DIV_ROUND_CLOSEST(lum * brightness, 101));
+               return;
+       } while (i < caps->data_points);
+ }
+@@ -4702,11 +4717,10 @@ static u32 convert_brightness_from_user(const struct amdgpu_dm_backlight_caps *c
+       if (!get_brightness_range(caps, &min, &max))
+               return brightness;
+-      convert_custom_brightness(caps, &brightness);
++      convert_custom_brightness(caps, min, max, &brightness);
+-      // Rescale 0..255 to min..max
+-      return min + DIV_ROUND_CLOSEST((max - min) * brightness,
+-                                     AMDGPU_MAX_BL_LEVEL);
++      // Rescale 0..max to min..max
++      return min + DIV_ROUND_CLOSEST_ULL((u64)(max - min) * brightness, max);
+ }
+ static u32 convert_brightness_to_user(const struct amdgpu_dm_backlight_caps *caps,
+@@ -4719,8 +4733,8 @@ static u32 convert_brightness_to_user(const struct amdgpu_dm_backlight_caps *cap
+       if (brightness < min)
+               return 0;
+-      // Rescale min..max to 0..255
+-      return DIV_ROUND_CLOSEST(AMDGPU_MAX_BL_LEVEL * (brightness - min),
++      // Rescale min..max to 0..max
++      return DIV_ROUND_CLOSEST_ULL((u64)max * (brightness - min),
+                                max - min);
+ }
+@@ -4870,11 +4884,10 @@ amdgpu_dm_register_backlight_device(struct amdgpu_dm_connector *aconnector)
+               drm_dbg(drm, "Backlight caps: min: %d, max: %d, ac %d, dc %d\n", min, max,
+                       caps->ac_level, caps->dc_level);
+       } else
+-              props.brightness = AMDGPU_MAX_BL_LEVEL;
++              props.brightness = props.max_brightness = AMDGPU_MAX_BL_LEVEL;
+       if (caps->data_points && !(amdgpu_dc_debug_mask & DC_DISABLE_CUSTOM_BRIGHTNESS_CURVE))
+               drm_info(drm, "Using custom brightness curve\n");
+-      props.max_brightness = AMDGPU_MAX_BL_LEVEL;
+       props.type = BACKLIGHT_RAW;
+       snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d",
+-- 
+2.39.5
+
diff --git a/queue-6.15/drm-amd-display-fix-default-dc-and-ac-levels.patch b/queue-6.15/drm-amd-display-fix-default-dc-and-ac-levels.patch
new file mode 100644 (file)
index 0000000..bced5d5
--- /dev/null
@@ -0,0 +1,60 @@
+From 6eed9003aecde2bcc4d5078961778db891d70d20 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 14 May 2025 16:06:40 -0500
+Subject: drm/amd/display: Fix default DC and AC levels
+
+From: Mario Limonciello <mario.limonciello@amd.com>
+
+[ Upstream commit 8b5f3a229a70d242322b78c8e13744ca00212def ]
+
+[Why]
+DC and AC levels are advertised in a percentage, not a luminance.
+
+[How]
+Scale DC and AC levels to supported values.
+
+Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4221
+Reviewed-by: Alex Hung <alex.hung@amd.com>
+Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
+Signed-off-by: Wayne Lin <wayne.lin@amd.com>
+Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 11 ++++++++---
+ 1 file changed, 8 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+index 96118a0e1ffeb..389748c420b02 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -4834,6 +4834,7 @@ amdgpu_dm_register_backlight_device(struct amdgpu_dm_connector *aconnector)
+       struct backlight_properties props = { 0 };
+       struct amdgpu_dm_backlight_caps caps = { 0 };
+       char bl_name[16];
++      int min, max;
+       if (aconnector->bl_idx == -1)
+               return;
+@@ -4846,11 +4847,15 @@ amdgpu_dm_register_backlight_device(struct amdgpu_dm_connector *aconnector)
+       }
+       amdgpu_acpi_get_backlight_caps(&caps);
+-      if (caps.caps_valid) {
++      if (caps.caps_valid && get_brightness_range(&caps, &min, &max)) {
+               if (power_supply_is_system_supplied() > 0)
+-                      props.brightness = caps.ac_level;
++                      props.brightness = (max - min) * DIV_ROUND_CLOSEST(caps.ac_level, 100);
+               else
+-                      props.brightness = caps.dc_level;
++                      props.brightness = (max - min) * DIV_ROUND_CLOSEST(caps.dc_level, 100);
++              /* min is zero, so max needs to be adjusted */
++              props.max_brightness = max - min;
++              drm_dbg(drm, "Backlight caps: min: %d, max: %d, ac %d, dc %d\n", min, max,
++                      caps.ac_level, caps.dc_level);
+       } else
+               props.brightness = AMDGPU_MAX_BL_LEVEL;
+-- 
+2.39.5
+
diff --git a/queue-6.15/drm-amd-display-get-lttpr-ieee-oui-device-id-from-cl.patch b/queue-6.15/drm-amd-display-get-lttpr-ieee-oui-device-id-from-cl.patch
new file mode 100644 (file)
index 0000000..467c62c
--- /dev/null
@@ -0,0 +1,142 @@
+From da322003b880402456776e60777932936fd17d3a Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 26 Feb 2025 10:03:48 -0500
+Subject: drm/amd/display: Get LTTPR IEEE OUI/Device ID From Closest LTTPR To
+ Host
+
+From: Michael Strauss <michael.strauss@amd.com>
+
+[ Upstream commit d358a51444c88bcc995e471dc8cc840f19e4b374 ]
+
+[WHY]
+These fields are read for the explicit purpose of detecting embedded LTTPRs
+(i.e. between host ASIC and the user-facing port), and thus need to
+calculate the correct DPCD address offset based on LTTPR count to target
+the appropriate LTTPR's DPCD register space with these queries.
+
+[HOW]
+Cascaded LTTPRs in a link each snoop and increment LTTPR count when queried
+via DPCD read, so an LTTPR embedded in a source device (e.g. USB4 port on a
+laptop) will always be addressible using the max LTTPR count seen by the
+host. Therefore we simply need to use a recently added helper function to
+calculate the correct DPCD address to target potentially embedded LTTPRs
+based on the received LTTPR count.
+
+Cc: Mario Limonciello <mario.limonciello@amd.com>
+Cc: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Wenjing Liu <wenjing.liu@amd.com>
+Signed-off-by: Michael Strauss <michael.strauss@amd.com>
+Signed-off-by: Alex Hung <alex.hung@amd.com>
+Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+(cherry picked from commit 791897f5c77a2a65d0e500be4743af2ddf6eb061)
+Cc: stable@vger.kernel.org
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/gpu/drm/amd/display/dc/dc_dp_types.h  |  4 +-
+ .../dc/link/protocols/link_dp_capability.c    | 38 +++++++++++++++----
+ 2 files changed, 33 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
+index 77c87ad572207..bbd6701096ca9 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
++++ b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
+@@ -1157,8 +1157,8 @@ struct dc_lttpr_caps {
+       union dp_128b_132b_supported_lttpr_link_rates supported_128b_132b_rates;
+       union dp_alpm_lttpr_cap alpm;
+       uint8_t aux_rd_interval[MAX_REPEATER_CNT - 1];
+-      uint8_t lttpr_ieee_oui[3];
+-      uint8_t lttpr_device_id[6];
++      uint8_t lttpr_ieee_oui[3]; // Always read from closest LTTPR to host
++      uint8_t lttpr_device_id[6]; // Always read from closest LTTPR to host
+ };
+ struct dc_dongle_dfp_cap_ext {
+diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
+index 9d49e77a24a1f..ed9d396e3d0ea 100644
+--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
++++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
+@@ -385,9 +385,15 @@ bool dp_is_128b_132b_signal(struct pipe_ctx *pipe_ctx)
+ bool dp_is_lttpr_present(struct dc_link *link)
+ {
+       /* Some sink devices report invalid LTTPR revision, so don't validate against that cap */
+-      return (dp_parse_lttpr_repeater_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt) != 0 &&
++      uint32_t lttpr_count = dp_parse_lttpr_repeater_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt);
++      bool is_lttpr_present = (lttpr_count > 0 &&
+                       link->dpcd_caps.lttpr_caps.max_lane_count > 0 &&
+                       link->dpcd_caps.lttpr_caps.max_lane_count <= 4);
++
++      if (lttpr_count > 0 && !is_lttpr_present)
++              DC_LOG_ERROR("LTTPR count is nonzero but invalid lane count reported. Assuming no LTTPR present.\n");
++
++      return is_lttpr_present;
+ }
+ /* in DP compliance test, DPR-120 may have
+@@ -1551,6 +1557,8 @@ enum dc_status dp_retrieve_lttpr_cap(struct dc_link *link)
+       uint8_t lttpr_dpcd_data[10] = {0};
+       enum dc_status status;
+       bool is_lttpr_present;
++      uint32_t lttpr_count;
++      uint32_t closest_lttpr_offset;
+       /* Logic to determine LTTPR support*/
+       bool vbios_lttpr_interop = link->dc->caps.vbios_lttpr_aware;
+@@ -1602,20 +1610,22 @@ enum dc_status dp_retrieve_lttpr_cap(struct dc_link *link)
+                       lttpr_dpcd_data[DP_LTTPR_ALPM_CAPABILITIES -
+                                                       DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
++      lttpr_count = dp_parse_lttpr_repeater_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt);
++
+       /* If this chip cap is set, at least one retimer must exist in the chain
+        * Override count to 1 if we receive a known bad count (0 or an invalid value) */
+       if (((link->chip_caps & AMD_EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK) == AMD_EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) &&
+-                      (dp_parse_lttpr_repeater_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt) == 0)) {
++                      lttpr_count == 0) {
+               /* If you see this message consistently, either the host platform has FIXED_VS flag
+                * incorrectly configured or the sink device is returning an invalid count.
+                */
+               DC_LOG_ERROR("lttpr_caps phy_repeater_cnt is 0x%x, forcing it to 0x80.",
+                            link->dpcd_caps.lttpr_caps.phy_repeater_cnt);
+               link->dpcd_caps.lttpr_caps.phy_repeater_cnt = 0x80;
++              lttpr_count = 1;
+               DC_LOG_DC("lttpr_caps forced phy_repeater_cnt = %d\n", link->dpcd_caps.lttpr_caps.phy_repeater_cnt);
+       }
+-      /* Attempt to train in LTTPR transparent mode if repeater count exceeds 8. */
+       is_lttpr_present = dp_is_lttpr_present(link);
+       DC_LOG_DC("is_lttpr_present = %d\n", is_lttpr_present);
+@@ -1623,11 +1633,25 @@ enum dc_status dp_retrieve_lttpr_cap(struct dc_link *link)
+       if (is_lttpr_present) {
+               CONN_DATA_DETECT(link, lttpr_dpcd_data, sizeof(lttpr_dpcd_data), "LTTPR Caps: ");
+-              core_link_read_dpcd(link, DP_LTTPR_IEEE_OUI, link->dpcd_caps.lttpr_caps.lttpr_ieee_oui, sizeof(link->dpcd_caps.lttpr_caps.lttpr_ieee_oui));
+-              CONN_DATA_DETECT(link, link->dpcd_caps.lttpr_caps.lttpr_ieee_oui, sizeof(link->dpcd_caps.lttpr_caps.lttpr_ieee_oui), "LTTPR IEEE OUI: ");
++              // Identify closest LTTPR to determine if workarounds required for known embedded LTTPR
++              closest_lttpr_offset = dp_get_closest_lttpr_offset(lttpr_count);
+-              core_link_read_dpcd(link, DP_LTTPR_DEVICE_ID, link->dpcd_caps.lttpr_caps.lttpr_device_id, sizeof(link->dpcd_caps.lttpr_caps.lttpr_device_id));
+-              CONN_DATA_DETECT(link, link->dpcd_caps.lttpr_caps.lttpr_device_id, sizeof(link->dpcd_caps.lttpr_caps.lttpr_device_id), "LTTPR Device ID: ");
++              core_link_read_dpcd(link, (DP_LTTPR_IEEE_OUI + closest_lttpr_offset),
++                              link->dpcd_caps.lttpr_caps.lttpr_ieee_oui, sizeof(link->dpcd_caps.lttpr_caps.lttpr_ieee_oui));
++              core_link_read_dpcd(link, (DP_LTTPR_DEVICE_ID + closest_lttpr_offset),
++                              link->dpcd_caps.lttpr_caps.lttpr_device_id, sizeof(link->dpcd_caps.lttpr_caps.lttpr_device_id));
++
++              if (lttpr_count > 1) {
++                      CONN_DATA_DETECT(link, link->dpcd_caps.lttpr_caps.lttpr_ieee_oui, sizeof(link->dpcd_caps.lttpr_caps.lttpr_ieee_oui),
++                                      "Closest LTTPR To Host's IEEE OUI: ");
++                      CONN_DATA_DETECT(link, link->dpcd_caps.lttpr_caps.lttpr_device_id, sizeof(link->dpcd_caps.lttpr_caps.lttpr_device_id),
++                                      "Closest LTTPR To Host's LTTPR Device ID: ");
++              } else {
++                      CONN_DATA_DETECT(link, link->dpcd_caps.lttpr_caps.lttpr_ieee_oui, sizeof(link->dpcd_caps.lttpr_caps.lttpr_ieee_oui),
++                                      "LTTPR IEEE OUI: ");
++                      CONN_DATA_DETECT(link, link->dpcd_caps.lttpr_caps.lttpr_device_id, sizeof(link->dpcd_caps.lttpr_caps.lttpr_device_id),
++                                      "LTTPR Device ID: ");
++              }
+       }
+       return status;
+-- 
+2.39.5
+
diff --git a/queue-6.15/drm-amd-display-only-read-acpi-backlight-caps-once.patch b/queue-6.15/drm-amd-display-only-read-acpi-backlight-caps-once.patch
new file mode 100644 (file)
index 0000000..b888802
--- /dev/null
@@ -0,0 +1,74 @@
+From 6db7dead46f8560af4845a305669a34d0af7e8e9 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 29 May 2025 11:33:44 -0500
+Subject: drm/amd/display: Only read ACPI backlight caps once
+
+From: Mario Limonciello <mario.limonciello@amd.com>
+
+[ Upstream commit ffcaed1d7ecef31198000dfbbea791f30f7ca437 ]
+
+[WHY]
+Backlight caps are read already in amdgpu_dm_update_backlight_caps().
+They may be updated by update_connector_ext_caps(). Reading again when
+registering backlight device may cause wrong values to be used.
+
+[HOW]
+Use backlight caps already registered to the dm.
+
+Cc: Mario Limonciello <mario.limonciello@amd.com>
+Cc: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Roman Li <roman.li@amd.com>
+Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
+Signed-off-by: Alex Hung <alex.hung@amd.com>
+Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+(cherry picked from commit 148144f6d2f14b02eaaa39b86bbe023cbff350bd)
+Cc: stable@vger.kernel.org
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 14 +++++++-------
+ 1 file changed, 7 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+index 389748c420b02..e61166a8230b6 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -4832,7 +4832,7 @@ amdgpu_dm_register_backlight_device(struct amdgpu_dm_connector *aconnector)
+       struct drm_device *drm = aconnector->base.dev;
+       struct amdgpu_display_manager *dm = &drm_to_adev(drm)->dm;
+       struct backlight_properties props = { 0 };
+-      struct amdgpu_dm_backlight_caps caps = { 0 };
++      struct amdgpu_dm_backlight_caps *caps;
+       char bl_name[16];
+       int min, max;
+@@ -4846,20 +4846,20 @@ amdgpu_dm_register_backlight_device(struct amdgpu_dm_connector *aconnector)
+               return;
+       }
+-      amdgpu_acpi_get_backlight_caps(&caps);
+-      if (caps.caps_valid && get_brightness_range(&caps, &min, &max)) {
++      caps = &dm->backlight_caps[aconnector->bl_idx];
++      if (get_brightness_range(caps, &min, &max)) {
+               if (power_supply_is_system_supplied() > 0)
+-                      props.brightness = (max - min) * DIV_ROUND_CLOSEST(caps.ac_level, 100);
++                      props.brightness = (max - min) * DIV_ROUND_CLOSEST(caps->ac_level, 100);
+               else
+-                      props.brightness = (max - min) * DIV_ROUND_CLOSEST(caps.dc_level, 100);
++                      props.brightness = (max - min) * DIV_ROUND_CLOSEST(caps->dc_level, 100);
+               /* min is zero, so max needs to be adjusted */
+               props.max_brightness = max - min;
+               drm_dbg(drm, "Backlight caps: min: %d, max: %d, ac %d, dc %d\n", min, max,
+-                      caps.ac_level, caps.dc_level);
++                      caps->ac_level, caps->dc_level);
+       } else
+               props.brightness = AMDGPU_MAX_BL_LEVEL;
+-      if (caps.data_points && !(amdgpu_dc_debug_mask & DC_DISABLE_CUSTOM_BRIGHTNESS_CURVE))
++      if (caps->data_points && !(amdgpu_dc_debug_mask & DC_DISABLE_CUSTOM_BRIGHTNESS_CURVE))
+               drm_info(drm, "Using custom brightness curve\n");
+       props.max_brightness = AMDGPU_MAX_BL_LEVEL;
+       props.type = BACKLIGHT_RAW;
+-- 
+2.39.5
+
diff --git a/queue-6.15/drm-amd-display-optimize-custom-brightness-curve.patch b/queue-6.15/drm-amd-display-optimize-custom-brightness-curve.patch
new file mode 100644 (file)
index 0000000..146411a
--- /dev/null
@@ -0,0 +1,110 @@
+From 6e1e126b02f71ac44a77136dcc8f208dc63aadba Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 24 Mar 2025 12:57:25 -0500
+Subject: drm/amd/display: Optimize custom brightness curve
+
+From: Mario Limonciello <mario.limonciello@amd.com>
+
+[Why]
+When BIOS includes a lot of custom brightness data points, walking
+the entire list can be time consuming.  This is most noticed when
+dragging a power slider.  The "higher" values are "slower" to drag
+around.
+
+[How]
+Move custom brightness calculation loop into a static function. Before
+starting the loop check the "half way" data point to see how it compares
+to the input.  If greater than the half way data point use that as the
+starting point instead.
+
+Reviewed-by: Alex Hung <alex.hung@amd.com>
+Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
+Signed-off-by: Roman Li <roman.li@amd.com>
+Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 53 ++++++++++++-------
+ 1 file changed, 33 insertions(+), 20 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+index e61166a8230b6..a9a719f051f90 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -4655,41 +4655,54 @@ static int get_brightness_range(const struct amdgpu_dm_backlight_caps *caps,
+       return 1;
+ }
+-static u32 convert_brightness_from_user(const struct amdgpu_dm_backlight_caps *caps,
+-                                      uint32_t brightness)
++static void convert_custom_brightness(const struct amdgpu_dm_backlight_caps *caps,
++                                    uint32_t *brightness)
+ {
+-      unsigned int min, max;
+       u8 prev_signal = 0, prev_lum = 0;
++      int i = 0;
+-      if (!get_brightness_range(caps, &min, &max))
+-              return brightness;
+-
+-      for (int i = 0; i < caps->data_points; i++) {
+-              u8 signal, lum;
++      if (amdgpu_dc_debug_mask & DC_DISABLE_CUSTOM_BRIGHTNESS_CURVE)
++              return;
+-              if (amdgpu_dc_debug_mask & DC_DISABLE_CUSTOM_BRIGHTNESS_CURVE)
+-                      break;
++      if (!caps->data_points)
++              return;
+-              signal = caps->luminance_data[i].input_signal;
+-              lum = caps->luminance_data[i].luminance;
++      /* choose start to run less interpolation steps */
++      if (caps->luminance_data[caps->data_points/2].input_signal > *brightness)
++              i = caps->data_points/2;
++      do {
++              u8 signal = caps->luminance_data[i].input_signal;
++              u8 lum = caps->luminance_data[i].luminance;
+               /*
+                * brightness == signal: luminance is percent numerator
+                * brightness < signal: interpolate between previous and current luminance numerator
+                * brightness > signal: find next data point
+                */
+-              if (brightness < signal)
+-                      lum = prev_lum + DIV_ROUND_CLOSEST((lum - prev_lum) *
+-                                                         (brightness - prev_signal),
+-                                                         signal - prev_signal);
+-              else if (brightness > signal) {
++              if (*brightness > signal) {
+                       prev_signal = signal;
+                       prev_lum = lum;
++                      i++;
+                       continue;
+               }
+-              brightness = DIV_ROUND_CLOSEST(lum * brightness, 101);
+-              break;
+-      }
++              if (*brightness < signal)
++                      lum = prev_lum + DIV_ROUND_CLOSEST((lum - prev_lum) *
++                                                         (*brightness - prev_signal),
++                                                         signal - prev_signal);
++              *brightness = DIV_ROUND_CLOSEST(lum * *brightness, 101);
++              return;
++      } while (i < caps->data_points);
++}
++
++static u32 convert_brightness_from_user(const struct amdgpu_dm_backlight_caps *caps,
++                                      uint32_t brightness)
++{
++      unsigned int min, max;
++
++      if (!get_brightness_range(caps, &min, &max))
++              return brightness;
++
++      convert_custom_brightness(caps, &brightness);
+       // Rescale 0..255 to min..max
+       return min + DIV_ROUND_CLOSEST((max - min) * brightness,
+-- 
+2.39.5
+
diff --git a/queue-6.15/drm-amdgpu-mes-add-missing-locking-in-helper-functio.patch b/queue-6.15/drm-amdgpu-mes-add-missing-locking-in-helper-functio.patch
new file mode 100644 (file)
index 0000000..03c6579
--- /dev/null
@@ -0,0 +1,106 @@
+From 347e9ff49442bf00f0af5cd13a62da85593c2b89 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 19 May 2025 15:46:25 -0400
+Subject: drm/amdgpu/mes: add missing locking in helper functions
+
+From: Alex Deucher <alexander.deucher@amd.com>
+
+[ Upstream commit 40f970ba7a4ab77be2ffe6d50a70416c8876496a ]
+
+We need to take the MES lock.
+
+Reviewed-by: Michael Chen <michael.chen@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Cc: stable@vger.kernel.org
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 16 ++++++++++++++++
+ 1 file changed, 16 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
+index 5590ad5e8cd76..7164948001e9d 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
+@@ -836,7 +836,9 @@ int amdgpu_mes_map_legacy_queue(struct amdgpu_device *adev,
+       queue_input.mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
+       queue_input.wptr_addr = ring->wptr_gpu_addr;
++      amdgpu_mes_lock(&adev->mes);
+       r = adev->mes.funcs->map_legacy_queue(&adev->mes, &queue_input);
++      amdgpu_mes_unlock(&adev->mes);
+       if (r)
+               DRM_ERROR("failed to map legacy queue\n");
+@@ -859,7 +861,9 @@ int amdgpu_mes_unmap_legacy_queue(struct amdgpu_device *adev,
+       queue_input.trail_fence_addr = gpu_addr;
+       queue_input.trail_fence_data = seq;
++      amdgpu_mes_lock(&adev->mes);
+       r = adev->mes.funcs->unmap_legacy_queue(&adev->mes, &queue_input);
++      amdgpu_mes_unlock(&adev->mes);
+       if (r)
+               DRM_ERROR("failed to unmap legacy queue\n");
+@@ -886,7 +890,9 @@ int amdgpu_mes_reset_legacy_queue(struct amdgpu_device *adev,
+       queue_input.vmid = vmid;
+       queue_input.use_mmio = use_mmio;
++      amdgpu_mes_lock(&adev->mes);
+       r = adev->mes.funcs->reset_legacy_queue(&adev->mes, &queue_input);
++      amdgpu_mes_unlock(&adev->mes);
+       if (r)
+               DRM_ERROR("failed to reset legacy queue\n");
+@@ -916,7 +922,9 @@ uint32_t amdgpu_mes_rreg(struct amdgpu_device *adev, uint32_t reg)
+               goto error;
+       }
++      amdgpu_mes_lock(&adev->mes);
+       r = adev->mes.funcs->misc_op(&adev->mes, &op_input);
++      amdgpu_mes_unlock(&adev->mes);
+       if (r)
+               DRM_ERROR("failed to read reg (0x%x)\n", reg);
+       else
+@@ -944,7 +952,9 @@ int amdgpu_mes_wreg(struct amdgpu_device *adev,
+               goto error;
+       }
++      amdgpu_mes_lock(&adev->mes);
+       r = adev->mes.funcs->misc_op(&adev->mes, &op_input);
++      amdgpu_mes_unlock(&adev->mes);
+       if (r)
+               DRM_ERROR("failed to write reg (0x%x)\n", reg);
+@@ -971,7 +981,9 @@ int amdgpu_mes_reg_write_reg_wait(struct amdgpu_device *adev,
+               goto error;
+       }
++      amdgpu_mes_lock(&adev->mes);
+       r = adev->mes.funcs->misc_op(&adev->mes, &op_input);
++      amdgpu_mes_unlock(&adev->mes);
+       if (r)
+               DRM_ERROR("failed to reg_write_reg_wait\n");
+@@ -996,7 +1008,9 @@ int amdgpu_mes_reg_wait(struct amdgpu_device *adev, uint32_t reg,
+               goto error;
+       }
++      amdgpu_mes_lock(&adev->mes);
+       r = adev->mes.funcs->misc_op(&adev->mes, &op_input);
++      amdgpu_mes_unlock(&adev->mes);
+       if (r)
+               DRM_ERROR("failed to reg_write_reg_wait\n");
+@@ -1687,7 +1701,9 @@ static int amdgpu_mes_set_enforce_isolation(struct amdgpu_device *adev,
+               goto error;
+       }
++      amdgpu_mes_lock(&adev->mes);
+       r = adev->mes.funcs->misc_op(&adev->mes, &op_input);
++      amdgpu_mes_unlock(&adev->mes);
+       if (r)
+               dev_err(adev->dev, "failed to change_config.\n");
+-- 
+2.39.5
+
diff --git a/queue-6.15/sched_ext-make-scx_group_set_weight-always-update-tg.patch b/queue-6.15/sched_ext-make-scx_group_set_weight-always-update-tg.patch
new file mode 100644 (file)
index 0000000..d23000e
--- /dev/null
@@ -0,0 +1,44 @@
+From 27897b7a853994b2123a6fc3d9dfef75afc592b6 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 1 Jul 2025 21:58:33 -0400
+Subject: sched_ext: Make scx_group_set_weight() always update tg->scx.weight
+
+[ Upstream commit c50784e99f0e7199cdb12dbddf02229b102744ef ]
+
+Otherwise, tg->scx.weight can go out of sync while scx_cgroup is not enabled
+and ops.cgroup_init() may be called with a stale weight value.
+
+Signed-off-by: Tejun Heo <tj@kernel.org>
+Fixes: 819513666966 ("sched_ext: Add cgroup support")
+Cc: stable@vger.kernel.org # v6.12+
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ kernel/sched/ext.c | 12 ++++++------
+ 1 file changed, 6 insertions(+), 6 deletions(-)
+
+diff --git a/kernel/sched/ext.c b/kernel/sched/ext.c
+index afaf49e5ecb97..86ce43fa36693 100644
+--- a/kernel/sched/ext.c
++++ b/kernel/sched/ext.c
+@@ -4074,12 +4074,12 @@ void scx_group_set_weight(struct task_group *tg, unsigned long weight)
+ {
+       percpu_down_read(&scx_cgroup_rwsem);
+-      if (scx_cgroup_enabled && tg->scx_weight != weight) {
+-              if (SCX_HAS_OP(cgroup_set_weight))
+-                      SCX_CALL_OP(SCX_KF_UNLOCKED, cgroup_set_weight, NULL,
+-                                  tg_cgrp(tg), weight);
+-              tg->scx_weight = weight;
+-      }
++      if (scx_cgroup_enabled && SCX_HAS_OP(cgroup_set_weight) &&
++          tg->scx_weight != weight)
++              SCX_CALL_OP(SCX_KF_UNLOCKED, cgroup_set_weight, NULL,
++                          tg_cgrp(tg), weight);
++
++      tg->scx_weight = weight;
+       percpu_up_read(&scx_cgroup_rwsem);
+ }
+-- 
+2.39.5
+
index 0e3ca9615211328d1f7ceff31736ed3f9f4fea42..7a160cb126debf9435429da93cd48291d641b563 100644 (file)
@@ -238,3 +238,17 @@ drm-amdgpu-add-kicker-fws-loading-for-gfx11-smu13-psp13.patch
 drm-amd-display-add-more-checks-for-dsc-hubp-ono-guarantees.patch
 drm-amd-display-add-dc-cap-for-dp-tunneling.patch
 drm-amd-display-fix-mpv-playback-corruption-on-weston.patch
+arm64-dts-qcom-commonize-x1-crd-dtsi.patch
+arm64-dts-qcom-x1e80100-crd-mark-l12b-and-l15b-alway.patch
+arm64-dts-qcom-x1e78100-t14s-mark-l12b-and-l15b-alwa.patch
+arm64-dts-qcom-x1-crd-fix-vreg_l2j_1p2-voltage.patch
+crypto-powerpc-poly1305-add-depends-on-broken-for-no.patch
+drm-amdgpu-mes-add-missing-locking-in-helper-functio.patch
+arm64-dts-qcom-x1e78100-t14s-fix-missing-hid-supplie.patch
+sched_ext-make-scx_group_set_weight-always-update-tg.patch
+drm-amd-display-add-early-8b-10b-channel-equalizatio.patch
+drm-amd-display-get-lttpr-ieee-oui-device-id-from-cl.patch
+drm-amd-display-fix-default-dc-and-ac-levels.patch
+drm-amd-display-only-read-acpi-backlight-caps-once.patch
+drm-amd-display-optimize-custom-brightness-curve.patch
+drm-amd-display-export-full-brightness-range-to-user.patch