--- /dev/null
+From wse@tuxedocomputers.com Thu Oct 27 12:25:48 2022
+From: Werner Sembach <wse@tuxedocomputers.com>
+Date: Wed, 26 Oct 2022 17:22:46 +0200
+Subject: [PATCH v3] ACPI: video: Force backlight native for more TongFang devices
+To: stable@vger.kernel.org
+Cc: hdegoede@redhat.com, daniel@ffwll.ch, airlied@redhat.com, lenb@kernel.org, rafael.j.wysocki@intel.com
+Message-ID: <20221026152246.24990-1-wse@tuxedocomputers.com>
+
+From: Werner Sembach <wse@tuxedocomputers.com>
+
+commit 3dbc80a3e4c55c4a5b89ef207bed7b7de36157b4 upstream.
+
+This commit is very different from the upstream commit! It fixes the same
+issue by adding more quirks, rather then the general fix from the 6.1
+kernel, because the general fix from the 6.1 kernel is part of a larger
+refactoring of the backlight code which is not suitable for the stable
+series.
+
+As described in "ACPI: video: Drop NL5x?U, PF4NU1F and PF5?U??
+acpi_backlight=native quirks" (10212754a0d2) the upstream commit "ACPI:
+video: Make backlight class device registration a separate step (v2)"
+(3dbc80a3e4c5) makes these quirks unnecessary. However as mentioned in this
+bugtracker ticket https://bugzilla.kernel.org/show_bug.cgi?id=215683#c17
+the upstream fix is part of a larger patchset that is overall too complex
+for stable.
+
+The TongFang GKxNRxx, GMxNGxx, GMxZGxx, and GMxRGxx / TUXEDO
+Stellaris/Polaris Gen 1-4, have the same problem as the Clevo NL5xRU and
+NL5xNU / TUXEDO Aura 15 Gen1 and Gen2:
+They have a working native and video interface for screen backlight.
+However the default detection mechanism first registers the video interface
+before unregistering it again and switching to the native interface during
+boot. This results in a dangling SBIOS request for backlight change for
+some reason, causing the backlight to switch to ~2% once per boot on the
+first power cord connect or disconnect event. Setting the native interface
+explicitly circumvents this buggy behaviour by avoiding the unregistering
+process.
+
+Reviewed-by: Hans de Goede <hdegoede@redhat.com>
+Signed-off-by: Werner Sembach <wse@tuxedocomputers.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/acpi/video_detect.c | 64 ++++++++++++++++++++++++++++++++++++++++++++
+ 1 file changed, 64 insertions(+)
+
+--- a/drivers/acpi/video_detect.c
++++ b/drivers/acpi/video_detect.c
+@@ -464,6 +464,70 @@ static const struct dmi_system_id video_
+ },
+ },
+ /*
++ * More Tongfang devices with the same issue as the Clevo NL5xRU and
++ * NL5xNU/TUXEDO Aura 15 Gen1 and Gen2. See the description above.
++ */
++ {
++ .callback = video_detect_force_native,
++ .ident = "TongFang GKxNRxx",
++ .matches = {
++ DMI_MATCH(DMI_BOARD_NAME, "GKxNRxx"),
++ },
++ },
++ {
++ .callback = video_detect_force_native,
++ .ident = "TongFang GKxNRxx",
++ .matches = {
++ DMI_MATCH(DMI_SYS_VENDOR, "TUXEDO"),
++ DMI_MATCH(DMI_BOARD_NAME, "POLARIS1501A1650TI"),
++ },
++ },
++ {
++ .callback = video_detect_force_native,
++ .ident = "TongFang GKxNRxx",
++ .matches = {
++ DMI_MATCH(DMI_SYS_VENDOR, "TUXEDO"),
++ DMI_MATCH(DMI_BOARD_NAME, "POLARIS1501A2060"),
++ },
++ },
++ {
++ .callback = video_detect_force_native,
++ .ident = "TongFang GKxNRxx",
++ .matches = {
++ DMI_MATCH(DMI_SYS_VENDOR, "TUXEDO"),
++ DMI_MATCH(DMI_BOARD_NAME, "POLARIS1701A1650TI"),
++ },
++ },
++ {
++ .callback = video_detect_force_native,
++ .ident = "TongFang GKxNRxx",
++ .matches = {
++ DMI_MATCH(DMI_SYS_VENDOR, "TUXEDO"),
++ DMI_MATCH(DMI_BOARD_NAME, "POLARIS1701A2060"),
++ },
++ },
++ {
++ .callback = video_detect_force_native,
++ .ident = "TongFang GMxNGxx",
++ .matches = {
++ DMI_MATCH(DMI_BOARD_NAME, "GMxNGxx"),
++ },
++ },
++ {
++ .callback = video_detect_force_native,
++ .ident = "TongFang GMxZGxx",
++ .matches = {
++ DMI_MATCH(DMI_BOARD_NAME, "GMxZGxx"),
++ },
++ },
++ {
++ .callback = video_detect_force_native,
++ .ident = "TongFang GMxRGxx",
++ .matches = {
++ DMI_MATCH(DMI_BOARD_NAME, "GMxRGxx"),
++ },
++ },
++ /*
+ * Desktops which falsely report a backlight and which our heuristics
+ * for this do not catch.
+ */
--- /dev/null
+From foo@baz Thu Oct 27 12:19:05 PM CEST 2022
+From: Conor Dooley <conor.dooley@microchip.com>
+Date: Wed, 19 Oct 2022 13:52:09 +0100
+Subject: arm64: topology: move store_cpu_topology() to shared code
+To: <stable@vger.kernel.org>
+Cc: <conor.dooley@microchip.com>, <Brice.Goglin@inria.fr>, <atishp@atishpatra.org>, <catalin.marinas@arm.com>, <gregkh@linuxfoundation.org>, <linux-arm-kernel@lists.infradead.org>, <linux-kernel@vger.kernel.org>, <linux-riscv@lists.infradead.org>, <palmer@dabbelt.com>, <sudeep.holla@arm.com>, <will@kernel.org>, Atish Patra <atishp@rivosinc.com>
+Message-ID: <20221019125209.2844943-1-conor.dooley@microchip.com>
+
+From: Conor Dooley <conor.dooley@microchip.com>
+
+commit 456797da792fa7cbf6698febf275fe9b36691f78 upstream.
+
+arm64's method of defining a default cpu topology requires only minimal
+changes to apply to RISC-V also. The current arm64 implementation exits
+early in a uniprocessor configuration by reading MPIDR & claiming that
+uniprocessor can rely on the default values.
+
+This is appears to be a hangover from prior to '3102bc0e6ac7 ("arm64:
+topology: Stop using MPIDR for topology information")', because the
+current code just assigns default values for multiprocessor systems.
+
+With the MPIDR references removed, store_cpu_topolgy() can be moved to
+the common arch_topology code.
+
+Reviewed-by: Sudeep Holla <sudeep.holla@arm.com>
+Acked-by: Catalin Marinas <catalin.marinas@arm.com>
+Reviewed-by: Atish Patra <atishp@rivosinc.com>
+Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ arch/arm64/kernel/topology.c | 40 ----------------------------------------
+ drivers/base/arch_topology.c | 19 +++++++++++++++++++
+ 2 files changed, 19 insertions(+), 40 deletions(-)
+
+--- a/arch/arm64/kernel/topology.c
++++ b/arch/arm64/kernel/topology.c
+@@ -21,46 +21,6 @@
+ #include <asm/cputype.h>
+ #include <asm/topology.h>
+
+-void store_cpu_topology(unsigned int cpuid)
+-{
+- struct cpu_topology *cpuid_topo = &cpu_topology[cpuid];
+- u64 mpidr;
+-
+- if (cpuid_topo->package_id != -1)
+- goto topology_populated;
+-
+- mpidr = read_cpuid_mpidr();
+-
+- /* Uniprocessor systems can rely on default topology values */
+- if (mpidr & MPIDR_UP_BITMASK)
+- return;
+-
+- /*
+- * This would be the place to create cpu topology based on MPIDR.
+- *
+- * However, it cannot be trusted to depict the actual topology; some
+- * pieces of the architecture enforce an artificial cap on Aff0 values
+- * (e.g. GICv3's ICC_SGI1R_EL1 limits it to 15), leading to an
+- * artificial cycling of Aff1, Aff2 and Aff3 values. IOW, these end up
+- * having absolutely no relationship to the actual underlying system
+- * topology, and cannot be reasonably used as core / package ID.
+- *
+- * If the MT bit is set, Aff0 *could* be used to define a thread ID, but
+- * we still wouldn't be able to obtain a sane core ID. This means we
+- * need to entirely ignore MPIDR for any topology deduction.
+- */
+- cpuid_topo->thread_id = -1;
+- cpuid_topo->core_id = cpuid;
+- cpuid_topo->package_id = cpu_to_node(cpuid);
+-
+- pr_debug("CPU%u: cluster %d core %d thread %d mpidr %#016llx\n",
+- cpuid, cpuid_topo->package_id, cpuid_topo->core_id,
+- cpuid_topo->thread_id, mpidr);
+-
+-topology_populated:
+- update_siblings_masks(cpuid);
+-}
+-
+ #ifdef CONFIG_ACPI
+ static bool __init acpi_cpu_is_threaded(int cpu)
+ {
+--- a/drivers/base/arch_topology.c
++++ b/drivers/base/arch_topology.c
+@@ -538,4 +538,23 @@ void __init init_cpu_topology(void)
+ else if (of_have_populated_dt() && parse_dt_topology())
+ reset_cpu_topology();
+ }
++
++void store_cpu_topology(unsigned int cpuid)
++{
++ struct cpu_topology *cpuid_topo = &cpu_topology[cpuid];
++
++ if (cpuid_topo->package_id != -1)
++ goto topology_populated;
++
++ cpuid_topo->thread_id = -1;
++ cpuid_topo->core_id = cpuid;
++ cpuid_topo->package_id = cpu_to_node(cpuid);
++
++ pr_debug("CPU%u: package %d core %d thread %d\n",
++ cpuid, cpuid_topo->package_id, cpuid_topo->core_id,
++ cpuid_topo->thread_id);
++
++topology_populated:
++ update_siblings_masks(cpuid);
++}
+ #endif
--- /dev/null
+From foo@baz Thu Oct 27 12:32:13 PM CEST 2022
+From: Nick Desaulniers <ndesaulniers@google.com>
+Date: Mon, 24 Oct 2022 13:34:14 -0700
+Subject: Makefile.debug: re-enable debug info for .S files
+
+From: Nick Desaulniers <ndesaulniers@google.com>
+
+This is _not_ an upstream commit and just for 5.4.y only. It is based
+on commit 32ef9e5054ec0321b9336058c58ec749e9c6b0fe upstream.
+
+Alexey reported that the fraction of unknown filename instances in
+kallsyms grew from ~0.3% to ~10% recently; Bill and Greg tracked it down
+to assembler defined symbols, which regressed as a result of:
+
+commit b8a9092330da ("Kbuild: do not emit debug info for assembly with LLVM_IAS=1")
+
+In that commit, I allude to restoring debug info for assembler defined
+symbols in a follow up patch, but it seems I forgot to do so in
+
+commit a66049e2cf0e ("Kbuild: make DWARF version a choice")
+
+Fixes: b8a9092330da ("Kbuild: do not emit debug info for assembly with LLVM_IAS=1")
+Signed-off-by: Nick Desaulniers <ndesaulniers@google.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ Makefile | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+--- a/Makefile
++++ b/Makefile
+@@ -802,7 +802,9 @@ DEBUG_CFLAGS += -gsplit-dwarf
+ else
+ DEBUG_CFLAGS += -g
+ endif
+-ifneq ($(LLVM_IAS),1)
++ifeq ($(LLVM_IAS),1)
++KBUILD_AFLAGS += -g
++else
+ KBUILD_AFLAGS += -Wa,-gdwarf-2
+ endif
+ endif
--- /dev/null
+From foo@baz Thu Oct 27 12:19:05 PM CEST 2022
+From: Conor Dooley <conor.dooley@microchip.com>
+Date: Wed, 19 Oct 2022 13:52:10 +0100
+Subject: riscv: topology: fix default topology reporting
+To: <stable@vger.kernel.org>
+Cc: <conor.dooley@microchip.com>, <Brice.Goglin@inria.fr>, <atishp@atishpatra.org>, <catalin.marinas@arm.com>, <gregkh@linuxfoundation.org>, <linux-arm-kernel@lists.infradead.org>, <linux-kernel@vger.kernel.org>, <linux-riscv@lists.infradead.org>, <palmer@dabbelt.com>, <sudeep.holla@arm.com>, <will@kernel.org>, Atish Patra <atishp@rivosinc.com>
+Message-ID: <20221019125209.2844943-2-conor.dooley@microchip.com>
+
+From: Conor Dooley <conor.dooley@microchip.com>
+
+commit fbd92809997a391f28075f1c8b5ee314c225557c upstream.
+
+RISC-V has no sane defaults to fall back on where there is no cpu-map
+in the devicetree.
+Without sane defaults, the package, core and thread IDs are all set to
+-1. This causes user-visible inaccuracies for tools like hwloc/lstopo
+which rely on the sysfs cpu topology files to detect a system's
+topology.
+
+On a PolarFire SoC, which should have 4 harts with a thread each,
+lstopo currently reports:
+
+Machine (793MB total)
+ Package L#0
+ NUMANode L#0 (P#0 793MB)
+ Core L#0
+ L1d L#0 (32KB) + L1i L#0 (32KB) + PU L#0 (P#0)
+ L1d L#1 (32KB) + L1i L#1 (32KB) + PU L#1 (P#1)
+ L1d L#2 (32KB) + L1i L#2 (32KB) + PU L#2 (P#2)
+ L1d L#3 (32KB) + L1i L#3 (32KB) + PU L#3 (P#3)
+
+Adding calls to store_cpu_topology() in {boot,smp} hart bringup code
+results in the correct topolgy being reported:
+
+Machine (793MB total)
+ Package L#0
+ NUMANode L#0 (P#0 793MB)
+ L1d L#0 (32KB) + L1i L#0 (32KB) + Core L#0 + PU L#0 (P#0)
+ L1d L#1 (32KB) + L1i L#1 (32KB) + Core L#1 + PU L#1 (P#1)
+ L1d L#2 (32KB) + L1i L#2 (32KB) + Core L#2 + PU L#2 (P#2)
+ L1d L#3 (32KB) + L1i L#3 (32KB) + Core L#3 + PU L#3 (P#3)
+
+CC: stable@vger.kernel.org # 456797da792f: arm64: topology: move store_cpu_topology() to shared code
+Fixes: 03f11f03dbfe ("RISC-V: Parse cpu topology during boot.")
+Reported-by: Brice Goglin <Brice.Goglin@inria.fr>
+Link: https://github.com/open-mpi/hwloc/issues/536
+Reviewed-by: Sudeep Holla <sudeep.holla@arm.com>
+Reviewed-by: Atish Patra <atishp@rivosinc.com>
+Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ arch/riscv/Kconfig | 2 +-
+ arch/riscv/kernel/smpboot.c | 4 +++-
+ 2 files changed, 4 insertions(+), 2 deletions(-)
+
+--- a/arch/riscv/Kconfig
++++ b/arch/riscv/Kconfig
+@@ -51,7 +51,7 @@ config RISCV
+ select PCI_MSI if PCI
+ select RISCV_TIMER
+ select GENERIC_IRQ_MULTI_HANDLER
+- select GENERIC_ARCH_TOPOLOGY if SMP
++ select GENERIC_ARCH_TOPOLOGY
+ select ARCH_HAS_PTE_SPECIAL
+ select ARCH_HAS_MMIOWB
+ select HAVE_EBPF_JIT if 64BIT
+--- a/arch/riscv/kernel/smpboot.c
++++ b/arch/riscv/kernel/smpboot.c
+@@ -46,6 +46,8 @@ void __init smp_prepare_cpus(unsigned in
+ {
+ int cpuid;
+
++ store_cpu_topology(smp_processor_id());
++
+ /* This covers non-smp usecase mandated by "nosmp" option */
+ if (max_cpus == 0)
+ return;
+@@ -142,8 +144,8 @@ asmlinkage __visible void __init smp_cal
+ current->active_mm = mm;
+
+ trap_init();
++ store_cpu_topology(smp_processor_id());
+ notify_cpu_starting(smp_processor_id());
+- update_siblings_masks(smp_processor_id());
+ set_cpu_online(smp_processor_id(), 1);
+ /*
+ * Remote TLB flushes are ignored while the CPU is offline, so emit
net-sched-cake-fix-null-pointer-access-issue-when-ca.patch
net-hns-fix-possible-memory-leak-in-hnae_ae_register.patch
iommu-vt-d-clean-up-si_domain-in-the-init_dmars-erro.patch
+arm64-topology-move-store_cpu_topology-to-shared-code.patch
+riscv-topology-fix-default-topology-reporting.patch
+acpi-video-force-backlight-native-for-more-tongfang-devices.patch
+makefile.debug-re-enable-debug-info-for-.s-files.patch
projects / thirdparty / kernel / stable-queue.git / commitdiff
