configs: raise SPL_SYS_MALLOC_SIZE to 8 MiB on RISC-V

On several RISC-V boards we have seen that 1 MiB is a insufficient value
for CONFIG_SPL_SYS_MALLOC_SIZE.

For instance qemu-riscv32_spl_defconfig fails booting because u-boot.itb
exceeds 1 MiB.

8 MiB is a reasonable value that allows adding FPGA blobs or splash images
to main U-boot.

Reported-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>

diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index be87b3e63fd4b5a7851f18c44fe6e9115a629527..880192043c49e1306b8045f7b11d2e9f679a0937 100644 (file)
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -488,7 +488,7 @@ config SPL_CUSTOM_SYS_MALLOC_ADDR
 config SPL_SYS_MALLOC_SIZE
        hex "Size of the SPL malloc pool"
        depends on SPL_SYS_MALLOC
-       default 0x180000 if BIOSEMU && RISCV
+       default 0x800000 if RISCV
        default 0x100000
 
 config SPL_READ_ONLY

diff --git a/configs/starfive_visionfive2_defconfig b/configs/starfive_visionfive2_defconfig
index e145ced8db807131d3069f2230d9ae42e67c0e40..6982d422a8248de25b191c358988d010e23e3b5f 100644 (file)
--- a/configs/starfive_visionfive2_defconfig
+++ b/configs/starfive_visionfive2_defconfig
@@ -56,7 +56,6 @@ CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80000000
-CONFIG_SPL_SYS_MALLOC_SIZE=0x400000
 CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x2

diff --git a/configs/th1520_lpi4a_defconfig b/configs/th1520_lpi4a_defconfig
index b19dc009fdee1979433190b9a8a87bde2ca1d990..6ced7afe6b1e20931968f340c7a22637bc495ccf 100644 (file)
--- a/configs/th1520_lpi4a_defconfig
+++ b/configs/th1520_lpi4a_defconfig
@@ -107,4 +107,3 @@ CONFIG_SPL_MMC_y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x10000000
-CONFIG_SPL_SYS_MALLOC_SIZE=0x400000

diff --git a/configs/xilinx_mbv32_defconfig b/configs/xilinx_mbv32_defconfig
index 861d147545347642b030dca0eb1661dc60c575d4..c3f33d6454d2c3914bd014551382e441f21d12f3 100644 (file)
--- a/configs/xilinx_mbv32_defconfig
+++ b/configs/xilinx_mbv32_defconfig
@@ -29,7 +29,6 @@ CONFIG_SPL_MAX_SIZE=0x40000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
 CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
-CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
 # CONFIG_CMD_MII is not set
 CONFIG_CMD_TIMER=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y

diff --git a/configs/xilinx_mbv32_smode_defconfig b/configs/xilinx_mbv32_smode_defconfig
index 9398b4c240dd798b38bfc024d24ba1c1ada75796..c588bd563acb27b4bd557bdef843ab14227fe687 100644 (file)
--- a/configs/xilinx_mbv32_smode_defconfig
+++ b/configs/xilinx_mbv32_smode_defconfig
@@ -30,7 +30,6 @@ CONFIG_SPL_MAX_SIZE=0x40000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
 CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
-CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
 CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS=0x2
 # CONFIG_CMD_MII is not set
 CONFIG_CMD_TIMER=y

diff --git a/configs/xilinx_mbv64_defconfig b/configs/xilinx_mbv64_defconfig
index c39925bd86a7b1b478c466b9f5c36fa4c71e7e3f..c2c677d7443d29c929e99e2d53c8696a0eb88869 100644 (file)
--- a/configs/xilinx_mbv64_defconfig
+++ b/configs/xilinx_mbv64_defconfig
@@ -30,7 +30,6 @@ CONFIG_SPL_MAX_SIZE=0x40000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
 CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
-CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
 # CONFIG_CMD_MII is not set
 CONFIG_CMD_TIMER=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y

diff --git a/configs/xilinx_mbv64_smode_defconfig b/configs/xilinx_mbv64_smode_defconfig
index 811f93a2671ce8d37fdacbd39f27cdfd4e4fb240..7a26c85dfb7cfe22b3e073135fb3e4722d4f21ca 100644 (file)
--- a/configs/xilinx_mbv64_smode_defconfig
+++ b/configs/xilinx_mbv64_smode_defconfig
@@ -31,7 +31,6 @@ CONFIG_SPL_MAX_SIZE=0x40000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
 CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
-CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
 CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS=0x2
 # CONFIG_CMD_MII is not set
 CONFIG_CMD_TIMER=y