--- /dev/null
+From ee7360fc27d6045510f8fe459b5649b2af27811a Mon Sep 17 00:00:00 2001
+From: "David (Ming Qiang) Wu" <David.Wu3@amd.com>
+Date: Mon, 12 May 2025 15:14:43 -0400
+Subject: drm/amdgpu: read back register after written for VCN v4.0.5
+
+From: David (Ming Qiang) Wu <David.Wu3@amd.com>
+
+commit ee7360fc27d6045510f8fe459b5649b2af27811a upstream.
+
+On VCN v4.0.5 there is a race condition where the WPTR is not
+updated after starting from idle when doorbell is used. Adding
+register read-back after written at function end is to ensure
+all register writes are done before they can be used.
+
+Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12528
+Signed-off-by: David (Ming Qiang) Wu <David.Wu3@amd.com>
+Reviewed-by: Mario Limonciello <mario.limonciello@amd.com>
+Tested-by: Mario Limonciello <mario.limonciello@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+(cherry picked from commit 07c9db090b86e5211188e1b351303fbc673378cf)
+Cc: stable@vger.kernel.org
+(cherry picked from commit ee7360fc27d6045510f8fe459b5649b2af27811a)
+Hand modified for contextual changes where there is a for loop
+in 6.12 that was dropped later on.
+Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
++++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
+@@ -985,6 +985,10 @@ static int vcn_v4_0_5_start_dpg_mode(str
+ ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT |
+ VCN_RB1_DB_CTRL__EN_MASK);
+
++ /* Keeping one read-back to ensure all register writes are done, otherwise
++ * it may introduce race conditions */
++ RREG32_SOC15(VCN, inst_idx, regVCN_RB1_DB_CTRL);
++
+ return 0;
+ }
+
+@@ -1167,6 +1171,10 @@ static int vcn_v4_0_5_start(struct amdgp
+ tmp |= VCN_RB_ENABLE__RB1_EN_MASK;
+ WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp);
+ fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF);
++
++ /* Keeping one read-back to ensure all register writes are done, otherwise
++ * it may introduce race conditions */
++ RREG32_SOC15(VCN, i, regVCN_RB_ENABLE);
+ }
+
+ return 0;