ARM: dts: qcom: drop underscore in node names

Underscores should not be used in node names (dtc with W=2 warns about
them), so replace them with hyphens.  Use also generic name for
avago,apds9930 node, because generic naming is favored by Devicetree
spec.

Functional impact checked with comparing before/after DTBs with dtx_diff
and fdtdump.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konradybcio@kernel.org>
Link: https://lore.kernel.org/r/20240905-dts-cleanup-v1-1-f4c5f7b2c8c2@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi
index ac7494ed633e1b8bf97927950d5af8727ed3db52..1bc935d900854ea40e7520ac5762f307c73232f2 100644 (file)
--- a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi
@@ -675,7 +675,7 @@
                        tsens_calib: calib@404 {
                                reg = <0x404 0x10>;
                        };
-                       tsens_backup: backup_calib@414 {
+                       tsens_backup: backup-calib@414 {
                                reg = <0x414 0x10>;
                        };
                };

diff --git a/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi
index 014e6c5ee88984ff3b5f0b0446f45838d6ac4a47..40dbbf8655f09ff3c6259c69bdd08b2fe3c39594 100644 (file)
--- a/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi
@@ -17,7 +17,7 @@
                #size-cells = <1>;
                ranges;
 
-               smem_mem: smem_region@fa00000 {
+               smem_mem: smem-region@fa00000 {
                        reg = <0xfa00000 0x200000>;
                        no-map;
                };
@@ -311,7 +311,7 @@
                                bits = <0 6>;
                        };
 
-                       tsens_s10_p1: s10_p1@d8 {
+                       tsens_s10_p1: s10-p1@d8 {
                                reg = <0xd8 0x2>;
                                bits = <6 6>;
                        };
@@ -371,137 +371,137 @@
                                bits = <4 6>;
                        };
 
-                       tsens_s10_p2: s10_p2@e2 {
+                       tsens_s10_p2: s10-p2@e2 {
                                reg = <0xe2 0x2>;
                                bits = <2 6>;
                        };
 
-                       tsens_s5_p2_backup: s5-p2_backup@e3 {
+                       tsens_s5_p2_backup: s5-p2-backup@e3 {
                                reg = <0xe3 0x2>;
                                bits = <0 6>;
                        };
 
-                       tsens_mode_backup: mode_backup@e3 {
+                       tsens_mode_backup: mode-backup@e3 {
                                reg = <0xe3 0x1>;
                                bits = <6 2>;
                        };
 
-                       tsens_s6_p2_backup: s6-p2_backup@e4 {
+                       tsens_s6_p2_backup: s6-p2-backup@e4 {
                                reg = <0xe4 0x1>;
                                bits = <0 6>;
                        };
 
-                       tsens_s7_p2_backup: s7-p2_backup@e4 {
+                       tsens_s7_p2_backup: s7-p2-backup@e4 {
                                reg = <0xe4 0x2>;
                                bits = <6 6>;
                        };
 
-                       tsens_s8_p2_backup: s8-p2_backup@e5 {
+                       tsens_s8_p2_backup: s8-p2-backup@e5 {
                                reg = <0xe5 0x2>;
                                bits = <4 6>;
                        };
 
-                       tsens_s9_p2_backup: s9-p2_backup@e6 {
+                       tsens_s9_p2_backup: s9-p2-backup@e6 {
                                reg = <0xe6 0x2>;
                                bits = <2 6>;
                        };
 
-                       tsens_s10_p2_backup: s10_p2_backup@e7 {
+                       tsens_s10_p2_backup: s10-p2-backup@e7 {
                                reg = <0xe7 0x1>;
                                bits = <0 6>;
                        };
 
-                       tsens_base1_backup: base1_backup@440 {
+                       tsens_base1_backup: base1-backup@440 {
                                reg = <0x440 0x1>;
                                bits = <0 8>;
                        };
 
-                       tsens_s0_p1_backup: s0-p1_backup@441 {
+                       tsens_s0_p1_backup: s0-p1-backup@441 {
                                reg = <0x441 0x1>;
                                bits = <0 6>;
                        };
 
-                       tsens_s1_p1_backup: s1-p1_backup@442 {
+                       tsens_s1_p1_backup: s1-p1-backup@442 {
                                reg = <0x441 0x2>;
                                bits = <6 6>;
                        };
 
-                       tsens_s2_p1_backup: s2-p1_backup@442 {
+                       tsens_s2_p1_backup: s2-p1-backup@442 {
                                reg = <0x442 0x2>;
                                bits = <4 6>;
                        };
 
-                       tsens_s3_p1_backup: s3-p1_backup@443 {
+                       tsens_s3_p1_backup: s3-p1-backup@443 {
                                reg = <0x443 0x1>;
                                bits = <2 6>;
                        };
 
-                       tsens_s4_p1_backup: s4-p1_backup@444 {
+                       tsens_s4_p1_backup: s4-p1-backup@444 {
                                reg = <0x444 0x1>;
                                bits = <0 6>;
                        };
 
-                       tsens_s5_p1_backup: s5-p1_backup@444 {
+                       tsens_s5_p1_backup: s5-p1-backup@444 {
                                reg = <0x444 0x2>;
                                bits = <6 6>;
                        };
 
-                       tsens_s6_p1_backup: s6-p1_backup@445 {
+                       tsens_s6_p1_backup: s6-p1-backup@445 {
                                reg = <0x445 0x2>;
                                bits = <4 6>;
                        };
 
-                       tsens_s7_p1_backup: s7-p1_backup@446 {
+                       tsens_s7_p1_backup: s7-p1-backup@446 {
                                reg = <0x446 0x1>;
                                bits = <2 6>;
                        };
 
-                       tsens_use_backup: use_backup@447 {
+                       tsens_use_backup: use-backup@447 {
                                reg = <0x447 0x1>;
                                bits = <5 3>;
                        };
 
-                       tsens_s8_p1_backup: s8-p1_backup@448 {
+                       tsens_s8_p1_backup: s8-p1-backup@448 {
                                reg = <0x448 0x1>;
                                bits = <0 6>;
                        };
 
-                       tsens_s9_p1_backup: s9-p1_backup@448 {
+                       tsens_s9_p1_backup: s9-p1-backup@448 {
                                reg = <0x448 0x2>;
                                bits = <6 6>;
                        };
 
-                       tsens_s10_p1_backup: s10_p1_backup@449 {
+                       tsens_s10_p1_backup: s10-p1-backup@449 {
                                reg = <0x449 0x2>;
                                bits = <4 6>;
                        };
 
-                       tsens_base2_backup: base2_backup@44a {
+                       tsens_base2_backup: base2-backup@44a {
                                reg = <0x44a 0x2>;
                                bits = <2 8>;
                        };
 
-                       tsens_s0_p2_backup: s0-p2_backup@44b {
+                       tsens_s0_p2_backup: s0-p2-backup@44b {
                                reg = <0x44b 0x3>;
                                bits = <2 6>;
                        };
 
-                       tsens_s1_p2_backup: s1-p2_backup@44c {
+                       tsens_s1_p2_backup: s1-p2-backup@44c {
                                reg = <0x44c 0x1>;
                                bits = <0 6>;
                        };
 
-                       tsens_s2_p2_backup: s2-p2_backup@44c {
+                       tsens_s2_p2_backup: s2-p2-backup@44c {
                                reg = <0x44c 0x2>;
                                bits = <6 6>;
                        };
 
-                       tsens_s3_p2_backup: s3-p2_backup@44d {
+                       tsens_s3_p2_backup: s3-p2-backup@44d {
                                reg = <0x44d 0x2>;
                                bits = <4 6>;
                        };
 
-                       tsens_s4_p2_backup: s4-p2_backup@44e {
+                       tsens_s4_p2_backup: s4-p2-backup@44e {
                                reg = <0x44e 0x1>;
                                bits = <2 6>;
                        };

diff --git a/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi
index 759a59c2bdbcfa23685f7ff42183ff316cb48c3b..0f02f59c282a25698bade3ef3cac3082bd056b3c 100644 (file)
--- a/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi
@@ -383,7 +383,7 @@
                        tsens_calib: calib@400 {
                                reg = <0x400 0xb>;
                        };
-                       tsens_calib_backup: calib_backup@410 {
+                       tsens_calib_backup: calib-backup@410 {
                                reg = <0x410 0xb>;
                        };
                };

diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974-lge-nexus5-hammerhead.dts b/arch/arm/boot/dts/qcom/qcom-msm8974-lge-nexus5-hammerhead.dts
index fdb6e22986cfc7d7fa88b46c6ca55298ba0544ca..261044fdfee866449e9d9d62cef5aea10d88e874 100644 (file)
--- a/arch/arm/boot/dts/qcom/qcom-msm8974-lge-nexus5-hammerhead.dts
+++ b/arch/arm/boot/dts/qcom/qcom-msm8974-lge-nexus5-hammerhead.dts
@@ -167,7 +167,7 @@
        status = "okay";
        clock-frequency = <100000>;
 
-       avago_apds993@39 {
+       sensor@39 {
                compatible = "avago,apds9930";
                reg = <0x39>;
                interrupts-extended = <&tlmm 61 IRQ_TYPE_EDGE_FALLING>;

diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi
index 1bd87170252df7771bd8ebdcbf0d57cc99af04fc..742d2104b4fe5db54fcbf8c55c6fb2e0fb12a410 100644 (file)
--- a/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi
@@ -1299,7 +1299,7 @@
                                bits = <0 6>;
                        };
 
-                       tsens_s10_p1: s10_p1@d8 {
+                       tsens_s10_p1: s10-p1@d8 {
                                reg = <0xd8 0x2>;
                                bits = <6 6>;
                        };
@@ -1359,137 +1359,137 @@
                                bits = <4 6>;
                        };
 
-                       tsens_s10_p2: s10_p2@e2 {
+                       tsens_s10_p2: s10-p2@e2 {
                                reg = <0xe2 0x2>;
                                bits = <2 6>;
                        };
 
-                       tsens_s5_p2_backup: s5-p2_backup@e3 {
+                       tsens_s5_p2_backup: s5-p2-backup@e3 {
                                reg = <0xe3 0x2>;
                                bits = <0 6>;
                        };
 
-                       tsens_mode_backup: mode_backup@e3 {
+                       tsens_mode_backup: mode-backup@e3 {
                                reg = <0xe3 0x1>;
                                bits = <6 2>;
                        };
 
-                       tsens_s6_p2_backup: s6-p2_backup@e4 {
+                       tsens_s6_p2_backup: s6-p2-backup@e4 {
                                reg = <0xe4 0x1>;
                                bits = <0 6>;
                        };
 
-                       tsens_s7_p2_backup: s7-p2_backup@e4 {
+                       tsens_s7_p2_backup: s7-p2-backup@e4 {
                                reg = <0xe4 0x2>;
                                bits = <6 6>;
                        };
 
-                       tsens_s8_p2_backup: s8-p2_backup@e5 {
+                       tsens_s8_p2_backup: s8-p2-backup@e5 {
                                reg = <0xe5 0x2>;
                                bits = <4 6>;
                        };
 
-                       tsens_s9_p2_backup: s9-p2_backup@e6 {
+                       tsens_s9_p2_backup: s9-p2-backup@e6 {
                                reg = <0xe6 0x2>;
                                bits = <2 6>;
                        };
 
-                       tsens_s10_p2_backup: s10_p2_backup@e7 {
+                       tsens_s10_p2_backup: s10-p2-backup@e7 {
                                reg = <0xe7 0x1>;
                                bits = <0 6>;
                        };
 
-                       tsens_base1_backup: base1_backup@440 {
+                       tsens_base1_backup: base1-backup@440 {
                                reg = <0x440 0x1>;
                                bits = <0 8>;
                        };
 
-                       tsens_s0_p1_backup: s0-p1_backup@441 {
+                       tsens_s0_p1_backup: s0-p1-backup@441 {
                                reg = <0x441 0x1>;
                                bits = <0 6>;
                        };
 
-                       tsens_s1_p1_backup: s1-p1_backup@442 {
+                       tsens_s1_p1_backup: s1-p1-backup@442 {
                                reg = <0x441 0x2>;
                                bits = <6 6>;
                        };
 
-                       tsens_s2_p1_backup: s2-p1_backup@442 {
+                       tsens_s2_p1_backup: s2-p1-backup@442 {
                                reg = <0x442 0x2>;
                                bits = <4 6>;
                        };
 
-                       tsens_s3_p1_backup: s3-p1_backup@443 {
+                       tsens_s3_p1_backup: s3-p1-backup@443 {
                                reg = <0x443 0x1>;
                                bits = <2 6>;
                        };
 
-                       tsens_s4_p1_backup: s4-p1_backup@444 {
+                       tsens_s4_p1_backup: s4-p1-backup@444 {
                                reg = <0x444 0x1>;
                                bits = <0 6>;
                        };
 
-                       tsens_s5_p1_backup: s5-p1_backup@444 {
+                       tsens_s5_p1_backup: s5-p1-backup@444 {
                                reg = <0x444 0x2>;
                                bits = <6 6>;
                        };
 
-                       tsens_s6_p1_backup: s6-p1_backup@445 {
+                       tsens_s6_p1_backup: s6-p1-backup@445 {
                                reg = <0x445 0x2>;
                                bits = <4 6>;
                        };
 
-                       tsens_s7_p1_backup: s7-p1_backup@446 {
+                       tsens_s7_p1_backup: s7-p1-backup@446 {
                                reg = <0x446 0x1>;
                                bits = <2 6>;
                        };
 
-                       tsens_use_backup: use_backup@447 {
+                       tsens_use_backup: use-backup@447 {
                                reg = <0x447 0x1>;
                                bits = <5 3>;
                        };
 
-                       tsens_s8_p1_backup: s8-p1_backup@448 {
+                       tsens_s8_p1_backup: s8-p1-backup@448 {
                                reg = <0x448 0x1>;
                                bits = <0 6>;
                        };
 
-                       tsens_s9_p1_backup: s9-p1_backup@448 {
+                       tsens_s9_p1_backup: s9-p1-backup@448 {
                                reg = <0x448 0x2>;
                                bits = <6 6>;
                        };
 
-                       tsens_s10_p1_backup: s10_p1_backup@449 {
+                       tsens_s10_p1_backup: s10-p1-backup@449 {
                                reg = <0x449 0x2>;
                                bits = <4 6>;
                        };
 
-                       tsens_base2_backup: base2_backup@44a {
+                       tsens_base2_backup: base2-backup@44a {
                                reg = <0x44a 0x2>;
                                bits = <2 8>;
                        };
 
-                       tsens_s0_p2_backup: s0-p2_backup@44b {
+                       tsens_s0_p2_backup: s0-p2-backup@44b {
                                reg = <0x44b 0x3>;
                                bits = <2 6>;
                        };
 
-                       tsens_s1_p2_backup: s1-p2_backup@44c {
+                       tsens_s1_p2_backup: s1-p2-backup@44c {
                                reg = <0x44c 0x1>;
                                bits = <0 6>;
                        };
 
-                       tsens_s2_p2_backup: s2-p2_backup@44c {
+                       tsens_s2_p2_backup: s2-p2-backup@44c {
                                reg = <0x44c 0x2>;
                                bits = <6 6>;
                        };
 
-                       tsens_s3_p2_backup: s3-p2_backup@44d {
+                       tsens_s3_p2_backup: s3-p2-backup@44d {
                                reg = <0x44d 0x2>;
                                bits = <4 6>;
                        };
 
-                       tsens_s4_p2_backup: s4-p2_backup@44e {
+                       tsens_s4_p2_backup: s4-p2-backup@44e {
                                reg = <0x44e 0x1>;
                                bits = <2 6>;
                        };