5.4-stable patches

added patches:
	edac-altera-handle-ocram-ecc-enable-after-warm-reset.patch
	edac-altera-use-inttest-register-for-ethernet-and-usb-sbe-injection.patch

diff --git a/queue-5.4/edac-altera-handle-ocram-ecc-enable-after-warm-reset.patch b/queue-5.4/edac-altera-handle-ocram-ecc-enable-after-warm-reset.patch
new file mode 100644 (file)
index 0000000..84e36d9
--- /dev/null
+++ b/queue-5.4/edac-altera-handle-ocram-ecc-enable-after-warm-reset.patch
@@ -0,0 +1,55 @@
+From fd3ecda38fe0cb713d167b5477d25f6b350f0514 Mon Sep 17 00:00:00 2001
+From: Niravkumar L Rabara <niravkumarlaxmidas.rabara@altera.com>
+Date: Tue, 11 Nov 2025 16:08:01 +0800
+Subject: EDAC/altera: Handle OCRAM ECC enable after warm reset
+
+From: Niravkumar L Rabara <niravkumarlaxmidas.rabara@altera.com>
+
+commit fd3ecda38fe0cb713d167b5477d25f6b350f0514 upstream.
+
+The OCRAM ECC is always enabled either by the BootROM or by the Secure Device
+Manager (SDM) during a power-on reset on SoCFPGA.
+
+However, during a warm reset, the OCRAM content is retained to preserve data,
+while the control and status registers are reset to their default values. As
+a result, ECC must be explicitly re-enabled after a warm reset.
+
+Fixes: 17e47dc6db4f ("EDAC/altera: Add Stratix10 OCRAM ECC support")
+Signed-off-by: Niravkumar L Rabara <niravkumarlaxmidas.rabara@altera.com>
+Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
+Acked-by: Dinh Nguyen <dinguyen@kernel.org>
+Cc: stable@vger.kernel.org
+Link: https://patch.msgid.link/20251111080801.1279401-1-niravkumarlaxmidas.rabara@altera.com
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/edac/altera_edac.c |   18 +++++++++++++++---
+ 1 file changed, 15 insertions(+), 3 deletions(-)
+
+--- a/drivers/edac/altera_edac.c
++++ b/drivers/edac/altera_edac.c
+@@ -1247,10 +1247,22 @@ altr_check_ocram_deps_init(struct altr_e
+       if (ret)
+               return ret;
+ 
+-      /* Verify OCRAM has been initialized */
++      /*
++       * Verify that OCRAM has been initialized.
++       * During a warm reset, OCRAM contents are retained, but the control
++       * and status registers are reset to their default values. Therefore,
++       * ECC must be explicitly re-enabled in the control register.
++       * Error condition: if INITCOMPLETEA is clear and ECC_EN is already set.
++       */
+       if (!ecc_test_bits(ALTR_A10_ECC_INITCOMPLETEA,
+-                         (base + ALTR_A10_ECC_INITSTAT_OFST)))
+-              return -ENODEV;
++                         (base + ALTR_A10_ECC_INITSTAT_OFST))) {
++              if (!ecc_test_bits(ALTR_A10_ECC_EN,
++                                 (base + ALTR_A10_ECC_CTRL_OFST)))
++                      ecc_set_bits(ALTR_A10_ECC_EN,
++                                   (base + ALTR_A10_ECC_CTRL_OFST));
++              else
++                      return -ENODEV;
++      }
+ 
+       /* Enable IRQ on Single Bit Error */
+       writel(ALTR_A10_ECC_SERRINTEN, (base + ALTR_A10_ECC_ERRINTENS_OFST));

diff --git a/queue-5.4/edac-altera-use-inttest-register-for-ethernet-and-usb-sbe-injection.patch b/queue-5.4/edac-altera-use-inttest-register-for-ethernet-and-usb-sbe-injection.patch
new file mode 100644 (file)
index 0000000..8afd09d
--- /dev/null
+++ b/queue-5.4/edac-altera-use-inttest-register-for-ethernet-and-usb-sbe-injection.patch
@@ -0,0 +1,49 @@
+From 281326be67252ac5794d1383f67526606b1d6b13 Mon Sep 17 00:00:00 2001
+From: Niravkumar L Rabara <niravkumarlaxmidas.rabara@altera.com>
+Date: Tue, 11 Nov 2025 16:13:33 +0800
+Subject: EDAC/altera: Use INTTEST register for Ethernet and USB SBE injection
+
+From: Niravkumar L Rabara <niravkumarlaxmidas.rabara@altera.com>
+
+commit 281326be67252ac5794d1383f67526606b1d6b13 upstream.
+
+The current single-bit error injection mechanism flips bits directly in ECC RAM
+by performing write and read operations. When the ECC RAM is actively used by
+the Ethernet or USB controller, this approach sometimes trigger a false
+double-bit error.
+
+Switch both Ethernet and USB EDAC devices to use the INTTEST register
+(altr_edac_a10_device_inject_fops) for single-bit error injection, similar to
+the existing double-bit error injection method.
+
+Fixes: 064acbd4f4ab ("EDAC, altera: Add Stratix10 peripheral support")
+Signed-off-by: Niravkumar L Rabara <niravkumarlaxmidas.rabara@altera.com>
+Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
+Acked-by: Dinh Nguyen <dinguyen@kernel.org>
+Cc: stable@vger.kernel.org
+Link: https://patch.msgid.link/20251111081333.1279635-1-niravkumarlaxmidas.rabara@altera.com
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/edac/altera_edac.c |    4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/drivers/edac/altera_edac.c
++++ b/drivers/edac/altera_edac.c
+@@ -1432,7 +1432,7 @@ static const struct edac_device_prv_data
+       .ue_set_mask = ALTR_A10_ECC_TDERRA,
+       .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
+       .ecc_irq_handler = altr_edac_a10_ecc_irq,
+-      .inject_fops = &altr_edac_a10_device_inject2_fops,
++      .inject_fops = &altr_edac_a10_device_inject_fops,
+ };
+ 
+ #endif        /* CONFIG_EDAC_ALTERA_ETHERNET */
+@@ -1522,7 +1522,7 @@ static const struct edac_device_prv_data
+       .ue_set_mask = ALTR_A10_ECC_TDERRA,
+       .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
+       .ecc_irq_handler = altr_edac_a10_ecc_irq,
+-      .inject_fops = &altr_edac_a10_device_inject2_fops,
++      .inject_fops = &altr_edac_a10_device_inject_fops,
+ };
+ 
+ #endif        /* CONFIG_EDAC_ALTERA_USB */

diff --git a/queue-5.4/series b/queue-5.4/series
index 3bcf35e15a40cfe551023b6b6d73006fdbd0a521..c1f7d26cffc6c36114e50e19501a768474a7f040 100644 (file)
--- a/queue-5.4/series
+++ b/queue-5.4/series
@@ -153,3 +153,5 @@ gcov-add-support-for-gcc-15.patch
 strparser-fix-signed-unsigned-mismatch-bug.patch
 ipv4-route-prevent-rt_bind_exception-from-rebinding-stale-fnhe.patch
 spi-try-to-get-acpi-gpio-irq-earlier.patch
+edac-altera-handle-ocram-ecc-enable-after-warm-reset.patch
+edac-altera-use-inttest-register-for-ethernet-and-usb-sbe-injection.patch