RISC-V: Enable vect test for RV32

gcc/testsuite/ChangeLog:

	* lib/target-supports.exp: Add RV32.

diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index bd38d72562d9f454f164dda8b6dc5959c4d6e6a2..370df10978dbdcf4ee323fd8522f6b5575202c0d 100644 (file)
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -11569,13 +11569,14 @@ proc check_vect_support_and_set_flags { } {
         }
     } elseif [istarget amdgcn-*-*] {
         set dg-do-what-default run
-    } elseif [istarget riscv64-*-*] {
+    } elseif [istarget riscv*-*-*] {
        if [check_effective_target_riscv_v] {
            lappend DEFAULT_VECTCFLAGS "--param" "riscv-vector-abi"
            set dg-do-what-default run
        } else {
-           lappend DEFAULT_VECTCFLAGS "-march=rv64gcv_zvfh" "-mabi=lp64d"
-           lappend DEFAULT_VECTCFLAGS "--param" "riscv-autovec-preference=scalable"
+           foreach item [add_options_for_riscv_v ""] {
+               lappend DEFAULT_VECTCFLAGS $item
+           }
            lappend DEFAULT_VECTCFLAGS "--param" "riscv-vector-abi"
            set dg-do-what-default compile
        }