drm/amdgpu/vcn2: read back register after written

The addition of register read-back in VCN v2.0 is intended to prevent
potential race conditions.

Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Signed-off-by: David (Ming Qiang) Wu <David.Wu3@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
index b8d835c9e17eda68df9cefd3831ae196d82c19f7..148b651be7ca7cfe8b43936d89f453532831f8de 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
@@ -978,6 +978,12 @@ static int vcn_v2_0_start_dpg_mode(struct amdgpu_vcn_inst *vinst, bool indirect)
        /* Unstall DPG */
        WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS),
                0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
+
+       /* Keeping one read-back to ensure all register writes are done,
+        * otherwise it may introduce race conditions.
+        */
+       RREG32_SOC15(UVD, 0, mmUVD_STATUS);
+
        return 0;
 }
 
@@ -1152,6 +1158,11 @@ static int vcn_v2_0_start(struct amdgpu_vcn_inst *vinst)
        WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4);
        fw_shared->multi_queue.encode_lowlatency_queue_mode &= ~FW_QUEUE_RING_RESET;
 
+       /* Keeping one read-back to ensure all register writes are done,
+        * otherwise it may introduce race conditions.
+        */
+       RREG32_SOC15(UVD, 0, mmUVD_STATUS);
+
        return 0;
 }
 
@@ -1183,6 +1194,11 @@ static int vcn_v2_0_stop_dpg_mode(struct amdgpu_vcn_inst *vinst)
        WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 0,
                        ~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
 
+       /* Keeping one read-back to ensure all register writes are done,
+        * otherwise it may introduce race conditions.
+        */
+       RREG32_SOC15(UVD, 0, mmUVD_STATUS);
+
        return 0;
 }
 
@@ -1248,6 +1264,11 @@ static int vcn_v2_0_stop(struct amdgpu_vcn_inst *vinst)
        vcn_v2_0_enable_clock_gating(vinst);
        vcn_v2_0_enable_static_power_gating(vinst);
 
+       /* Keeping one read-back to ensure all register writes are done,
+        * otherwise it may introduce race conditions.
+        */
+       RREG32_SOC15(VCN, 0, mmUVD_STATUS);
+
 power_off:
        if (adev->pm.dpm_enabled)
                amdgpu_dpm_enable_vcn(adev, false, 0);