arm64: dts: qcom: x1e80100: add soundwire controller resets

Soundwire controllers (WSA, WSA2, RX, TX) require reset lines to enable
switching clock control from hardware to software.

Add them along with the reset control providers.

Without this reset we might hit fifo under/over run when we try to write to
soundwire device registers.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240624-x1e-swr-reset-v2-3-8bc677fcfa64@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
index 326283822aee3defa727654fec75b64bdae6006b..ff1fe2372a06d548b77c474109017d1eaf344bcc 100644 (file)
--- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
+++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
@@ -4,6 +4,7 @@
  */
 
 #include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h>
 #include <dt-bindings/clock/qcom,x1e80100-dispcc.h>
 #include <dt-bindings/clock/qcom,x1e80100-gcc.h>
 #include <dt-bindings/clock/qcom,x1e80100-gpucc.h>
@@ -3504,6 +3505,8 @@
 
                        pinctrl-0 = <&wsa2_swr_active>;
                        pinctrl-names = "default";
+                       resets = <&lpass_audiocc LPASS_AUDIO_SWR_WSA2_CGCR>;
+                       reset-names = "swr_audio_cgcr";
 
                        qcom,din-ports = <4>;
                        qcom,dout-ports = <9>;
@@ -3552,6 +3555,8 @@
                        pinctrl-0 = <&rx_swr_active>;
                        pinctrl-names = "default";
 
+                       resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>;
+                       reset-names = "swr_audio_cgcr";
                        qcom,din-ports = <1>;
                        qcom,dout-ports = <11>;
 
@@ -3616,6 +3621,8 @@
 
                        pinctrl-0 = <&wsa_swr_active>;
                        pinctrl-names = "default";
+                       resets = <&lpass_audiocc LPASS_AUDIO_SWR_WSA_CGCR>;
+                       reset-names = "swr_audio_cgcr";
 
                        qcom,din-ports = <4>;
                        qcom,dout-ports = <9>;
@@ -3636,6 +3643,13 @@
                        status = "disabled";
                };
 
+               lpass_audiocc: clock-controller@6b6c000 {
+                       compatible = "qcom,x1e80100-lpassaudiocc", "qcom,sc8280xp-lpassaudiocc";
+                       reg = <0 0x06b6c000 0 0x1000>;
+                       #clock-cells = <1>;
+                       #reset-cells = <1>;
+               };
+
                swr2: soundwire@6d30000 {
                        compatible = "qcom,soundwire-v2.0.0";
                        reg = <0 0x06d30000 0 0x10000>;
@@ -3645,6 +3659,8 @@
                                     <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>;
                        interrupt-names = "core", "wakeup";
                        label = "TX";
+                       resets = <&lpasscc LPASS_AUDIO_SWR_TX_CGCR>;
+                       reset-names = "swr_audio_cgcr";
 
                        pinctrl-0 = <&tx_swr_active>;
                        pinctrl-names = "default";
@@ -3801,6 +3817,13 @@
                        };
                };
 
+               lpasscc: clock-controller@6ea0000 {
+                       compatible = "qcom,x1e80100-lpasscc", "qcom,sc8280xp-lpasscc";
+                       reg = <0 0x06ea0000 0 0x12000>;
+                       #clock-cells = <1>;
+                       #reset-cells = <1>;
+               };
+
                lpass_ag_noc: interconnect@7e40000 {
                        compatible = "qcom,x1e80100-lpass-ag-noc";
                        reg = <0 0x07e40000 0 0xe080>;