drm/amd/display: Add DCN36 DML2 support

Enable DML2 for DCN36.

Acked-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Martin Leung <martin.leung@amd.com>
Signed-off-by: Taimur Hassan <Syed.Hassan@amd.com>
Signed-off-by: Wayne Lin <Wayne.Lin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dml2/display_mode_core_structs.h b/drivers/gpu/drm/amd/display/dc/dml2/display_mode_core_structs.h
index dd3f43181a6ef44bfcee3b2da90ade052b4fd601..0670e4dc4fd91029aff4806563ac1d167e11d478 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml2/display_mode_core_structs.h
+++ b/drivers/gpu/drm/amd/display/dc/dml2/display_mode_core_structs.h
@@ -38,6 +38,7 @@ enum dml_project_id {
        dml_project_dcn35 = 3,
        dml_project_dcn351 = 4,
        dml_project_dcn401 = 5,
+       dml_project_dcn36 = 6,
 };
 enum dml_prefetch_modes {
        dml_prefetch_support_uclk_fclk_and_stutter_if_possible = 0,

diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_policy.c b/drivers/gpu/drm/amd/display/dc/dml2/dml2_policy.c
index c4c52173ef2240d181fef8309891cc921535fc4e..ef693f608d599b42d145d6a239210e1beca92bb9 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml2_policy.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml2_policy.c
@@ -301,6 +301,7 @@ void build_unoptimized_policy_settings(enum dml_project_id project, struct dml_m
        policy->AssumeModeSupportAtMaxPwrStateEvenDRAMClockChangeNotSupported = true; // TOREVIEW: What does this mean?
        policy->AssumeModeSupportAtMaxPwrStateEvenFClockChangeNotSupported = true; // TOREVIEW: What does this mean?
        if (project == dml_project_dcn35 ||
+               project == dml_project_dcn36 ||
                project == dml_project_dcn351) {
                policy->DCCProgrammingAssumesScanDirectionUnknownFinal = false;
                policy->EnhancedPrefetchScheduleAccelerationFinal = 0;

diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c b/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c
index b8a34abaf519a5f93665971820b5583b713c50be..f829d5ac7c8e89bce5851b576cd40de90288f31e 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c
@@ -107,6 +107,7 @@ void dml2_init_ip_params(struct dml2_context *dml2, const struct dc *in_dc, stru
 
        case dml_project_dcn35:
        case dml_project_dcn351:
+       case dml_project_dcn36:
                out->rob_buffer_size_kbytes = 64;
                out->config_return_buffer_size_in_kbytes = 1792;
                out->compressed_buffer_segment_size_in_kbytes = 64;
@@ -292,6 +293,7 @@ void dml2_init_socbb_params(struct dml2_context *dml2, const struct dc *in_dc, s
 
        case dml_project_dcn35:
        case dml_project_dcn351:
+       case dml_project_dcn36:
                out->num_chans = 4;
                out->round_trip_ping_latency_dcfclk_cycles = 106;
                out->smn_latency_us = 2;
@@ -506,6 +508,7 @@ void dml2_init_soc_states(struct dml2_context *dml2, const struct dc *in_dc,
                p->dcfclk_stas_mhz[3] = 1324;
                p->dcfclk_stas_mhz[4] = p->in_states->state_array[1].dcfclk_mhz;
        } else if (dml2->v20.dml_core_ctx.project != dml_project_dcn35 &&
+                       dml2->v20.dml_core_ctx.project != dml_project_dcn36 &&
                        dml2->v20.dml_core_ctx.project != dml_project_dcn351) {
                p->dcfclk_stas_mhz[0] = 300;
                p->dcfclk_stas_mhz[1] = 615;

diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c b/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c
index 556a780466ce36d6befab52cd4bdc4e9e1234981..45584e2f5dfe8c6cdf3d4e623cf0637b9a74431b 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c
@@ -72,6 +72,7 @@ static void map_hw_resources(struct dml2_context *dml2,
                in_out_display_cfg->hw.NumberOfDSCSlices[i] = mode_support_info->NumberOfDSCSlices[i];
                in_out_display_cfg->hw.DLGRefClkFreqMHz = 24;
                if (dml2->v20.dml_core_ctx.project != dml_project_dcn35 &&
+                       dml2->v20.dml_core_ctx.project != dml_project_dcn36 &&
                        dml2->v20.dml_core_ctx.project != dml_project_dcn351) {
                        /*dGPU default as 50Mhz*/
                        in_out_display_cfg->hw.DLGRefClkFreqMHz = 50;
@@ -762,6 +763,9 @@ static void dml2_init(const struct dc *in_dc, const struct dml2_configuration_op
        case DCN_VERSION_3_51:
                (*dml2)->v20.dml_core_ctx.project = dml_project_dcn351;
                break;
+       case DCN_VERSION_3_6:
+               (*dml2)->v20.dml_core_ctx.project = dml_project_dcn36;
+               break;
        case DCN_VERSION_3_2:
                (*dml2)->v20.dml_core_ctx.project = dml_project_dcn32;
                break;