5.15-stable patches

added patches:
	x86-acpi-cstate-optimize-c3-entry-on-amd-cpus.patch

diff --git a/queue-5.15/series b/queue-5.15/series
index 5ec8857decaf7edda96ae73841c88d77421f9399..24aaecc64554950ac7fc86ffab6bfbb006781c3e 100644 (file)
--- a/queue-5.15/series
+++ b/queue-5.15/series
@@ -120,3 +120,4 @@ firmware-coreboot-check-size-of-table-entry-and-use-.patch
 drm-i915-allow-switching-away-via-vga-switcheroo-if-.patch
 revert-selftests-bpf-check-null-propagation-only-nei.patch
 drm-i915-remove-unused-variable.patch
+x86-acpi-cstate-optimize-c3-entry-on-amd-cpus.patch

diff --git a/queue-5.15/x86-acpi-cstate-optimize-c3-entry-on-amd-cpus.patch b/queue-5.15/x86-acpi-cstate-optimize-c3-entry-on-amd-cpus.patch
new file mode 100644 (file)
index 0000000..2ca266e
--- /dev/null
+++ b/queue-5.15/x86-acpi-cstate-optimize-c3-entry-on-amd-cpus.patch
@@ -0,0 +1,47 @@
+From a8fb40966f19ff81520d9ccf8f7e2b95201368b8 Mon Sep 17 00:00:00 2001
+From: Deepak Sharma <deepak.sharma@amd.com>
+Date: Thu, 23 Sep 2021 23:12:05 -0700
+Subject: x86: ACPI: cstate: Optimize C3 entry on AMD CPUs
+
+From: Deepak Sharma <deepak.sharma@amd.com>
+
+commit a8fb40966f19ff81520d9ccf8f7e2b95201368b8 upstream.
+
+All Zen or newer CPU which support C3 shares cache. Its not necessary to
+flush the caches in software before entering C3. This will cause drop in
+performance for the cores which share some caches. ARB_DIS is not used
+with current AMD C state implementation. So set related flags correctly.
+
+Signed-off-by: Deepak Sharma <deepak.sharma@amd.com>
+Acked-by: Thomas Gleixner <tglx@linutronix.de>
+Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
+Signed-off-by: Guilherme G. Piccoli <gpiccoli@igalia.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ arch/x86/kernel/acpi/cstate.c |   15 +++++++++++++++
+ 1 file changed, 15 insertions(+)
+
+--- a/arch/x86/kernel/acpi/cstate.c
++++ b/arch/x86/kernel/acpi/cstate.c
+@@ -79,6 +79,21 @@ void acpi_processor_power_init_bm_check(
+                */
+               flags->bm_control = 0;
+       }
++      if (c->x86_vendor == X86_VENDOR_AMD && c->x86 >= 0x17) {
++              /*
++               * For all AMD Zen or newer CPUs that support C3, caches
++               * should not be flushed by software while entering C3
++               * type state. Set bm->check to 1 so that kernel doesn't
++               * need to execute cache flush operation.
++               */
++              flags->bm_check = 1;
++              /*
++               * In current AMD C state implementation ARB_DIS is no longer
++               * used. So set bm_control to zero to indicate ARB_DIS is not
++               * required while entering C3 type state.
++               */
++              flags->bm_control = 0;
++      }
+ }
+ EXPORT_SYMBOL(acpi_processor_power_init_bm_check);
+