--- /dev/null
+From e70bfd294429de2d55d3530b8a5eac37fd1cb62d Mon Sep 17 00:00:00 2001
+From: Christian Hewitt <christianshewitt@gmail.com>
+Date: Tue, 6 Nov 2018 00:08:20 +0100
+Subject: clk: meson-gxbb: set fclk_div3 as CLK_IS_CRITICAL
+
+[ Upstream commit e2576c8bdfd462c34b8a46c0084e7c30b0851bf4 ]
+
+On the Khadas VIM2 (GXM) and LePotato (GXL) board there are problems
+with reboot; e.g. a ~60 second delay between issuing reboot and the
+board power cycling (and in some OS configurations reboot will fail
+and require manual power cycling).
+
+Similar to 'commit c987ac6f1f088663b6dad39281071aeb31d450a8 ("clk:
+meson-gxbb: set fclk_div2 as CLK_IS_CRITICAL")' the SCPI Cortex-M4
+Co-Processor seems to depend on FCLK_DIV3 being operational.
+
+Until commit 05f814402d6174369b3b29832cbb5eb5ed287059 ("clk:
+meson: add fdiv clock gates"), this clock was modeled and left on by
+the bootloader.
+
+We don't have precise documentation about the SCPI Co-Processor and
+its clock requirement so we are learning things the hard way.
+
+Marking this clock as critical solves the problem but it should not
+be viewed as final solution. Ideally, the SCPI driver should claim
+these clocks. We also depends on some clock hand-off mechanism
+making its way to CCF, to make sure the clock stays on between its
+registration and the SCPI driver probe.
+
+Fixes: 05f814402d61 ("clk: meson: add fdiv clock gates")
+Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
+Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/clk/meson/gxbb.c | 12 ++++++++++++
+ 1 file changed, 12 insertions(+)
+
+diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
+index 177fffb9ebef..902c63209785 100644
+--- a/drivers/clk/meson/gxbb.c
++++ b/drivers/clk/meson/gxbb.c
+@@ -523,6 +523,18 @@ static struct clk_regmap gxbb_fclk_div3 = {
+ .ops = &clk_regmap_gate_ops,
+ .parent_names = (const char *[]){ "fclk_div3_div" },
+ .num_parents = 1,
++ /*
++ * FIXME:
++ * This clock, as fdiv2, is used by the SCPI FW and is required
++ * by the platform to operate correctly.
++ * Until the following condition are met, we need this clock to
++ * be marked as critical:
++ * a) The SCPI generic driver claims and enable all the clocks
++ * it needs
++ * b) CCF has a clock hand-off mechanism to make the sure the
++ * clock stays on until the proper driver comes along
++ */
++ .flags = CLK_IS_CRITICAL,
+ },
+ };
+
+--
+2.17.1
+
scsi-qla2xxx-fix-nvme-session-hang-on-unload.patch
arm64-dts-stratix10-support-ethernet-jumbo-frame.patch
arm64-dts-stratix10-fix-multicast-filtering.patch
+clk-meson-gxbb-set-fclk_div3-as-clk_is_critical.patch
--- /dev/null
+From 017d2e7d8e6799b4189fa9decb58df196239de31 Mon Sep 17 00:00:00 2001
+From: Christian Hewitt <christianshewitt@gmail.com>
+Date: Tue, 6 Nov 2018 00:08:20 +0100
+Subject: clk: meson-gxbb: set fclk_div3 as CLK_IS_CRITICAL
+
+[ Upstream commit e2576c8bdfd462c34b8a46c0084e7c30b0851bf4 ]
+
+On the Khadas VIM2 (GXM) and LePotato (GXL) board there are problems
+with reboot; e.g. a ~60 second delay between issuing reboot and the
+board power cycling (and in some OS configurations reboot will fail
+and require manual power cycling).
+
+Similar to 'commit c987ac6f1f088663b6dad39281071aeb31d450a8 ("clk:
+meson-gxbb: set fclk_div2 as CLK_IS_CRITICAL")' the SCPI Cortex-M4
+Co-Processor seems to depend on FCLK_DIV3 being operational.
+
+Until commit 05f814402d6174369b3b29832cbb5eb5ed287059 ("clk:
+meson: add fdiv clock gates"), this clock was modeled and left on by
+the bootloader.
+
+We don't have precise documentation about the SCPI Co-Processor and
+its clock requirement so we are learning things the hard way.
+
+Marking this clock as critical solves the problem but it should not
+be viewed as final solution. Ideally, the SCPI driver should claim
+these clocks. We also depends on some clock hand-off mechanism
+making its way to CCF, to make sure the clock stays on between its
+registration and the SCPI driver probe.
+
+Fixes: 05f814402d61 ("clk: meson: add fdiv clock gates")
+Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
+Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/clk/meson/gxbb.c | 12 ++++++++++++
+ 1 file changed, 12 insertions(+)
+
+diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
+index 86d3ae58e84c..6435d86118f1 100644
+--- a/drivers/clk/meson/gxbb.c
++++ b/drivers/clk/meson/gxbb.c
+@@ -522,6 +522,18 @@ static struct clk_regmap gxbb_fclk_div3 = {
+ .ops = &clk_regmap_gate_ops,
+ .parent_names = (const char *[]){ "fclk_div3_div" },
+ .num_parents = 1,
++ /*
++ * FIXME:
++ * This clock, as fdiv2, is used by the SCPI FW and is required
++ * by the platform to operate correctly.
++ * Until the following condition are met, we need this clock to
++ * be marked as critical:
++ * a) The SCPI generic driver claims and enable all the clocks
++ * it needs
++ * b) CCF has a clock hand-off mechanism to make the sure the
++ * clock stays on until the proper driver comes along
++ */
++ .flags = CLK_IS_CRITICAL,
+ },
+ };
+
+--
+2.17.1
+
drm-msm-fix-of-child-node-lookup.patch
arm64-dts-stratix10-support-ethernet-jumbo-frame.patch
arm64-dts-stratix10-fix-multicast-filtering.patch
+clk-meson-gxbb-set-fclk_div3-as-clk_is_critical.patch