]> git.ipfire.org Git - thirdparty/binutils-gdb.git/commitdiff
aarch64: Enable mandatory feature bits for v9.4-A.
authorSrinath Parvathaneni <srinath.parvathaneni@arm.com>
Tue, 25 Jun 2024 10:25:26 +0000 (11:25 +0100)
committerSrinath Parvathaneni <srinath.parvathaneni@arm.com>
Tue, 25 Jun 2024 12:38:01 +0000 (13:38 +0100)
This patch fixes the mandatory feature bits in v9.4-a architectures,
by enabling FEAT_SVE2p1 for Armv9.4-A architecture by default.

gas/testsuite/gas/aarch64/sve2p1-1-bad.d
gas/testsuite/gas/aarch64/sve2p1-1.d
gas/testsuite/gas/aarch64/sve2p1-2-bad.d [new file with mode: 0644]
gas/testsuite/gas/aarch64/sve2p1-2-bad.l [new file with mode: 0644]
gas/testsuite/gas/aarch64/sve2p1-nosve2.s [new file with mode: 0644]
include/opcode/aarch64.h

index a2ca49ef487563a55ae8c26ca4318e68da850e64..c28cdc76c4c3c002528b9de3636be8bf1c991160 100644 (file)
@@ -1,4 +1,4 @@
 #name: Illegal test of SVE2.1 min max instructions.
-#as: -march=armv9.4-a
+#as: -march=armv9.3-a
 #source: sve2p1-1.s
 #error_output: sve2p1-1-bad.l
index b93920cd02b78a01a9601f8322269c5735350f67..f562985b5691398b8c08393012a78f31d3e30430 100644 (file)
@@ -1,5 +1,5 @@
 #name: Test of SVE2.1 instructions
-#as: -march=armv9.4-a+sve2p1
+#as: -march=armv9.4-a
 #objdump: -dr
 
 [^:]+:     file format .*
diff --git a/gas/testsuite/gas/aarch64/sve2p1-2-bad.d b/gas/testsuite/gas/aarch64/sve2p1-2-bad.d
new file mode 100644 (file)
index 0000000..4d58f4b
--- /dev/null
@@ -0,0 +1,4 @@
+#name: Illegal test of SVE2.1 instructions.
+#as: -march=armv9.4-a+nosve2
+#source: sve2p1-nosve2.s
+#error_output: sve2p1-2-bad.l
diff --git a/gas/testsuite/gas/aarch64/sve2p1-2-bad.l b/gas/testsuite/gas/aarch64/sve2p1-2-bad.l
new file mode 100644 (file)
index 0000000..1e16026
--- /dev/null
@@ -0,0 +1,2 @@
+.*: Assembler messages:
+.*: Error: selected processor does not support `addqv v0.16b,p0,z16.b'
diff --git a/gas/testsuite/gas/aarch64/sve2p1-nosve2.s b/gas/testsuite/gas/aarch64/sve2p1-nosve2.s
new file mode 100644 (file)
index 0000000..7f457ea
--- /dev/null
@@ -0,0 +1 @@
+addqv v0.16b, p0, z16.b
index 19dadaa18ecb466dbc2d26e0970b8f42b227fdd3..3410a76a56174066cfb9ed49349cd8b4cbbf37a0 100644 (file)
@@ -359,7 +359,8 @@ enum aarch64_feature_bit {
 #define AARCH64_ARCH_V9_1A_FEATURES(X) AARCH64_ARCH_V8_6A_FEATURES (X)
 #define AARCH64_ARCH_V9_2A_FEATURES(X) AARCH64_ARCH_V8_7A_FEATURES (X)
 #define AARCH64_ARCH_V9_3A_FEATURES(X) AARCH64_ARCH_V8_8A_FEATURES (X)
-#define AARCH64_ARCH_V9_4A_FEATURES(X) AARCH64_ARCH_V8_9A_FEATURES (X)
+#define AARCH64_ARCH_V9_4A_FEATURES(X) (AARCH64_ARCH_V8_9A_FEATURES (X) \
+                                        | AARCH64_FEATBIT (X, SVE2p1))
 
 /* Architectures are the sum of the base and extensions.  */
 #define AARCH64_ARCH_V8A(X)    (AARCH64_FEATBIT (X, V8) \