--- /dev/null
+From 85868313177700d20644263a782351262d2aff84 Mon Sep 17 00:00:00 2001
+From: Mark Rutland <mark.rutland@arm.com>
+Date: Fri, 15 Aug 2014 12:11:49 +0100
+Subject: ARM: 8128/1: abort: don't clear the exclusive monitors
+
+From: Mark Rutland <mark.rutland@arm.com>
+
+commit 85868313177700d20644263a782351262d2aff84 upstream.
+
+The ARMv6 and ARMv7 early abort handlers clear the exclusive monitors
+upon entry to the kernel, but this is redundant:
+
+ - We clear the monitors on every exception return since commit
+ 200b812d0084 ("Clear the exclusive monitor when returning from an
+ exception"), so this is not necessary to ensure the monitors are
+ cleared before returning from a fault handler.
+
+ - Any dummy STREX will target a temporary scratch area in memory, and
+ may succeed or fail without corrupting useful data. Its status value
+ will not be used.
+
+ - Any other STREX in the kernel must be preceded by an LDREX, which
+ will initialise the monitors consistently and will not depend on the
+ earlier state of the monitors.
+
+Therefore we have no reason to care about the initial state of the
+exclusive monitors when a data abort is taken, and clearing the monitors
+prior to exception return (as we already do) is sufficient.
+
+This patch removes the redundant clearing of the exclusive monitors from
+the early abort handlers.
+
+Signed-off-by: Mark Rutland <mark.rutland@arm.com>
+Acked-by: Will Deacon <will.deacon@arm.com>
+Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/arm/mm/abort-ev6.S | 6 ------
+ arch/arm/mm/abort-ev7.S | 6 ------
+ 2 files changed, 12 deletions(-)
+
+--- a/arch/arm/mm/abort-ev6.S
++++ b/arch/arm/mm/abort-ev6.S
+@@ -17,12 +17,6 @@
+ */
+ .align 5
+ ENTRY(v6_early_abort)
+-#ifdef CONFIG_CPU_V6
+- sub r1, sp, #4 @ Get unused stack location
+- strex r0, r1, [r1] @ Clear the exclusive monitor
+-#elif defined(CONFIG_CPU_32v6K)
+- clrex
+-#endif
+ mrc p15, 0, r1, c5, c0, 0 @ get FSR
+ mrc p15, 0, r0, c6, c0, 0 @ get FAR
+ /*
+--- a/arch/arm/mm/abort-ev7.S
++++ b/arch/arm/mm/abort-ev7.S
+@@ -13,12 +13,6 @@
+ */
+ .align 5
+ ENTRY(v7_early_abort)
+- /*
+- * The effect of data aborts on on the exclusive access monitor are
+- * UNPREDICTABLE. Do a CLREX to clear the state
+- */
+- clrex
+-
+ mrc p15, 0, r1, c5, c0, 0 @ get FSR
+ mrc p15, 0, r0, c6, c0, 0 @ get FAR
+
--- /dev/null
+From 2c32c65e3726c773760038910be30cce1b4d4149 Mon Sep 17 00:00:00 2001
+From: Mark Rutland <mark.rutland@arm.com>
+Date: Fri, 15 Aug 2014 12:11:50 +0100
+Subject: ARM: 8129/1: errata: work around Cortex-A15 erratum 830321 using dummy strex
+
+From: Mark Rutland <mark.rutland@arm.com>
+
+commit 2c32c65e3726c773760038910be30cce1b4d4149 upstream.
+
+On revisions of Cortex-A15 prior to r3p3, a CLREX instruction at PL1 may
+falsely trigger a watchpoint exception, leading to potential data aborts
+during exception return and/or livelock.
+
+This patch resolves the issue in the following ways:
+
+ - Replacing our uses of CLREX with a dummy STREX sequence instead (as
+ we did for v6 CPUs).
+
+ - Removing the clrex code from v7_exit_coherency_flush and derivatives,
+ since this only exists as a minor performance improvement when
+ non-cached exclusives are in use (Linux doesn't use these).
+
+Benchmarking on a variety of ARM cores revealed no measurable
+performance difference with this change applied, so the change is
+performed unconditionally and no new Kconfig entry is added.
+
+Signed-off-by: Mark Rutland <mark.rutland@arm.com>
+Signed-off-by: Will Deacon <will.deacon@arm.com>
+Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/arm/include/asm/cacheflush.h | 1 -
+ arch/arm/kernel/entry-header.S | 29 +++++++++++++++--------------
+ arch/arm/mach-exynos/mcpm-exynos.c | 1 -
+ 3 files changed, 15 insertions(+), 16 deletions(-)
+
+--- a/arch/arm/include/asm/cacheflush.h
++++ b/arch/arm/include/asm/cacheflush.h
+@@ -472,7 +472,6 @@ static inline void __sync_cache_range_r(
+ "mcr p15, 0, r0, c1, c0, 0 @ set SCTLR \n\t" \
+ "isb \n\t" \
+ "bl v7_flush_dcache_"__stringify(level)" \n\t" \
+- "clrex \n\t" \
+ "mrc p15, 0, r0, c1, c0, 1 @ get ACTLR \n\t" \
+ "bic r0, r0, #(1 << 6) @ disable local coherency \n\t" \
+ "mcr p15, 0, r0, c1, c0, 1 @ set ACTLR \n\t" \
+--- a/arch/arm/kernel/entry-header.S
++++ b/arch/arm/kernel/entry-header.S
+@@ -208,26 +208,21 @@
+ #endif
+ .endif
+ msr spsr_cxsf, \rpsr
+-#if defined(CONFIG_CPU_V6)
+- ldr r0, [sp]
+- strex r1, r2, [sp] @ clear the exclusive monitor
+- ldmib sp, {r1 - pc}^ @ load r1 - pc, cpsr
+-#elif defined(CONFIG_CPU_32v6K)
+- clrex @ clear the exclusive monitor
+- ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr
+-#else
+- ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr
++#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_32v6K)
++ @ We must avoid clrex due to Cortex-A15 erratum #830321
++ sub r0, sp, #4 @ uninhabited address
++ strex r1, r2, [r0] @ clear the exclusive monitor
+ #endif
++ ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr
+ .endm
+
+ .macro restore_user_regs, fast = 0, offset = 0
+ ldr r1, [sp, #\offset + S_PSR] @ get calling cpsr
+ ldr lr, [sp, #\offset + S_PC]! @ get pc
+ msr spsr_cxsf, r1 @ save in spsr_svc
+-#if defined(CONFIG_CPU_V6)
++#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_32v6K)
++ @ We must avoid clrex due to Cortex-A15 erratum #830321
+ strex r1, r2, [sp] @ clear the exclusive monitor
+-#elif defined(CONFIG_CPU_32v6K)
+- clrex @ clear the exclusive monitor
+ #endif
+ .if \fast
+ ldmdb sp, {r1 - lr}^ @ get calling r1 - lr
+@@ -267,7 +262,10 @@
+ .endif
+ ldr lr, [sp, #S_SP] @ top of the stack
+ ldrd r0, r1, [sp, #S_LR] @ calling lr and pc
+- clrex @ clear the exclusive monitor
++
++ @ We must avoid clrex due to Cortex-A15 erratum #830321
++ strex r2, r1, [sp, #S_LR] @ clear the exclusive monitor
++
+ stmdb lr!, {r0, r1, \rpsr} @ calling lr and rfe context
+ ldmia sp, {r0 - r12}
+ mov sp, lr
+@@ -288,13 +286,16 @@
+ .endm
+ #else /* ifdef CONFIG_CPU_V7M */
+ .macro restore_user_regs, fast = 0, offset = 0
+- clrex @ clear the exclusive monitor
+ mov r2, sp
+ load_user_sp_lr r2, r3, \offset + S_SP @ calling sp, lr
+ ldr r1, [sp, #\offset + S_PSR] @ get calling cpsr
+ ldr lr, [sp, #\offset + S_PC] @ get pc
+ add sp, sp, #\offset + S_SP
+ msr spsr_cxsf, r1 @ save in spsr_svc
++
++ @ We must avoid clrex due to Cortex-A15 erratum #830321
++ strex r1, r2, [sp] @ clear the exclusive monitor
++
+ .if \fast
+ ldmdb sp, {r1 - r12} @ get calling r1 - r12
+ .else
+--- a/arch/arm/mach-exynos/mcpm-exynos.c
++++ b/arch/arm/mach-exynos/mcpm-exynos.c
+@@ -39,7 +39,6 @@
+ "mcr p15, 0, r0, c1, c0, 0 @ set SCTLR\n\t" \
+ "isb\n\t"\
+ "bl v7_flush_dcache_"__stringify(level)"\n\t" \
+- "clrex\n\t"\
+ "mrc p15, 0, r0, c1, c0, 1 @ get ACTLR\n\t" \
+ "bic r0, r0, #(1 << 6) @ disable local coherency\n\t" \
+ /* Dummy Load of a device register to avoid Erratum 799270 */ \
--- /dev/null
+From a040803a9d6b8c1876d3487a5cb69602ebcbb82c Mon Sep 17 00:00:00 2001
+From: Sudeep Holla <sudeep.holla@arm.com>
+Date: Mon, 1 Sep 2014 17:14:29 +0100
+Subject: ARM: 8133/1: use irq_set_affinity with force=false when migrating irqs
+
+From: Sudeep Holla <sudeep.holla@arm.com>
+
+commit a040803a9d6b8c1876d3487a5cb69602ebcbb82c upstream.
+
+Since commit 1dbfa187dad ("ARM: irq migration: force migration off CPU
+going down") the ARM interrupt migration code on cpu offline calls
+irqchip.irq_set_affinity() with the argument force=true. At the point
+of this change the argument had no effect because it was not used by
+any interrupt chip driver and there was no semantics defined.
+
+This changed with commit 01f8fa4f01d8 ("genirq: Allow forcing cpu
+affinity of interrupts") which made the force argument useful to route
+interrupts to not yet online cpus without checking the target cpu
+against the cpu online mask. The following commit ffde1de64012
+("irqchip: gic: Support forced affinity setting") implemented this for
+the GIC interrupt controller.
+
+As a consequence the ARM cpu offline irq migration fails if CPU0 is
+offlined, because CPU0 is still set in the affinity mask and the
+validataion against cpu online mask is skipped to the force argument
+being true. The following first_cpu(mask) selection always selects
+CPU0 as the target.
+
+Solve the issue by calling irq_set_affinity() with force=false from
+the CPU offline irq migration code so the GIC driver validates the
+affinity mask against CPU online mask and therefore removes CPU0 from
+the possible target candidates.
+
+Tested on TC2 hotpluging CPU0 in and out. Without this patch the system
+locks up as the IRQs are not migrated away from CPU0.
+
+Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
+Acked-by: Thomas Gleixner <tglx@linutronix.de>
+Acked-by: Mark Rutland <mark.rutland@arm.com>
+Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/arm/kernel/irq.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/arm/kernel/irq.c
++++ b/arch/arm/kernel/irq.c
+@@ -175,7 +175,7 @@ static bool migrate_one_irq(struct irq_d
+ c = irq_data_get_irq_chip(d);
+ if (!c->irq_set_affinity)
+ pr_debug("IRQ%u: unable to set affinity\n", d->irq);
+- else if (c->irq_set_affinity(d, affinity, true) == IRQ_SET_MASK_OK && ret)
++ else if (c->irq_set_affinity(d, affinity, false) == IRQ_SET_MASK_OK && ret)
+ cpumask_copy(d->affinity, affinity);
+
+ return ret;
--- /dev/null
+From fbfb872f5f417cea48760c535e0ff027c88b507a Mon Sep 17 00:00:00 2001
+From: Nathan Lynch <nathan_lynch@mentor.com>
+Date: Thu, 11 Sep 2014 02:49:08 +0100
+Subject: ARM: 8148/1: flush TLS and thumbee register state during exec
+
+From: Nathan Lynch <nathan_lynch@mentor.com>
+
+commit fbfb872f5f417cea48760c535e0ff027c88b507a upstream.
+
+The TPIDRURO and TPIDRURW registers need to be flushed during exec;
+otherwise TLS information is potentially leaked. TPIDRURO in
+particular needs careful treatment. Since flush_thread basically
+needs the same code used to set the TLS in arm_syscall, pull that into
+a common set_tls helper in tls.h and use it in both places.
+
+Similarly, TEEHBR needs to be cleared during exec as well. Clearing
+its save slot in thread_info isn't right as there is no guarantee
+that a thread switch will occur before the new program runs. Just
+setting the register directly is sufficient.
+
+Signed-off-by: Nathan Lynch <nathan_lynch@mentor.com>
+Acked-by: Will Deacon <will.deacon@arm.com>
+Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/arm/include/asm/tls.h | 62 +++++++++++++++++++++++++++++++++++++++++++++
+ arch/arm/kernel/process.c | 2 +
+ arch/arm/kernel/thumbee.c | 2 -
+ arch/arm/kernel/traps.c | 17 ------------
+ 4 files changed, 66 insertions(+), 17 deletions(-)
+
+--- a/arch/arm/include/asm/tls.h
++++ b/arch/arm/include/asm/tls.h
+@@ -1,6 +1,9 @@
+ #ifndef __ASMARM_TLS_H
+ #define __ASMARM_TLS_H
+
++#include <linux/compiler.h>
++#include <asm/thread_info.h>
++
+ #ifdef __ASSEMBLY__
+ #include <asm/asm-offsets.h>
+ .macro switch_tls_none, base, tp, tpuser, tmp1, tmp2
+@@ -50,6 +53,47 @@
+ #endif
+
+ #ifndef __ASSEMBLY__
++
++static inline void set_tls(unsigned long val)
++{
++ struct thread_info *thread;
++
++ thread = current_thread_info();
++
++ thread->tp_value[0] = val;
++
++ /*
++ * This code runs with preemption enabled and therefore must
++ * be reentrant with respect to switch_tls.
++ *
++ * We need to ensure ordering between the shadow state and the
++ * hardware state, so that we don't corrupt the hardware state
++ * with a stale shadow state during context switch.
++ *
++ * If we're preempted here, switch_tls will load TPIDRURO from
++ * thread_info upon resuming execution and the following mcr
++ * is merely redundant.
++ */
++ barrier();
++
++ if (!tls_emu) {
++ if (has_tls_reg) {
++ asm("mcr p15, 0, %0, c13, c0, 3"
++ : : "r" (val));
++ } else {
++ /*
++ * User space must never try to access this
++ * directly. Expect your app to break
++ * eventually if you do so. The user helper
++ * at 0xffff0fe0 must be used instead. (see
++ * entry-armv.S for details)
++ */
++ *((unsigned int *)0xffff0ff0) = val;
++ }
++
++ }
++}
++
+ static inline unsigned long get_tpuser(void)
+ {
+ unsigned long reg = 0;
+@@ -59,5 +103,23 @@ static inline unsigned long get_tpuser(v
+
+ return reg;
+ }
++
++static inline void set_tpuser(unsigned long val)
++{
++ /* Since TPIDRURW is fully context-switched (unlike TPIDRURO),
++ * we need not update thread_info.
++ */
++ if (has_tls_reg && !tls_emu) {
++ asm("mcr p15, 0, %0, c13, c0, 2"
++ : : "r" (val));
++ }
++}
++
++static inline void flush_tls(void)
++{
++ set_tls(0);
++ set_tpuser(0);
++}
++
+ #endif
+ #endif /* __ASMARM_TLS_H */
+--- a/arch/arm/kernel/process.c
++++ b/arch/arm/kernel/process.c
+@@ -334,6 +334,8 @@ void flush_thread(void)
+ memset(&tsk->thread.debug, 0, sizeof(struct debug_info));
+ memset(&thread->fpstate, 0, sizeof(union fp_state));
+
++ flush_tls();
++
+ thread_notify(THREAD_NOTIFY_FLUSH, thread);
+ }
+
+--- a/arch/arm/kernel/thumbee.c
++++ b/arch/arm/kernel/thumbee.c
+@@ -45,7 +45,7 @@ static int thumbee_notifier(struct notif
+
+ switch (cmd) {
+ case THREAD_NOTIFY_FLUSH:
+- thread->thumbee_state = 0;
++ teehbr_write(0);
+ break;
+ case THREAD_NOTIFY_SWITCH:
+ current_thread_info()->thumbee_state = teehbr_read();
+--- a/arch/arm/kernel/traps.c
++++ b/arch/arm/kernel/traps.c
+@@ -579,7 +579,6 @@ do_cache_op(unsigned long start, unsigne
+ #define NR(x) ((__ARM_NR_##x) - __ARM_NR_BASE)
+ asmlinkage int arm_syscall(int no, struct pt_regs *regs)
+ {
+- struct thread_info *thread = current_thread_info();
+ siginfo_t info;
+
+ if ((no >> 16) != (__ARM_NR_BASE>> 16))
+@@ -630,21 +629,7 @@ asmlinkage int arm_syscall(int no, struc
+ return regs->ARM_r0;
+
+ case NR(set_tls):
+- thread->tp_value[0] = regs->ARM_r0;
+- if (tls_emu)
+- return 0;
+- if (has_tls_reg) {
+- asm ("mcr p15, 0, %0, c13, c0, 3"
+- : : "r" (regs->ARM_r0));
+- } else {
+- /*
+- * User space must never try to access this directly.
+- * Expect your app to break eventually if you do so.
+- * The user helper at 0xffff0fe0 must be used instead.
+- * (see entry-armv.S for details)
+- */
+- *((unsigned int *)0xffff0ff0) = regs->ARM_r0;
+- }
++ set_tls(regs->ARM_r0);
+ return 0;
+
+ #ifdef CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG
--- /dev/null
+From 505013bc9065391f09a51d51cd3bf0b06dfb570a Mon Sep 17 00:00:00 2001
+From: Stephen Boyd <sboyd@codeaurora.org>
+Date: Thu, 11 Sep 2014 23:25:30 +0100
+Subject: ARM: 8149/1: perf: Don't sleep while atomic when enabling per-cpu interrupts
+
+From: Stephen Boyd <sboyd@codeaurora.org>
+
+commit 505013bc9065391f09a51d51cd3bf0b06dfb570a upstream.
+
+Rob Clark reports a sleeping while atomic bug when using perf.
+
+BUG: sleeping function called from invalid context at ../kernel/locking/mutex.c:583
+in_atomic(): 1, irqs_disabled(): 128, pid: 0, name: swapper/0
+------------[ cut here ]------------
+WARNING: CPU: 2 PID: 4828 at ../kernel/locking/mutex.c:479 mutex_lock_nested+0x3a0/0x3e8()
+DEBUG_LOCKS_WARN_ON(in_interrupt())
+Modules linked in:
+CPU: 2 PID: 4828 Comm: Xorg.bin Tainted: G W 3.17.0-rc3-00234-gd535c45-dirty #819
+[<c0216690>] (unwind_backtrace) from [<c0212174>] (show_stack+0x10/0x14)
+[<c0212174>] (show_stack) from [<c0867cc0>] (dump_stack+0x98/0xb8)
+[<c0867cc0>] (dump_stack) from [<c02492a4>] (warn_slowpath_common+0x70/0x8c)
+[<c02492a4>] (warn_slowpath_common) from [<c02492f0>] (warn_slowpath_fmt+0x30/0x40)
+[<c02492f0>] (warn_slowpath_fmt) from [<c086a3f8>] (mutex_lock_nested+0x3a0/0x3e8)
+[<c086a3f8>] (mutex_lock_nested) from [<c0294d08>] (irq_find_host+0x20/0x9c)
+[<c0294d08>] (irq_find_host) from [<c0769d50>] (of_irq_get+0x28/0x48)
+[<c0769d50>] (of_irq_get) from [<c057d104>] (platform_get_irq+0x1c/0x8c)
+[<c057d104>] (platform_get_irq) from [<c021a06c>] (cpu_pmu_enable_percpu_irq+0x14/0x38)
+[<c021a06c>] (cpu_pmu_enable_percpu_irq) from [<c02b1634>] (flush_smp_call_function_queue+0x88/0x178)
+[<c02b1634>] (flush_smp_call_function_queue) from [<c0214dc0>] (handle_IPI+0x88/0x160)
+[<c0214dc0>] (handle_IPI) from [<c0208930>] (gic_handle_irq+0x64/0x68)
+[<c0208930>] (gic_handle_irq) from [<c0212d04>] (__irq_svc+0x44/0x5c)
+Exception stack(0xe63ddea0 to 0xe63ddee8)
+dea0: 00000001 00000001 00000000 c2f3b200 c16db380 c032d4a0 e63ddf40 60010013
+dec0: 00000000 001fbfd4 00000100 00000000 00000001 e63ddee8 c0284770 c02a2e30
+dee0: 20010013 ffffffff
+[<c0212d04>] (__irq_svc) from [<c02a2e30>] (ktime_get_ts64+0x1c8/0x200)
+[<c02a2e30>] (ktime_get_ts64) from [<c032d4a0>] (poll_select_set_timeout+0x60/0xa8)
+[<c032d4a0>] (poll_select_set_timeout) from [<c032df64>] (SyS_select+0xa8/0x118)
+[<c032df64>] (SyS_select) from [<c020e8e0>] (ret_fast_syscall+0x0/0x48)
+---[ end trace 0bb583b46342da6f ]---
+INFO: lockdep is turned off.
+
+We don't really need to get the platform irq again when we're
+enabling or disabling the per-cpu irq. Furthermore, we don't
+really need to set and clear bits in the active_irqs bitmask
+because that's only used in the non-percpu irq case to figure out
+when the last CPU PMU has been disabled. Just pass the irq
+directly to the enable/disable functions to clean all this up.
+This should be slightly more efficient and also fix the
+scheduling while atomic bug.
+
+Fixes: bbd64559376f "ARM: perf: support percpu irqs for the CPU PMU"
+
+Reported-by: Rob Clark <robdclark@gmail.com>
+Acked-by: Will Deacon <will.deacon@arm.com>
+Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
+Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/arm/kernel/perf_event_cpu.c | 14 ++++----------
+ 1 file changed, 4 insertions(+), 10 deletions(-)
+
+--- a/arch/arm/kernel/perf_event_cpu.c
++++ b/arch/arm/kernel/perf_event_cpu.c
+@@ -76,21 +76,15 @@ static struct pmu_hw_events *cpu_pmu_get
+
+ static void cpu_pmu_enable_percpu_irq(void *data)
+ {
+- struct arm_pmu *cpu_pmu = data;
+- struct platform_device *pmu_device = cpu_pmu->plat_device;
+- int irq = platform_get_irq(pmu_device, 0);
++ int irq = *(int *)data;
+
+ enable_percpu_irq(irq, IRQ_TYPE_NONE);
+- cpumask_set_cpu(smp_processor_id(), &cpu_pmu->active_irqs);
+ }
+
+ static void cpu_pmu_disable_percpu_irq(void *data)
+ {
+- struct arm_pmu *cpu_pmu = data;
+- struct platform_device *pmu_device = cpu_pmu->plat_device;
+- int irq = platform_get_irq(pmu_device, 0);
++ int irq = *(int *)data;
+
+- cpumask_clear_cpu(smp_processor_id(), &cpu_pmu->active_irqs);
+ disable_percpu_irq(irq);
+ }
+
+@@ -103,7 +97,7 @@ static void cpu_pmu_free_irq(struct arm_
+
+ irq = platform_get_irq(pmu_device, 0);
+ if (irq >= 0 && irq_is_percpu(irq)) {
+- on_each_cpu(cpu_pmu_disable_percpu_irq, cpu_pmu, 1);
++ on_each_cpu(cpu_pmu_disable_percpu_irq, &irq, 1);
+ free_percpu_irq(irq, &percpu_pmu);
+ } else {
+ for (i = 0; i < irqs; ++i) {
+@@ -138,7 +132,7 @@ static int cpu_pmu_request_irq(struct ar
+ irq);
+ return err;
+ }
+- on_each_cpu(cpu_pmu_enable_percpu_irq, cpu_pmu, 1);
++ on_each_cpu(cpu_pmu_enable_percpu_irq, &irq, 1);
+ } else {
+ for (i = 0; i < irqs; ++i) {
+ err = 0;
--- /dev/null
+From 5ca918e5e3f9df4634077c06585c42bc6a8d699a Mon Sep 17 00:00:00 2001
+From: Robin Murphy <robin.murphy@arm.com>
+Date: Thu, 25 Sep 2014 11:56:19 +0100
+Subject: ARM: 8165/1: alignment: don't break misaligned NEON load/store
+
+From: Robin Murphy <robin.murphy@arm.com>
+
+commit 5ca918e5e3f9df4634077c06585c42bc6a8d699a upstream.
+
+The alignment fixup incorrectly decodes faulting ARM VLDn/VSTn
+instructions (where the optional alignment hint is given but incorrect)
+as LDR/STR, leading to register corruption. Detect these and correctly
+treat them as unhandled, so that userspace gets the fault it expects.
+
+Reported-by: Simon Hosie <simon.hosie@arm.com>
+Signed-off-by: Robin Murphy <robin.murphy@arm.com>
+Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/arm/mm/alignment.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+--- a/arch/arm/mm/alignment.c
++++ b/arch/arm/mm/alignment.c
+@@ -41,6 +41,7 @@
+ * This code is not portable to processors with late data abort handling.
+ */
+ #define CODING_BITS(i) (i & 0x0e000000)
++#define COND_BITS(i) (i & 0xf0000000)
+
+ #define LDST_I_BIT(i) (i & (1 << 26)) /* Immediate constant */
+ #define LDST_P_BIT(i) (i & (1 << 24)) /* Preindex */
+@@ -819,6 +820,8 @@ do_alignment(unsigned long addr, unsigne
+ break;
+
+ case 0x04000000: /* ldr or str immediate */
++ if (COND_BITS(instr) == 0xf0000000) /* NEON VLDn, VSTn */
++ goto bad;
+ offset.un = OFFSET_BITS(instr);
+ handler = do_alignment_ldrstr;
+ break;
--- /dev/null
+From 9cc6d9e5daaa147a9a3e31557efcb331989e77be Mon Sep 17 00:00:00 2001
+From: Nathan Lynch <nathan_lynch@mentor.com>
+Date: Mon, 29 Sep 2014 19:11:36 +0100
+Subject: ARM: 8178/1: fix set_tls for !CONFIG_KUSER_HELPERS
+
+From: Nathan Lynch <nathan_lynch@mentor.com>
+
+commit 9cc6d9e5daaa147a9a3e31557efcb331989e77be upstream.
+
+Joachim Eastwood reports that commit fbfb872f5f41 "ARM: 8148/1: flush
+TLS and thumbee register state during exec" causes a boot-time crash
+on a Cortex-M4 nommu system:
+
+Freeing unused kernel memory: 68K (281e5000 - 281f6000)
+Unhandled exception: IPSR = 00000005 LR = fffffff1
+CPU: 0 PID: 1 Comm: swapper Not tainted 3.17.0-rc6-00313-gd2205fa30aa7 #191
+task: 29834000 ti: 29832000 task.ti: 29832000
+PC is at flush_thread+0x2e/0x40
+LR is at flush_thread+0x21/0x40
+pc : [<2800954a>] lr : [<2800953d>] psr: 4100000b
+sp : 29833d60 ip : 00000000 fp : 00000001
+r10: 00003cf8 r9 : 29b1f000 r8 : 00000000
+r7 : 29b0bc00 r6 : 29834000 r5 : 29832000 r4 : 29832000
+r3 : ffff0ff0 r2 : 29832000 r1 : 00000000 r0 : 282121f0
+xPSR: 4100000b
+CPU: 0 PID: 1 Comm: swapper Not tainted 3.17.0-rc6-00313-gd2205fa30aa7 #191
+[<2800afa5>] (unwind_backtrace) from [<2800a327>] (show_stack+0xb/0xc)
+[<2800a327>] (show_stack) from [<2800a963>] (__invalid_entry+0x4b/0x4c)
+
+The problem is that set_tls is attempting to clear the TLS location in
+the kernel-user helper page, which isn't set up on V7M.
+
+Fix this by guarding the write to the kuser helper page with
+a CONFIG_KUSER_HELPERS ifdef.
+
+Fixes: fbfb872f5f41 ARM: 8148/1: flush TLS and thumbee register state during exec
+
+Reported-by: Joachim Eastwood <manabian@gmail.com>
+Tested-by: Joachim Eastwood <manabian@gmail.com>
+Signed-off-by: Nathan Lynch <nathan_lynch@mentor.com>
+Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/arm/include/asm/tls.h | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/arch/arm/include/asm/tls.h
++++ b/arch/arm/include/asm/tls.h
+@@ -81,6 +81,7 @@ static inline void set_tls(unsigned long
+ asm("mcr p15, 0, %0, c13, c0, 3"
+ : : "r" (val));
+ } else {
++#ifdef CONFIG_KUSER_HELPERS
+ /*
+ * User space must never try to access this
+ * directly. Expect your app to break
+@@ -89,6 +90,7 @@ static inline void set_tls(unsigned long
+ * entry-armv.S for details)
+ */
+ *((unsigned int *)0xffff0ff0) = val;
++#endif
+ }
+
+ }
--- /dev/null
+From f7f7a29bf0cf25af23f37e5b5bf1368b85705286 Mon Sep 17 00:00:00 2001
+From: Rajendra Nayak <rnayak@ti.com>
+Date: Wed, 27 Aug 2014 19:38:23 -0600
+Subject: ARM: DRA7: hwmod: Add dra74x and dra72x specific ocp interface lists
+
+From: Rajendra Nayak <rnayak@ti.com>
+
+commit f7f7a29bf0cf25af23f37e5b5bf1368b85705286 upstream.
+
+To deal with IPs which are specific to dra74x and dra72x, maintain seperate
+ocp interface lists, while keeping the common list for all common IPs.
+
+Move USB OTG SS4 to dra74x only list since its unavailable in
+dra72x and is giving an abort during boot. The dra72x only list
+is empty for now and a placeholder for future hwmod additions which
+are specific to dra72x.
+
+Fixes: d904b38df0db13 ("ARM: DRA7: hwmod: Add SYSCONFIG for usb_otg_ss")
+Reported-by: Keerthy <j-keerthy@ti.com>
+Signed-off-by: Rajendra Nayak <rnayak@ti.com>
+Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
+Tested-by: Nishanth Menon <nm@ti.com>
+[paul@pwsan.com: fixed comment style to conform with CodingStyle]
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/arm/mach-omap2/omap_hwmod.c | 3 +++
+ arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 22 ++++++++++++++++++++--
+ 2 files changed, 23 insertions(+), 2 deletions(-)
+
+--- a/arch/arm/mach-omap2/omap_hwmod.c
++++ b/arch/arm/mach-omap2/omap_hwmod.c
+@@ -3349,6 +3349,9 @@ int __init omap_hwmod_register_links(str
+ if (!ois)
+ return 0;
+
++ if (ois[0] == NULL) /* Empty list */
++ return 0;
++
+ if (!linkspace) {
+ if (_alloc_linkspace(ois)) {
+ pr_err("omap_hwmod: could not allocate link space\n");
+--- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
+@@ -35,6 +35,7 @@
+ #include "i2c.h"
+ #include "mmc.h"
+ #include "wd_timer.h"
++#include "soc.h"
+
+ /* Base offset for all DRA7XX interrupts external to MPUSS */
+ #define DRA7XX_IRQ_GIC_START 32
+@@ -2705,7 +2706,6 @@ static struct omap_hwmod_ocp_if *dra7xx_
+ &dra7xx_l4_per3__usb_otg_ss1,
+ &dra7xx_l4_per3__usb_otg_ss2,
+ &dra7xx_l4_per3__usb_otg_ss3,
+- &dra7xx_l4_per3__usb_otg_ss4,
+ &dra7xx_l3_main_1__vcp1,
+ &dra7xx_l4_per2__vcp1,
+ &dra7xx_l3_main_1__vcp2,
+@@ -2714,8 +2714,26 @@ static struct omap_hwmod_ocp_if *dra7xx_
+ NULL,
+ };
+
++static struct omap_hwmod_ocp_if *dra74x_hwmod_ocp_ifs[] __initdata = {
++ &dra7xx_l4_per3__usb_otg_ss4,
++ NULL,
++};
++
++static struct omap_hwmod_ocp_if *dra72x_hwmod_ocp_ifs[] __initdata = {
++ NULL,
++};
++
+ int __init dra7xx_hwmod_init(void)
+ {
++ int ret;
++
+ omap_hwmod_init();
+- return omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs);
++ ret = omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs);
++
++ if (!ret && soc_is_dra74x())
++ return omap_hwmod_register_links(dra74x_hwmod_ocp_ifs);
++ else if (!ret && soc_is_dra72x())
++ return omap_hwmod_register_links(dra72x_hwmod_ocp_ifs);
++
++ return ret;
+ }
--- /dev/null
+From 1b134c9c4b555342be667f144ee714af1c3f6a9f Mon Sep 17 00:00:00 2001
+From: Markus Niebel <Markus.Niebel@tq-group.com>
+Date: Thu, 11 Sep 2014 15:56:56 +0800
+Subject: ARM: DT: imx53: fix lvds channel 1 port
+
+From: Markus Niebel <Markus.Niebel@tq-group.com>
+
+commit 1b134c9c4b555342be667f144ee714af1c3f6a9f upstream.
+
+using LVDS channel 1 on an i.MX53 leads to following error:
+
+imx-ldb 53fa8008.ldb: unable to set di0 parent clock to ldb_di1
+
+This comes from imx_ldb_set_clock with mux = 0. Mux parameter must be "1" for
+reparenting di1 clock to ldb_di1. The value of the mux param comes from device
+tree port settings.
+
+On i.MX5, the internal two-input-multiplexer is used. Due to hardware limitations,
+only one port (port@[0,1]) can be used for each channel (lvds-channel@[0,1],
+respectively)
+
+Documentation update suggested by Philipp Zabel <p.zabel@pengutronix.de>
+
+Signed-off-by: Markus Niebel <Markus.Niebel@tq-group.com>
+Fixes: e05c8c9a790a ("ARM: dts: imx53: Add IPU DI ports and endpoints, move imx-drm node to dtsi")
+Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
+Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
+Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ Documentation/devicetree/bindings/staging/imx-drm/ldb.txt | 15 ++++++++++++--
+ arch/arm/boot/dts/imx53.dtsi | 12 +++++++++--
+ 2 files changed, 23 insertions(+), 4 deletions(-)
+
+--- a/Documentation/devicetree/bindings/staging/imx-drm/ldb.txt
++++ b/Documentation/devicetree/bindings/staging/imx-drm/ldb.txt
+@@ -56,6 +56,9 @@ Required properties:
+ - fsl,data-width : should be <18> or <24>
+ - port: A port node with endpoint definitions as defined in
+ Documentation/devicetree/bindings/media/video-interfaces.txt.
++ On i.MX5, the internal two-input-multiplexer is used.
++ Due to hardware limitations, only one port (port@[0,1])
++ can be used for each channel (lvds-channel@[0,1], respectively)
+ On i.MX6, there should be four ports (port@[0-3]) that correspond
+ to the four LVDS multiplexer inputs.
+
+@@ -78,6 +81,8 @@ ldb: ldb@53fa8008 {
+ "di0", "di1";
+
+ lvds-channel@0 {
++ #address-cells = <1>;
++ #size-cells = <0>;
+ reg = <0>;
+ fsl,data-mapping = "spwg";
+ fsl,data-width = <24>;
+@@ -86,7 +91,9 @@ ldb: ldb@53fa8008 {
+ /* ... */
+ };
+
+- port {
++ port@0 {
++ reg = <0>;
++
+ lvds0_in: endpoint {
+ remote-endpoint = <&ipu_di0_lvds0>;
+ };
+@@ -94,6 +101,8 @@ ldb: ldb@53fa8008 {
+ };
+
+ lvds-channel@1 {
++ #address-cells = <1>;
++ #size-cells = <0>;
+ reg = <1>;
+ fsl,data-mapping = "spwg";
+ fsl,data-width = <24>;
+@@ -102,7 +111,9 @@ ldb: ldb@53fa8008 {
+ /* ... */
+ };
+
+- port {
++ port@1 {
++ reg = <1>;
++
+ lvds1_in: endpoint {
+ remote-endpoint = <&ipu_di1_lvds1>;
+ };
+--- a/arch/arm/boot/dts/imx53.dtsi
++++ b/arch/arm/boot/dts/imx53.dtsi
+@@ -419,10 +419,14 @@
+ status = "disabled";
+
+ lvds-channel@0 {
++ #address-cells = <1>;
++ #size-cells = <0>;
+ reg = <0>;
+ status = "disabled";
+
+- port {
++ port@0 {
++ reg = <0>;
++
+ lvds0_in: endpoint {
+ remote-endpoint = <&ipu_di0_lvds0>;
+ };
+@@ -430,10 +434,14 @@
+ };
+
+ lvds-channel@1 {
++ #address-cells = <1>;
++ #size-cells = <0>;
+ reg = <1>;
+ status = "disabled";
+
+- port {
++ port@1 {
++ reg = <1>;
++
+ lvds1_in: endpoint {
+ remote-endpoint = <&ipu_di1_lvds1>;
+ };
--- /dev/null
+From 5990047cef0c6a36eefcb166bd32d99a8f95c75b Mon Sep 17 00:00:00 2001
+From: Roger Quadros <rogerq@ti.com>
+Date: Wed, 10 Sep 2014 08:57:11 -0700
+Subject: ARM: dts: dra7-evm: Fix NAND GPMC timings
+
+From: Roger Quadros <rogerq@ti.com>
+
+commit 5990047cef0c6a36eefcb166bd32d99a8f95c75b upstream.
+
+The nand timings were scaled down by 2 to account for
+the 2x rate returned by clk_get_rate(gpmc_fclk).
+
+As the clock data got fixed by [1], revert back to actual
+timings (i.e. scale them up by 2).
+
+Without this NAND doesn't work on dra7-evm.
+
+[1] - commit dd94324b983afe114ba9e7ee3649313b451f63ce
+ ARM: dts: dra7xx-clocks: Fix the l3 and l4 clock rates
+
+Fixes: ff66a3c86e00 ("ARM: dts: dra7: add support for parallel NAND flash")
+Signed-off-by: Roger Quadros <rogerq@ti.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/arm/boot/dts/dra7-evm.dts | 27 ++++++++++++---------------
+ 1 file changed, 12 insertions(+), 15 deletions(-)
+
+--- a/arch/arm/boot/dts/dra7-evm.dts
++++ b/arch/arm/boot/dts/dra7-evm.dts
+@@ -427,22 +427,19 @@
+ gpmc,device-width = <2>;
+ gpmc,sync-clk-ps = <0>;
+ gpmc,cs-on-ns = <0>;
+- gpmc,cs-rd-off-ns = <40>;
+- gpmc,cs-wr-off-ns = <40>;
++ gpmc,cs-rd-off-ns = <80>;
++ gpmc,cs-wr-off-ns = <80>;
+ gpmc,adv-on-ns = <0>;
+- gpmc,adv-rd-off-ns = <30>;
+- gpmc,adv-wr-off-ns = <30>;
+- gpmc,we-on-ns = <5>;
+- gpmc,we-off-ns = <25>;
+- gpmc,oe-on-ns = <2>;
+- gpmc,oe-off-ns = <20>;
+- gpmc,access-ns = <20>;
+- gpmc,wr-access-ns = <40>;
+- gpmc,rd-cycle-ns = <40>;
+- gpmc,wr-cycle-ns = <40>;
+- gpmc,wait-pin = <0>;
+- gpmc,wait-on-read;
+- gpmc,wait-on-write;
++ gpmc,adv-rd-off-ns = <60>;
++ gpmc,adv-wr-off-ns = <60>;
++ gpmc,we-on-ns = <10>;
++ gpmc,we-off-ns = <50>;
++ gpmc,oe-on-ns = <4>;
++ gpmc,oe-off-ns = <40>;
++ gpmc,access-ns = <40>;
++ gpmc,wr-access-ns = <80>;
++ gpmc,rd-cycle-ns = <80>;
++ gpmc,wr-cycle-ns = <80>;
+ gpmc,bus-turnaround-ns = <0>;
+ gpmc,cycle2cycle-delay-ns = <0>;
+ gpmc,clk-activation-ns = <0>;
--- /dev/null
+From 68e4d9e58dbae2fb178e8b74806f521adb16f0d3 Mon Sep 17 00:00:00 2001
+From: Nishanth Menon <nm@ti.com>
+Date: Thu, 4 Sep 2014 08:33:37 -0500
+Subject: ARM: dts: dra7-evm: Fix spi1 mux documentation
+
+From: Nishanth Menon <nm@ti.com>
+
+commit 68e4d9e58dbae2fb178e8b74806f521adb16f0d3 upstream.
+
+While auditing the various pin ctrl configurations using the following
+command:
+grep PIN_ arch/arm/boot/dts/dra7-evm.dts|(while read line;
+do
+ v=`echo "$line" | sed -e "s/\s\s*/|/g" | cut -d '|' -f1 |
+ cut -d 'x' -f2|tr [a-z] [A-Z]`;
+ HEX=`echo "obase=16;ibase=16;4A003400+$v"| bc`;
+ echo "$HEX ===> $line";
+done)
+against DRA75x/74x NDA TRM revision S(SPRUHI2S August 2014),
+documentation errors were found for spi1 pinctrl. Fix the same.
+
+Fixes: 6e58b8f1daaf1af ("ARM: dts: DRA7: Add the dts files for dra7 SoC and dra7-evm board")
+Signed-off-by: Nishanth Menon <nm@ti.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/arm/boot/dts/dra7-evm.dts | 14 +++++++-------
+ 1 file changed, 7 insertions(+), 7 deletions(-)
+
+--- a/arch/arm/boot/dts/dra7-evm.dts
++++ b/arch/arm/boot/dts/dra7-evm.dts
+@@ -50,13 +50,13 @@
+
+ mcspi1_pins: pinmux_mcspi1_pins {
+ pinctrl-single,pins = <
+- 0x3a4 (PIN_INPUT | MUX_MODE0) /* spi2_clk */
+- 0x3a8 (PIN_INPUT | MUX_MODE0) /* spi2_d1 */
+- 0x3ac (PIN_INPUT | MUX_MODE0) /* spi2_d0 */
+- 0x3b0 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_cs0 */
+- 0x3b4 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_cs1 */
+- 0x3b8 (PIN_INPUT_SLEW | MUX_MODE6) /* spi2_cs2 */
+- 0x3bc (PIN_INPUT_SLEW | MUX_MODE6) /* spi2_cs3 */
++ 0x3a4 (PIN_INPUT | MUX_MODE0) /* spi1_sclk */
++ 0x3a8 (PIN_INPUT | MUX_MODE0) /* spi1_d1 */
++ 0x3ac (PIN_INPUT | MUX_MODE0) /* spi1_d0 */
++ 0x3b0 (PIN_INPUT_SLEW | MUX_MODE0) /* spi1_cs0 */
++ 0x3b4 (PIN_INPUT_SLEW | MUX_MODE0) /* spi1_cs1 */
++ 0x3b8 (PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs2.hdmi1_hpd */
++ 0x3bc (PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs3.hdmi1_cec */
+ >;
+ };
+
--- /dev/null
+From e49d519c456f4fb6f4a0473bc04ba30bb805fce5 Mon Sep 17 00:00:00 2001
+From: Nishanth Menon <nm@ti.com>
+Date: Mon, 25 Aug 2014 16:15:34 -0700
+Subject: ARM: dts: DRA7: fix interrupt-cells for GPIO
+
+From: Nishanth Menon <nm@ti.com>
+
+commit e49d519c456f4fb6f4a0473bc04ba30bb805fce5 upstream.
+
+GPIO modules are also interrupt sources. However, they require both the
+GPIO number and IRQ type to function properly.
+
+By declaring that GPIO uses interrupt-cells=<1>, we essentially do not
+allow users of the nodes to use the interrupt property appropritely.
+
+With this change, the following now works:
+
+interrupt-parent = <&gpio6>;
+interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
+
+Fixes: 6e58b8f1daaf ('ARM: dts: DRA7: Add the dts files for dra7 SoC and dra7-evm board')
+Signed-off-by: Nishanth Menon <nm@ti.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/arm/boot/dts/dra7.dtsi | 16 ++++++++--------
+ 1 file changed, 8 insertions(+), 8 deletions(-)
+
+--- a/arch/arm/boot/dts/dra7.dtsi
++++ b/arch/arm/boot/dts/dra7.dtsi
+@@ -172,7 +172,7 @@
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+- #interrupt-cells = <1>;
++ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio@48055000 {
+@@ -183,7 +183,7 @@
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+- #interrupt-cells = <1>;
++ #interrupt-cells = <2>;
+ };
+
+ gpio3: gpio@48057000 {
+@@ -194,7 +194,7 @@
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+- #interrupt-cells = <1>;
++ #interrupt-cells = <2>;
+ };
+
+ gpio4: gpio@48059000 {
+@@ -205,7 +205,7 @@
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+- #interrupt-cells = <1>;
++ #interrupt-cells = <2>;
+ };
+
+ gpio5: gpio@4805b000 {
+@@ -216,7 +216,7 @@
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+- #interrupt-cells = <1>;
++ #interrupt-cells = <2>;
+ };
+
+ gpio6: gpio@4805d000 {
+@@ -227,7 +227,7 @@
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+- #interrupt-cells = <1>;
++ #interrupt-cells = <2>;
+ };
+
+ gpio7: gpio@48051000 {
+@@ -238,7 +238,7 @@
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+- #interrupt-cells = <1>;
++ #interrupt-cells = <2>;
+ };
+
+ gpio8: gpio@48053000 {
+@@ -249,7 +249,7 @@
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+- #interrupt-cells = <1>;
++ #interrupt-cells = <2>;
+ };
+
+ uart1: serial@4806a000 {
--- /dev/null
+From 090727b880ff3c56e333f267cc24ab076f3bc096 Mon Sep 17 00:00:00 2001
+From: Fabio Estevam <fabio.estevam@freescale.com>
+Date: Thu, 7 Aug 2014 15:01:33 -0300
+Subject: ARM: dts: imx53-qsrb: Fix suspend/resume
+
+From: Fabio Estevam <fabio.estevam@freescale.com>
+
+commit 090727b880ff3c56e333f267cc24ab076f3bc096 upstream.
+
+The following error is seen after a suspend/resume cycle on a mx53qsb with a
+MC34708 PMIC:
+
+root@freescale /$ echo mem > /sys/power/state
+[ 32.630592] PM: Syncing filesystems ... done.
+[ 32.643924] Freezing user space processes ... (elapsed 0.001 seconds) done.
+[ 32.652384] Freezing remaining freezable tasks ... (elapsed 0.001 seconds) done.
+[ 32.679156] PM: suspend of devices complete after 13.113 msecs
+[ 32.685128] PM: suspend devices took 0.030 seconds
+[ 32.696109] PM: late suspend of devices complete after 6.133 msecs
+[ 33.313032] mc13xxx 0-0008: Failed to read IRQ status: -110
+[ 33.322009] PM: noirq suspend of devices complete after 619.667 msecs
+[ 33.328544] Disabling non-boot CPUs ...
+[ 33.335031] PM: noirq resume of devices complete after 2.352 msecs
+[ 33.842940] mc13xxx 0-0008: Failed to read IRQ status: -110
+[ 33.976095] [sched_delayed] sched: RT throttling activated
+[ 33.984804] PM: early resume of devices complete after 642.642 msecs
+[ 34.352954] mc13xxx 0-0008: Failed to read IRQ status: -110
+[ 34.862910] mc13xxx 0-0008: Failed to read IRQ status: -110
+[ 34.996595] PM: resume of devices complete after 1005.367 msecs
+[ 35.372925] mc13xxx 0-0008: Failed to read IRQ status: -110
+[ 35.882911] mc13xxx 0-0008: Failed to read IRQ status: -110
+[ 35.955707] PM: resume devices took 1.970 seconds
+[ 35.960445] Restarting tasks ... done.
+[ 35.993386] fec 63fec000.ethernet eth0: Link is Down
+[ 36.392980] mc13xxx 0-0008: Failed to read IRQ status: -110
+[ 36.902908] mc13xxx 0-0008: Failed to read IRQ status: -110
+[ 36.953036] ata1: SATA link down (SStatus 0 SControl 300)
+[ 37.412922] mc13xxx 0-0008: Failed to read IRQ status: -110
+[ 37.922906] mc13xxx 0-0008: Failed to read IRQ status: -110
+[ 37.993379] fec 63fec000.ethernet eth0: Link is Up - 100Mbps/Full - flow control rx/tx
+[ 38.432938] mc13xxx 0-0008: Failed to read IRQ status: -110
+[ 38.942920] mc13xxx 0-0008: Failed to read IRQ status: -110
+[ 39.452933] mc13xxx 0-0008: Failed to read IRQ status: -110
+
+(flood of this error message continues forever)
+
+Commit 5169df8be0a432ee ("ARM: dts: i.MX53: add support for MCIMX53-START-R")
+missed to configure the IOMUX for the PMIC IRQ pin.
+
+Configure the PMIC IRQ pin so that the suspend/resume sequence behaves cleanly
+as expected.
+
+Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
+Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/arm/boot/dts/imx53-qsrb.dts | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+--- a/arch/arm/boot/dts/imx53-qsrb.dts
++++ b/arch/arm/boot/dts/imx53-qsrb.dts
+@@ -28,6 +28,12 @@
+ MX53_PAD_CSI0_DAT9__I2C1_SCL 0x400001ec
+ >;
+ };
++
++ pinctrl_pmic: pmicgrp {
++ fsl,pins = <
++ MX53_PAD_CSI0_DAT5__GPIO5_23 0x1e4 /* IRQ */
++ >;
++ };
+ };
+ };
+
+@@ -38,6 +44,8 @@
+
+ pmic: mc34708@8 {
+ compatible = "fsl,mc34708";
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_pmic>;
+ reg = <0x08>;
+ interrupt-parent = <&gpio5>;
+ interrupts = <23 0x8>;
--- /dev/null
+From 929a015b1809a30748d487f9d25b16a41434b61a Mon Sep 17 00:00:00 2001
+From: Peter Ujfalusi <peter.ujfalusi@ti.com>
+Date: Mon, 4 Aug 2014 15:26:56 +0300
+Subject: ARM: edma: Fix configuration parsing for SoCs with multiple eDMA3 CC
+
+From: Peter Ujfalusi <peter.ujfalusi@ti.com>
+
+commit 929a015b1809a30748d487f9d25b16a41434b61a upstream.
+
+The edma_setup_from_hw() should know about the CC number when parsing the
+CCCFG register - when it reads the register to be precise. The base
+addresses for CCs stored in an array and we need to provide the correct id
+to edma_read() in order to read the correct register.
+
+Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
+Signed-off-by: Sekhar Nori <nsekhar@ti.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/arm/common/edma.c | 9 +++++----
+ 1 file changed, 5 insertions(+), 4 deletions(-)
+
+--- a/arch/arm/common/edma.c
++++ b/arch/arm/common/edma.c
+@@ -1415,14 +1415,14 @@ void edma_clear_event(unsigned channel)
+ EXPORT_SYMBOL(edma_clear_event);
+
+ static int edma_setup_from_hw(struct device *dev, struct edma_soc_info *pdata,
+- struct edma *edma_cc)
++ struct edma *edma_cc, int cc_id)
+ {
+ int i;
+ u32 value, cccfg;
+ s8 (*queue_priority_map)[2];
+
+ /* Decode the eDMA3 configuration from CCCFG register */
+- cccfg = edma_read(0, EDMA_CCCFG);
++ cccfg = edma_read(cc_id, EDMA_CCCFG);
+
+ value = GET_NUM_REGN(cccfg);
+ edma_cc->num_region = BIT(value);
+@@ -1436,7 +1436,8 @@ static int edma_setup_from_hw(struct dev
+ value = GET_NUM_EVQUE(cccfg);
+ edma_cc->num_tc = value + 1;
+
+- dev_dbg(dev, "eDMA3 HW configuration (cccfg: 0x%08x):\n", cccfg);
++ dev_dbg(dev, "eDMA3 CC%d HW configuration (cccfg: 0x%08x):\n", cc_id,
++ cccfg);
+ dev_dbg(dev, "num_region: %u\n", edma_cc->num_region);
+ dev_dbg(dev, "num_channel: %u\n", edma_cc->num_channels);
+ dev_dbg(dev, "num_slot: %u\n", edma_cc->num_slots);
+@@ -1655,7 +1656,7 @@ static int edma_probe(struct platform_de
+ return -ENOMEM;
+
+ /* Get eDMA3 configuration from IP */
+- ret = edma_setup_from_hw(dev, info[j], edma_cc[j]);
++ ret = edma_setup_from_hw(dev, info[j], edma_cc[j], j);
+ if (ret)
+ return ret;
+
--- /dev/null
+From 9e1ac462b982f496ed3b491f02c417dcc8e40347 Mon Sep 17 00:00:00 2001
+From: Shawn Guo <shawn.guo@freescale.com>
+Date: Tue, 16 Sep 2014 09:35:33 +0800
+Subject: ARM: imx: fix .is_enabled() of shared gate clock
+
+From: Shawn Guo <shawn.guo@freescale.com>
+
+commit 9e1ac462b982f496ed3b491f02c417dcc8e40347 upstream.
+
+Commit 63288b721a80 ("ARM: imx: fix shared gate clock") attempted to fix
+an issue with particular enable/disable sequence from two shared gate
+clocks. But unfortunately, while it partially fixed the issue, it also
+did something wrong in .is_enabled() function hook. In case of shared
+gate, the function shouldn't really query the hardware state via
+share_count, because the function is trying to query the enabling state
+of the clock in question, not the hardware state which is shared by
+multiple clocks.
+
+Fix the issue by returning the enable_count of the clock itself which is
+maintained by clock core, in case it's a clock sharing hardware gate
+with others. As the result, the initialization of share_count per
+hardware state is not needed now. So remove it.
+
+Reported-by: Fabio Estevam <fabio.estevam@freescale.com>
+Fixes: 63288b721a80 ("ARM: imx: fix shared gate clock")
+Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
+Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
+Signed-off-by: Olof Johansson <olof@lixom.net>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/arm/mach-imx/clk-gate2.c | 6 +-----
+ 1 file changed, 1 insertion(+), 5 deletions(-)
+
+--- a/arch/arm/mach-imx/clk-gate2.c
++++ b/arch/arm/mach-imx/clk-gate2.c
+@@ -97,7 +97,7 @@ static int clk_gate2_is_enabled(struct c
+ struct clk_gate2 *gate = to_clk_gate2(hw);
+
+ if (gate->share_count)
+- return !!(*gate->share_count);
++ return !!__clk_get_enable_count(hw->clk);
+ else
+ return clk_gate2_reg_is_enabled(gate->reg, gate->bit_idx);
+ }
+@@ -127,10 +127,6 @@ struct clk *clk_register_gate2(struct de
+ gate->bit_idx = bit_idx;
+ gate->flags = clk_gate2_flags;
+ gate->lock = lock;
+-
+- /* Initialize share_count per hardware state */
+- if (share_count)
+- *share_count = clk_gate2_reg_is_enabled(reg, bit_idx) ? 1 : 0;
+ gate->share_count = share_count;
+
+ init.name = name;
nfs-don-t-sleep-with-inode-lock-in-lock_and_join_requests.patch
nfs-disallow-duplicate-pages-in-pgio-page-vectors.patch
nfs-can_coalesce_requests-must-enforce-contiguity.patch
+spi-omap-mcspi-fix-the-spi-task-hangs-waiting-dma_rx.patch
+spi-dw-fix-kernel-crash-due-to-null-pointer-dereference.patch
+spi-dw-pci-fix-bug-when-regs-left-uninitialized.patch
+arm-8128-1-abort-don-t-clear-the-exclusive-monitors.patch
+arm-8129-1-errata-work-around-cortex-a15-erratum-830321-using-dummy-strex.patch
+arm-dts-imx53-qsrb-fix-suspend-resume.patch
+arm-dra7-hwmod-add-dra74x-and-dra72x-specific-ocp-interface-lists.patch
+arm-dts-dra7-fix-interrupt-cells-for-gpio.patch
+arm-edma-fix-configuration-parsing-for-socs-with-multiple-edma3-cc.patch
+arm-dts-dra7-evm-fix-spi1-mux-documentation.patch
+arm-8133-1-use-irq_set_affinity-with-force-false-when-migrating-irqs.patch
+arm-8148-1-flush-tls-and-thumbee-register-state-during-exec.patch
+arm-8149-1-perf-don-t-sleep-while-atomic-when-enabling-per-cpu-interrupts.patch
+arm-dts-dra7-evm-fix-nand-gpmc-timings.patch
+arm-dt-imx53-fix-lvds-channel-1-port.patch
+arm-imx-fix-.is_enabled-of-shared-gate-clock.patch
+arm-8165-1-alignment-don-t-break-misaligned-neon-load-store.patch
+arm-8178-1-fix-set_tls-for-config_kuser_helpers.patch
--- /dev/null
+From 08a707b87874eaaa0f336ab604ecd6e5e9f286dd Mon Sep 17 00:00:00 2001
+From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
+Date: Wed, 27 Aug 2014 19:26:08 +0300
+Subject: spi: dw: fix kernel crash due to NULL pointer dereference
+
+From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
+
+commit 08a707b87874eaaa0f336ab604ecd6e5e9f286dd upstream.
+
+The obvious fix after the commit d9c73bb8a3a5 "spi: dw: add support for gpio
+controlled chip select". This patch fixes the issue by using locally defined
+temporary variable.
+
+Fixes: d9c73bb8a3a5 (spi: dw: add support for gpio controlled chip select)
+Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
+Signed-off-by: Mark Brown <broonie@linaro.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/spi/spi-dw.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/spi/spi-dw.c
++++ b/drivers/spi/spi-dw.c
+@@ -271,7 +271,7 @@ static void giveback(struct dw_spi *dws)
+ transfer_list);
+
+ if (!last_transfer->cs_change)
+- spi_chip_sel(dws, dws->cur_msg->spi, 0);
++ spi_chip_sel(dws, msg->spi, 0);
+
+ spi_finalize_current_message(dws->master);
+ }
--- /dev/null
+From c9d5d6fe168fd45a4dfdd0116affe708789b4702 Mon Sep 17 00:00:00 2001
+From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
+Date: Wed, 27 Aug 2014 16:21:12 +0300
+Subject: spi: dw-pci: fix bug when regs left uninitialized
+
+From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
+
+commit c9d5d6fe168fd45a4dfdd0116affe708789b4702 upstream.
+
+The commit 04f421e7 "spi: dw: use managed resources" changes drivers to use
+managed functions, but seems wasn't properly tested in PCI case. The regs field
+of struct dw_spi left uninitialized. Thus, kernel crashes when tries to access
+to the SPI controller registers. This patch fixes the issue.
+
+Fixes: 04f421e7 (spi: dw: use managed resources)
+Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
+Signed-off-by: Mark Brown <broonie@linaro.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/spi/spi-dw-pci.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/drivers/spi/spi-dw-pci.c
++++ b/drivers/spi/spi-dw-pci.c
+@@ -62,6 +62,8 @@ static int spi_pci_probe(struct pci_dev
+ if (ret)
+ return ret;
+
++ dws->regs = pcim_iomap_table(pdev)[pci_bar];
++
+ dws->bus_num = 0;
+ dws->num_cs = 4;
+ dws->irq = pdev->irq;
--- /dev/null
+From 3d0763c006f8da1b44a9f5f9a21187f5b8f674f4 Mon Sep 17 00:00:00 2001
+From: "Jorge A. Ventura" <jorge.araujo.ventura@gmail.com>
+Date: Sat, 9 Aug 2014 16:06:58 -0500
+Subject: spi/omap-mcspi: Fix the spi task hangs waiting dma_rx
+
+From: "Jorge A. Ventura" <jorge.araujo.ventura@gmail.com>
+
+commit 3d0763c006f8da1b44a9f5f9a21187f5b8f674f4 upstream.
+
+The spi hangs waiting the completion of omap2_mcspi_rx_callback.
+
+Signed-off-by: Jorge A. Ventura <jorge.araujo.ventura@gmail.com>
+Signed-off-by: Mark Brown <broonie@linaro.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/spi/spi-omap2-mcspi.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+--- a/drivers/spi/spi-omap2-mcspi.c
++++ b/drivers/spi/spi-omap2-mcspi.c
+@@ -329,7 +329,8 @@ static void omap2_mcspi_set_fifo(const s
+ disable_fifo:
+ if (t->rx_buf != NULL)
+ chconf &= ~OMAP2_MCSPI_CHCONF_FFER;
+- else
++
++ if (t->tx_buf != NULL)
+ chconf &= ~OMAP2_MCSPI_CHCONF_FFET;
+
+ mcspi_write_chconf0(spi, chconf);
projects / thirdparty / kernel / stable-queue.git / commitdiff
