--- /dev/null
+From fac33aa62841b69cd0e19a29b0e2ac96e4e8cf32 Mon Sep 17 00:00:00 2001
+From: Nitin Gupta <nitin.m.gupta@oracle.com>
+Date: Fri, 3 Nov 2017 12:26:06 -0700
+Subject: sparc64: Fix page table walk for PUD hugepages
+
+From: Nitin Gupta <nitin.m.gupta@oracle.com>
+
+[ Upstream commit 70f3c8b7c2e7ebcdde8354da004872e7c9184e97 ]
+
+For a PUD hugepage entry, we need to propagate bits [32:22]
+from virtual address to resolve at 4M granularity. However,
+the current code was incorrectly propagating bits [29:19].
+This bug can cause incorrect data to be returned for pages
+backed with 16G hugepages.
+
+Signed-off-by: Nitin Gupta <nitin.m.gupta@oracle.com>
+Reported-by: Al Viro <viro@ZenIV.linux.org.uk>
+Cc: Al Viro <viro@ZenIV.linux.org.uk>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ arch/sparc/include/asm/tsb.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/sparc/include/asm/tsb.h b/arch/sparc/include/asm/tsb.h
+index 25b6abdb3908..522a677e050d 100644
+--- a/arch/sparc/include/asm/tsb.h
++++ b/arch/sparc/include/asm/tsb.h
+@@ -217,7 +217,7 @@ extern struct tsb_phys_patch_entry __tsb_phys_patch, __tsb_phys_patch_end;
+ sllx REG2, 32, REG2; \
+ andcc REG1, REG2, %g0; \
+ be,pt %xcc, 700f; \
+- sethi %hi(0x1ffc0000), REG2; \
++ sethi %hi(0xffe00000), REG2; \
+ sllx REG2, 1, REG2; \
+ brgez,pn REG1, FAIL_LABEL; \
+ andn REG1, REG2, REG1; \
+--
+2.13.6
+