]> git.ipfire.org Git - thirdparty/binutils-gdb.git/commitdiff
Add testsuits for new assembler option of mthin-add-sub. gdb-14-branchpoint
authorcailulu <cailulu@loongson.cn>
Thu, 28 Sep 2023 08:01:53 +0000 (16:01 +0800)
committerliuzhensong <liuzhensong@loongson.cn>
Sun, 8 Oct 2023 01:18:12 +0000 (09:18 +0800)
gas/testsuite/gas/loongarch/no_thin_add_sub.d [new file with mode: 0644]
gas/testsuite/gas/loongarch/no_thin_add_sub.s [new file with mode: 0644]
gas/testsuite/gas/loongarch/thin_add_sub_norelax.d [moved from gas/testsuite/gas/loongarch/pcrel_norelax.d with 75% similarity]
gas/testsuite/gas/loongarch/thin_add_sub_norelax.s [moved from gas/testsuite/gas/loongarch/pcrel_norelax.s with 87% similarity]
gas/testsuite/gas/loongarch/thin_add_sub_relax.d [moved from gas/testsuite/gas/loongarch/pcrel_relax.d with 91% similarity]
gas/testsuite/gas/loongarch/thin_add_sub_relax.s [moved from gas/testsuite/gas/loongarch/pcrel_relax.s with 100% similarity]

diff --git a/gas/testsuite/gas/loongarch/no_thin_add_sub.d b/gas/testsuite/gas/loongarch/no_thin_add_sub.d
new file mode 100644 (file)
index 0000000..614aca7
--- /dev/null
@@ -0,0 +1,66 @@
+#as:
+#objdump: -Dr
+
+.*:[    ]+file format .*
+
+
+Disassembly of section .text:
+
+00000000.* <.L1>:
+[      ]+...
+[      ]+0:[   ]+R_LARCH_ADD32[        ]+.L3
+[      ]+0:[   ]+R_LARCH_SUB32[        ]+.L1
+[      ]+4:[   ]+R_LARCH_ADD32[        ]+.L3
+[      ]+4:[   ]+R_LARCH_SUB32[        ]+.L1
+
+0*00000008[    ]+<.L2>:
+[      ]+...
+[      ]+8:[   ]+R_LARCH_ADD64[        ]+.L3
+[      ]+8:[   ]+R_LARCH_SUB64[        ]+.L2
+[      ]+10:[  ]+R_LARCH_ADD64[        ]+.L3
+[      ]+10:[  ]+R_LARCH_SUB64[        ]+.L2
+
+Disassembly[   ]+of[   ]+section[      ]+sx:
+
+0*00000000[    ]+<.L3>:
+[      ]+0:[   ]+fffffff4[     ]+.word[        ]+0xfffffff4
+[      ]+4:[   ]+fffffff4[     ]+.word[        ]+0xfffffff4
+[      ]+8:[   ]+ffffffff[     ]+.word[        ]+0xffffffff
+
+0*0000000c[    ]+<.L4>:
+[      ]+...
+[      ]+c:[   ]+R_LARCH_ADD32[        ]+.L4
+[      ]+c:[   ]+R_LARCH_SUB32[        ]+.L5
+[      ]+10:[  ]+R_LARCH_ADD64[        ]+.L4
+[      ]+10:[  ]+R_LARCH_SUB64[        ]+.L5
+
+Disassembly[   ]+of[   ]+section[      ]+sy:
+
+0*00000000[    ]+<.L5>:
+[      ]+...
+[      ]+0:[   ]+R_LARCH_ADD32[        ]+.L1
+[      ]+0:[   ]+R_LARCH_SUB32[        ]+.L5
+[      ]+4:[   ]+R_LARCH_ADD32[        ]+.L3
+[      ]+4:[   ]+R_LARCH_SUB32[        ]+.L5
+[      ]+8:[   ]+R_LARCH_ADD64[        ]+.L1
+[      ]+8:[   ]+R_LARCH_SUB64[        ]+.L5
+[      ]+10:[  ]+R_LARCH_ADD64[        ]+.L3
+[      ]+10:[  ]+R_LARCH_SUB64[        ]+.L5
+
+Disassembly[   ]+of[   ]+section[      ]+sz:
+
+0*00000000[    ]+<sz>:
+[      ]+0:[   ]+00000000[     ]+.word[        ]+0x00000000
+[      ]+0:[   ]+R_LARCH_ADD32[        ]+.L1
+[      ]+0:[   ]+R_LARCH_SUB32[        ]+.L2
+[      ]+4:[   ]+fffffff4[     ]+.word[        ]+0xfffffff4
+[      ]+...
+[      ]+8:[   ]+R_LARCH_ADD32[        ]+.L3
+[      ]+8:[   ]+R_LARCH_SUB32[        ]+.L5
+[      ]+c:[   ]+R_LARCH_ADD64[        ]+.L1
+[      ]+c:[   ]+R_LARCH_SUB64[        ]+.L2
+[      ]+14:[  ]+fffffff4[     ]+.word[        ]+0xfffffff4
+[      ]+18:[  ]+ffffffff[     ]+.word[        ]+0xffffffff
+[      ]+...
+[      ]+1c:[  ]+R_LARCH_ADD64[        ]+.L3
+[      ]+1c:[  ]+R_LARCH_SUB64[        ]+.L5
diff --git a/gas/testsuite/gas/loongarch/no_thin_add_sub.s b/gas/testsuite/gas/loongarch/no_thin_add_sub.s
new file mode 100644 (file)
index 0000000..c680168
--- /dev/null
@@ -0,0 +1,44 @@
+  .section .text
+.L1:
+  # add32+sub32
+  .4byte .L3-.L1
+  .4byte .L3-.L1
+.L2:
+  # add64+sub64
+  .8byte .L3-.L2
+  .8byte .L3-.L2
+
+  .section sx
+.L3:
+  # no relocation
+  .4byte .L3-.L4
+  .8byte .L3-.L4
+.L4:
+  # add32+sub32
+  .4byte .L4-.L5
+  # add64+sub64
+  .8byte .L4-.L5
+
+  .section sy
+.L5:
+  # add32+sub32
+  .4byte .L1-.L5
+  .4byte .L3-.L5
+  # add64+sub64
+  .8byte .L1-.L5
+  .8byte .L3-.L5
+
+  .section sz
+  # add32+sub32
+  .4byte .L1-.L2
+  # no relocation
+  .4byte .L3-.L4
+  # add32+sub32
+  .4byte .L3-.L5
+
+  # add64+sub64
+  .8byte .L1-.L2
+  # no relocation
+  .8byte .L3-.L4
+  # add64+sub64
+  .8byte .L3-.L5
similarity index 75%
rename from gas/testsuite/gas/loongarch/pcrel_norelax.d
rename to gas/testsuite/gas/loongarch/thin_add_sub_norelax.d
index 842c8d48e0e82b7e4d5d6757e8128e27ae4223c4..702093b6997b2d75dfa589646994048e463574f9 100644 (file)
@@ -1,4 +1,4 @@
-#as: -mno-relax
+#as: -mthin-add-sub -mno-relax
 #objdump: -Dr
 
 .*:[    ]+file format .*
@@ -10,20 +10,17 @@ Disassembly of section .text:
 [      ]+...
 [      ]+0:[   ]+R_LARCH_32_PCREL[     ]+.L3
 [      ]+4:[   ]+R_LARCH_32_PCREL[     ]+.L3\+0x4
-
-0*00000008[ ]+<.L2>:
-[      ]+...
 [      ]+8:[   ]+R_LARCH_64_PCREL[     ]+.L3
 [      ]+10:[  ]+R_LARCH_64_PCREL[     ]+.L3\+0x8
 
 Disassembly[   ]+of[   ]+section[      ]+sx:
 
-0*00000000[ ]+<.L3>:
+0*00000000[    ]+<.L3>:
 [      ]+0:[   ]+fffffff4[     ]+.word[        ]+0xfffffff4
 [      ]+4:[   ]+fffffff4[     ]+.word[        ]+0xfffffff4
 [      ]+8:[   ]+ffffffff[     ]+.word[        ]+0xffffffff
 
-0*0000000c[ ]+<.L4>:
+0*0000000c[    ]+<.L4>:
 [      ]+...
 [      ]+c:[   ]+R_LARCH_ADD32[        ]+.L4
 [      ]+c:[   ]+R_LARCH_SUB32[        ]+.L5
@@ -32,25 +29,25 @@ Disassembly[        ]+of[   ]+section[      ]+sx:
 
 Disassembly[   ]+of[   ]+section[      ]+sy:
 
-0*00000000[ ]+<.L5>:
+0*00000000[    ]+<.L5>:
 [      ]+...
 [      ]+0:[   ]+R_LARCH_32_PCREL[     ]+.L1
-[      ]+4:[   ]+R_LARCH_32_PCREL[     ]+.L2\+0x4
+[      ]+4:[   ]+R_LARCH_32_PCREL[     ]+.L3\+0x4
 [      ]+8:[   ]+R_LARCH_64_PCREL[     ]+.L1\+0x8
-[      ]+10:[  ]+R_LARCH_64_PCREL[     ]+.L2\+0x10
+[      ]+10:[  ]+R_LARCH_64_PCREL[     ]+.L3\+0x10
 
 Disassembly[   ]+of[   ]+section[      ]+sz:
 
-0*00000000[ ]+<sz>:
+0*00000000[    ]+<sz>:
 [      ]+0:[   ]+fffffff8[     ]+.word[        ]+0xfffffff8
 [      ]+4:[   ]+fffffff4[     ]+.word[        ]+0xfffffff4
 [      ]+8:[   ]+00000000[     ]+.word[        ]+0x00000000
-[      ]+8:[   ]+R_LARCH_ADD32[        ]+.L2
-[      ]+8:[   ]+R_LARCH_SUB32[        ]+.L3
+[      ]+8:[   ]+R_LARCH_ADD32[        ]+.L3
+[      ]+8:[   ]+R_LARCH_SUB32[        ]+.L5
 [      ]+c:[   ]+fffffff8[     ]+.word[        ]+0xfffffff8
 [      ]+10:[  ]+ffffffff[     ]+.word[        ]+0xffffffff
 [      ]+14:[  ]+fffffff4[     ]+.word[        ]+0xfffffff4
 [      ]+18:[  ]+ffffffff[     ]+.word[        ]+0xffffffff
 [      ]+...
-[      ]+1c:[  ]+R_LARCH_ADD64[        ]+.L2
-[      ]+1c:[  ]+R_LARCH_SUB64[        ]+.L3
+[      ]+1c:[  ]+R_LARCH_ADD64[        ]+.L3
+[      ]+1c:[  ]+R_LARCH_SUB64[        ]+.L5
similarity index 87%
rename from gas/testsuite/gas/loongarch/pcrel_norelax.s
rename to gas/testsuite/gas/loongarch/thin_add_sub_norelax.s
index 09527f146a9b6841d1e1c45283731b20dddb1704..94cfd90870c0b984d5aab2f31d1ea023dbf10326 100644 (file)
 .L5:
   # 32_pcrel
   .4byte .L1-.L5
-  .4byte .L2-.L5
+  .4byte .L3-.L5
   # 64_pcrel
   .8byte .L1-.L5
-  .8byte .L2-.L5
+  .8byte .L3-.L5
 
   .section sz
   # no relocation
   .4byte .L1-.L2
   .4byte .L3-.L4
   # add32+sub32
-  .4byte .L2-.L3
+  .4byte .L3-.L5
 
   # no relocation
   .8byte .L1-.L2
   .8byte .L3-.L4
   # add64+sub64
-  .8byte .L2-.L3
+  .8byte .L3-.L5
similarity index 91%
rename from gas/testsuite/gas/loongarch/pcrel_relax.d
rename to gas/testsuite/gas/loongarch/thin_add_sub_relax.d
index d6f875259be9de864a2d22004a542c3461a3ad93..9455c3e66bf282090cd55a038899079ea6bf37bb 100644 (file)
@@ -1,4 +1,4 @@
-#as:
+#as: -mthin-add-sub
 #objdump: -Dr
 
 .*:[    ]+file format .*
@@ -12,7 +12,7 @@ Disassembly of section .text:
 [      ]+4:[   ]+R_LARCH_ADD32[        ]+.L3
 [      ]+4:[   ]+R_LARCH_SUB32[        ]+.L1
 
-0*00000008[ ]+<.L2>:
+0*00000008[    ]+<.L2>:
 [      ]+...
 [      ]+8:[   ]+R_LARCH_64_PCREL[     ]+.L3
 [      ]+10:[  ]+R_LARCH_ADD64[        ]+.L3
@@ -20,12 +20,12 @@ Disassembly of section .text:
 
 Disassembly[   ]+of[   ]+section[      ]+sx:
 
-0*00000000[ ]+<.L3>:
+0*00000000[    ]+<.L3>:
 [      ]+0:[   ]+fffffff4[     ]+.word[        ]+0xfffffff4
 [      ]+4:[   ]+fffffff4[     ]+.word[        ]+0xfffffff4
 [      ]+8:[   ]+ffffffff[     ]+.word[        ]+0xffffffff
 
-0*0000000c[ ]+<.L4>:
+0*0000000c[    ]+<.L4>:
 [      ]+...
 [      ]+c:[   ]+R_LARCH_ADD32[        ]+.L4
 [      ]+c:[   ]+R_LARCH_SUB32[        ]+.L5
@@ -34,7 +34,7 @@ Disassembly[  ]+of[   ]+section[      ]+sx:
 
 Disassembly[   ]+of[   ]+section[      ]+sy:
 
-0*00000000[ ]+<.L5>:
+0*00000000[    ]+<.L5>:
 [      ]+...
 [      ]+0:[   ]+R_LARCH_32_PCREL[     ]+.L1
 [      ]+4:[   ]+R_LARCH_32_PCREL[     ]+.L3\+0x4
@@ -43,7 +43,7 @@ Disassembly[  ]+of[   ]+section[      ]+sy:
 
 Disassembly[   ]+of[   ]+section[      ]+sz:
 
-0*00000000[ ]+<sz>:
+0*00000000[    ]+<sz>:
 [      ]+0:[   ]+00000000[     ]+.word[        ]+0x00000000
 [      ]+0:[   ]+R_LARCH_ADD32[        ]+.L1
 [      ]+0:[   ]+R_LARCH_SUB32[        ]+.L2