+++ /dev/null
-From 0dfa9ebb251240ebcef8877e48d2a5c4fdb19c5b Mon Sep 17 00:00:00 2001
-From: Sasha Levin <sashal@kernel.org>
-Date: Tue, 28 Dec 2021 07:54:12 +0300
-Subject: clk: qcom: gcc-msm8996: drop unsupported clock sources
-
-From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-
-[ Upstream commit b554a687b4971ae137e92ee3feddc38e85a38d60 ]
-
-In preparation of updating the msm8996 gcc driver, drop all unsupported
-GPLL sources (gpll1/gpll1_early_div, gpll2/gpll2_early and gpll3).
-Downstream kernel also does not provide support for these GPLL sources,
-so it is safe to drop them.
-
-Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Link: https://lore.kernel.org/r/20211228045415.20543-14-dmitry.baryshkov@linaro.org
-Stable-dep-of: 4afda5f6bcdf ("clk: qcom: gcc-msm8996: Remove RPM bus clocks")
-Signed-off-by: Sasha Levin <sashal@kernel.org>
----
- drivers/clk/qcom/gcc-msm8996.c | 55 ++++------------------------------
- 1 file changed, 6 insertions(+), 49 deletions(-)
-
-diff --git a/drivers/clk/qcom/gcc-msm8996.c b/drivers/clk/qcom/gcc-msm8996.c
-index d95814025c65e..4c85b3935a819 100644
---- a/drivers/clk/qcom/gcc-msm8996.c
-+++ b/drivers/clk/qcom/gcc-msm8996.c
-@@ -27,15 +27,10 @@
- enum {
- P_XO,
- P_GPLL0,
-- P_GPLL2,
-- P_GPLL3,
-- P_GPLL1,
-- P_GPLL2_EARLY,
- P_GPLL0_EARLY_DIV,
- P_SLEEP_CLK,
- P_GPLL4,
- P_AUD_REF_CLK,
-- P_GPLL1_EARLY_DIV
- };
-
- static const struct parent_map gcc_sleep_clk_map[] = {
-@@ -130,44 +125,6 @@ static const char * const gcc_xo_gpll0_gpll4_gpll0_early_div[] = {
- "gpll0_early_div"
- };
-
--static const struct parent_map gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div_map[] = {
-- { P_XO, 0 },
-- { P_GPLL0, 1 },
-- { P_GPLL1_EARLY_DIV, 3 },
-- { P_GPLL1, 4 },
-- { P_GPLL4, 5 },
-- { P_GPLL0_EARLY_DIV, 6 }
--};
--
--static const char * const gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div[] = {
-- "xo",
-- "gpll0",
-- "gpll1_early_div",
-- "gpll1",
-- "gpll4",
-- "gpll0_early_div"
--};
--
--static const struct parent_map gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div_map[] = {
-- { P_XO, 0 },
-- { P_GPLL0, 1 },
-- { P_GPLL2, 2 },
-- { P_GPLL3, 3 },
-- { P_GPLL1, 4 },
-- { P_GPLL2_EARLY, 5 },
-- { P_GPLL0_EARLY_DIV, 6 }
--};
--
--static const char * const gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div[] = {
-- "xo",
-- "gpll0",
-- "gpll2",
-- "gpll3",
-- "gpll1",
-- "gpll2_early",
-- "gpll0_early_div"
--};
--
- static struct clk_fixed_factor xo = {
- .mult = 1,
- .div = 1,
-@@ -285,12 +242,12 @@ static const struct freq_tbl ftbl_system_noc_clk_src[] = {
- static struct clk_rcg2 system_noc_clk_src = {
- .cmd_rcgr = 0x0401c,
- .hid_width = 5,
-- .parent_map = gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div_map,
-+ .parent_map = gcc_xo_gpll0_gpll0_early_div_map,
- .freq_tbl = ftbl_system_noc_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "system_noc_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div,
-- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div),
-+ .parent_names = gcc_xo_gpll0_gpll0_early_div,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1257,12 +1214,12 @@ static const struct freq_tbl ftbl_qspi_ser_clk_src[] = {
- static struct clk_rcg2 qspi_ser_clk_src = {
- .cmd_rcgr = 0x8b00c,
- .hid_width = 5,
-- .parent_map = gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div_map,
-+ .parent_map = gcc_xo_gpll0_gpll4_gpll0_early_div_map,
- .freq_tbl = ftbl_qspi_ser_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "qspi_ser_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div,
-- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div),
-+ .parent_names = gcc_xo_gpll0_gpll4_gpll0_early_div,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_gpll0_early_div),
- .ops = &clk_rcg2_ops,
- },
- };
---
-2.42.0
-
+++ /dev/null
-From 3bee5dfab0b5aad9aa78a9ad9b322f763d616f27 Mon Sep 17 00:00:00 2001
-From: Sasha Levin <sashal@kernel.org>
-Date: Tue, 28 Dec 2021 07:54:13 +0300
-Subject: clk: qcom: gcc-msm8996: move clock parent tables down
-
-From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-
-[ Upstream commit 1a2789cff03ccdeb70084157387f4a7bf4d2099f ]
-
-Move clock parent tables down, after the GPLL declrataions, so that we
-can use gpll hw clock fields in the next commit.
-
-Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
-Reviewed-by: Stephen Boyd <sboyd@kernel.org>
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Link: https://lore.kernel.org/r/20211228045415.20543-15-dmitry.baryshkov@linaro.org
-Stable-dep-of: 4afda5f6bcdf ("clk: qcom: gcc-msm8996: Remove RPM bus clocks")
-Signed-off-by: Sasha Levin <sashal@kernel.org>
----
- drivers/clk/qcom/gcc-msm8996.c | 184 ++++++++++++++++-----------------
- 1 file changed, 92 insertions(+), 92 deletions(-)
-
-diff --git a/drivers/clk/qcom/gcc-msm8996.c b/drivers/clk/qcom/gcc-msm8996.c
-index 4c85b3935a819..8531f2f3665fe 100644
---- a/drivers/clk/qcom/gcc-msm8996.c
-+++ b/drivers/clk/qcom/gcc-msm8996.c
-@@ -33,98 +33,6 @@ enum {
- P_AUD_REF_CLK,
- };
-
--static const struct parent_map gcc_sleep_clk_map[] = {
-- { P_SLEEP_CLK, 5 }
--};
--
--static const char * const gcc_sleep_clk[] = {
-- "sleep_clk"
--};
--
--static const struct parent_map gcc_xo_gpll0_map[] = {
-- { P_XO, 0 },
-- { P_GPLL0, 1 }
--};
--
--static const char * const gcc_xo_gpll0[] = {
-- "xo",
-- "gpll0"
--};
--
--static const struct parent_map gcc_xo_sleep_clk_map[] = {
-- { P_XO, 0 },
-- { P_SLEEP_CLK, 5 }
--};
--
--static const char * const gcc_xo_sleep_clk[] = {
-- "xo",
-- "sleep_clk"
--};
--
--static const struct parent_map gcc_xo_gpll0_gpll0_early_div_map[] = {
-- { P_XO, 0 },
-- { P_GPLL0, 1 },
-- { P_GPLL0_EARLY_DIV, 6 }
--};
--
--static const char * const gcc_xo_gpll0_gpll0_early_div[] = {
-- "xo",
-- "gpll0",
-- "gpll0_early_div"
--};
--
--static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
-- { P_XO, 0 },
-- { P_GPLL0, 1 },
-- { P_GPLL4, 5 }
--};
--
--static const char * const gcc_xo_gpll0_gpll4[] = {
-- "xo",
-- "gpll0",
-- "gpll4"
--};
--
--static const struct parent_map gcc_xo_gpll0_aud_ref_clk_map[] = {
-- { P_XO, 0 },
-- { P_GPLL0, 1 },
-- { P_AUD_REF_CLK, 2 }
--};
--
--static const char * const gcc_xo_gpll0_aud_ref_clk[] = {
-- "xo",
-- "gpll0",
-- "aud_ref_clk"
--};
--
--static const struct parent_map gcc_xo_gpll0_sleep_clk_gpll0_early_div_map[] = {
-- { P_XO, 0 },
-- { P_GPLL0, 1 },
-- { P_SLEEP_CLK, 5 },
-- { P_GPLL0_EARLY_DIV, 6 }
--};
--
--static const char * const gcc_xo_gpll0_sleep_clk_gpll0_early_div[] = {
-- "xo",
-- "gpll0",
-- "sleep_clk",
-- "gpll0_early_div"
--};
--
--static const struct parent_map gcc_xo_gpll0_gpll4_gpll0_early_div_map[] = {
-- { P_XO, 0 },
-- { P_GPLL0, 1 },
-- { P_GPLL4, 5 },
-- { P_GPLL0_EARLY_DIV, 6 }
--};
--
--static const char * const gcc_xo_gpll0_gpll4_gpll0_early_div[] = {
-- "xo",
-- "gpll0",
-- "gpll4",
-- "gpll0_early_div"
--};
--
- static struct clk_fixed_factor xo = {
- .mult = 1,
- .div = 1,
-@@ -229,6 +137,98 @@ static struct clk_alpha_pll_postdiv gpll4 = {
- },
- };
-
-+static const struct parent_map gcc_sleep_clk_map[] = {
-+ { P_SLEEP_CLK, 5 }
-+};
-+
-+static const char * const gcc_sleep_clk[] = {
-+ "sleep_clk"
-+};
-+
-+static const struct parent_map gcc_xo_gpll0_map[] = {
-+ { P_XO, 0 },
-+ { P_GPLL0, 1 }
-+};
-+
-+static const char * const gcc_xo_gpll0[] = {
-+ "xo",
-+ "gpll0"
-+};
-+
-+static const struct parent_map gcc_xo_sleep_clk_map[] = {
-+ { P_XO, 0 },
-+ { P_SLEEP_CLK, 5 }
-+};
-+
-+static const char * const gcc_xo_sleep_clk[] = {
-+ "xo",
-+ "sleep_clk"
-+};
-+
-+static const struct parent_map gcc_xo_gpll0_gpll0_early_div_map[] = {
-+ { P_XO, 0 },
-+ { P_GPLL0, 1 },
-+ { P_GPLL0_EARLY_DIV, 6 }
-+};
-+
-+static const char * const gcc_xo_gpll0_gpll0_early_div[] = {
-+ "xo",
-+ "gpll0",
-+ "gpll0_early_div"
-+};
-+
-+static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
-+ { P_XO, 0 },
-+ { P_GPLL0, 1 },
-+ { P_GPLL4, 5 }
-+};
-+
-+static const char * const gcc_xo_gpll0_gpll4[] = {
-+ "xo",
-+ "gpll0",
-+ "gpll4"
-+};
-+
-+static const struct parent_map gcc_xo_gpll0_aud_ref_clk_map[] = {
-+ { P_XO, 0 },
-+ { P_GPLL0, 1 },
-+ { P_AUD_REF_CLK, 2 }
-+};
-+
-+static const char * const gcc_xo_gpll0_aud_ref_clk[] = {
-+ "xo",
-+ "gpll0",
-+ "aud_ref_clk"
-+};
-+
-+static const struct parent_map gcc_xo_gpll0_sleep_clk_gpll0_early_div_map[] = {
-+ { P_XO, 0 },
-+ { P_GPLL0, 1 },
-+ { P_SLEEP_CLK, 5 },
-+ { P_GPLL0_EARLY_DIV, 6 }
-+};
-+
-+static const char * const gcc_xo_gpll0_sleep_clk_gpll0_early_div[] = {
-+ "xo",
-+ "gpll0",
-+ "sleep_clk",
-+ "gpll0_early_div"
-+};
-+
-+static const struct parent_map gcc_xo_gpll0_gpll4_gpll0_early_div_map[] = {
-+ { P_XO, 0 },
-+ { P_GPLL0, 1 },
-+ { P_GPLL4, 5 },
-+ { P_GPLL0_EARLY_DIV, 6 }
-+};
-+
-+static const char * const gcc_xo_gpll0_gpll4_gpll0_early_div[] = {
-+ "xo",
-+ "gpll0",
-+ "gpll4",
-+ "gpll0_early_div"
-+};
-+
- static const struct freq_tbl ftbl_system_noc_clk_src[] = {
- F(19200000, P_XO, 1, 0, 0),
- F(50000000, P_GPLL0_EARLY_DIV, 6, 0, 0),
---
-2.42.0
-
+++ /dev/null
-From 6ccd83d3606d1c7bc50f28cda2ebf5be59c53e25 Mon Sep 17 00:00:00 2001
-From: Sasha Levin <sashal@kernel.org>
-Date: Thu, 31 Aug 2023 11:39:14 +0200
-Subject: clk: qcom: gcc-msm8996: Remove RPM bus clocks
-
-From: Konrad Dybcio <konrad.dybcio@linaro.org>
-
-[ Upstream commit 4afda5f6bcdf673ef2556fcfa458daf3a5a648d8 ]
-
-The GCC driver contains clocks that are owned (meaning configured and
-scaled) by the RPM core.
-
-Remove them from Linux to stop interjecting the RPM's logic.
-
-Fixes: b1e010c0730a ("clk: qcom: Add MSM8996 Global Clock Control (GCC) driver")
-Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
-Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-Link: https://lore.kernel.org/r/20230830-topic-rpmbusclocks8996gcc-v1-1-9e99bedcdc3b@linaro.org
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Signed-off-by: Sasha Levin <sashal@kernel.org>
----
- drivers/clk/qcom/gcc-msm8996.c | 237 +--------------------------------
- 1 file changed, 5 insertions(+), 232 deletions(-)
-
-diff --git a/drivers/clk/qcom/gcc-msm8996.c b/drivers/clk/qcom/gcc-msm8996.c
-index 6b36024583b4a..2d79a73da1055 100644
---- a/drivers/clk/qcom/gcc-msm8996.c
-+++ b/drivers/clk/qcom/gcc-msm8996.c
-@@ -245,71 +245,6 @@ static const struct clk_parent_data gcc_xo_gpll0_gpll4_gpll0_early_div[] = {
- { .hw = &gpll0_early_div.hw }
- };
-
--static const struct freq_tbl ftbl_system_noc_clk_src[] = {
-- F(19200000, P_XO, 1, 0, 0),
-- F(50000000, P_GPLL0_EARLY_DIV, 6, 0, 0),
-- F(100000000, P_GPLL0, 6, 0, 0),
-- F(150000000, P_GPLL0, 4, 0, 0),
-- F(200000000, P_GPLL0, 3, 0, 0),
-- F(240000000, P_GPLL0, 2.5, 0, 0),
-- { }
--};
--
--static struct clk_rcg2 system_noc_clk_src = {
-- .cmd_rcgr = 0x0401c,
-- .hid_width = 5,
-- .parent_map = gcc_xo_gpll0_gpll0_early_div_map,
-- .freq_tbl = ftbl_system_noc_clk_src,
-- .clkr.hw.init = &(struct clk_init_data){
-- .name = "system_noc_clk_src",
-- .parent_data = gcc_xo_gpll0_gpll0_early_div,
-- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div),
-- .ops = &clk_rcg2_ops,
-- },
--};
--
--static const struct freq_tbl ftbl_config_noc_clk_src[] = {
-- F(19200000, P_XO, 1, 0, 0),
-- F(37500000, P_GPLL0, 16, 0, 0),
-- F(75000000, P_GPLL0, 8, 0, 0),
-- { }
--};
--
--static struct clk_rcg2 config_noc_clk_src = {
-- .cmd_rcgr = 0x0500c,
-- .hid_width = 5,
-- .parent_map = gcc_xo_gpll0_map,
-- .freq_tbl = ftbl_config_noc_clk_src,
-- .clkr.hw.init = &(struct clk_init_data){
-- .name = "config_noc_clk_src",
-- .parent_data = gcc_xo_gpll0,
-- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
-- .ops = &clk_rcg2_ops,
-- },
--};
--
--static const struct freq_tbl ftbl_periph_noc_clk_src[] = {
-- F(19200000, P_XO, 1, 0, 0),
-- F(37500000, P_GPLL0, 16, 0, 0),
-- F(50000000, P_GPLL0, 12, 0, 0),
-- F(75000000, P_GPLL0, 8, 0, 0),
-- F(100000000, P_GPLL0, 6, 0, 0),
-- { }
--};
--
--static struct clk_rcg2 periph_noc_clk_src = {
-- .cmd_rcgr = 0x06014,
-- .hid_width = 5,
-- .parent_map = gcc_xo_gpll0_map,
-- .freq_tbl = ftbl_periph_noc_clk_src,
-- .clkr.hw.init = &(struct clk_init_data){
-- .name = "periph_noc_clk_src",
-- .parent_data = gcc_xo_gpll0,
-- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
-- .ops = &clk_rcg2_ops,
-- },
--};
--
- static const struct freq_tbl ftbl_usb30_master_clk_src[] = {
- F(19200000, P_XO, 1, 0, 0),
- F(120000000, P_GPLL0, 5, 0, 0),
-@@ -1298,11 +1233,7 @@ static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_mmss_noc_cfg_ahb_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &config_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
-+ .flags = CLK_IGNORE_UNUSED,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -1465,11 +1396,6 @@ static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_usb_phy_cfg_ahb2phy_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &periph_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -1499,11 +1425,6 @@ static struct clk_branch gcc_sdcc1_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_sdcc1_ahb_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &periph_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -1550,11 +1471,6 @@ static struct clk_branch gcc_sdcc2_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_sdcc2_ahb_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &periph_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -1584,11 +1500,6 @@ static struct clk_branch gcc_sdcc3_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_sdcc3_ahb_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &periph_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -1618,11 +1529,6 @@ static struct clk_branch gcc_sdcc4_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_sdcc4_ahb_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &periph_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -1636,11 +1542,6 @@ static struct clk_branch gcc_blsp1_ahb_clk = {
- .enable_mask = BIT(17),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_ahb_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &periph_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -1978,11 +1879,6 @@ static struct clk_branch gcc_blsp2_ahb_clk = {
- .enable_mask = BIT(15),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp2_ahb_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &periph_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -2319,11 +2215,6 @@ static struct clk_branch gcc_pdm_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pdm_ahb_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &periph_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -2354,11 +2245,6 @@ static struct clk_branch gcc_prng_ahb_clk = {
- .enable_mask = BIT(13),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_prng_ahb_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &config_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -2371,11 +2257,6 @@ static struct clk_branch gcc_tsif_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_tsif_ahb_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &periph_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -2423,11 +2304,6 @@ static struct clk_branch gcc_boot_rom_ahb_clk = {
- .enable_mask = BIT(10),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_boot_rom_ahb_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &config_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -2521,11 +2397,6 @@ static struct clk_branch gcc_pcie_0_slv_axi_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie_0_slv_axi_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &system_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -2538,11 +2409,6 @@ static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie_0_mstr_axi_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &system_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -2555,11 +2421,6 @@ static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie_0_cfg_ahb_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &config_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -2607,11 +2468,6 @@ static struct clk_branch gcc_pcie_1_slv_axi_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie_1_slv_axi_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &system_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -2624,11 +2480,6 @@ static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie_1_mstr_axi_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &system_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -2641,11 +2492,6 @@ static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie_1_cfg_ahb_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &config_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -2693,11 +2539,6 @@ static struct clk_branch gcc_pcie_2_slv_axi_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie_2_slv_axi_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &system_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -2710,11 +2551,6 @@ static struct clk_branch gcc_pcie_2_mstr_axi_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie_2_mstr_axi_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &system_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -2727,11 +2563,6 @@ static struct clk_branch gcc_pcie_2_cfg_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie_2_cfg_ahb_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &config_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -2779,11 +2610,6 @@ static struct clk_branch gcc_pcie_phy_cfg_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie_phy_cfg_ahb_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &config_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -2830,11 +2656,6 @@ static struct clk_branch gcc_ufs_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_ufs_ahb_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &config_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -3061,11 +2882,7 @@ static struct clk_branch gcc_aggre0_snoc_axi_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_aggre0_snoc_axi_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &system_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
-+ .flags = CLK_IS_CRITICAL,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -3078,11 +2895,7 @@ static struct clk_branch gcc_aggre0_cnoc_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_aggre0_cnoc_ahb_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &config_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
-+ .flags = CLK_IS_CRITICAL,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -3095,11 +2908,7 @@ static struct clk_branch gcc_smmu_aggre0_axi_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_smmu_aggre0_axi_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &system_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
-+ .flags = CLK_IS_CRITICAL,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -3112,11 +2921,7 @@ static struct clk_branch gcc_smmu_aggre0_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_smmu_aggre0_ahb_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &config_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
-+ .flags = CLK_IS_CRITICAL,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -3163,10 +2968,6 @@ static struct clk_branch gcc_dcc_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_dcc_ahb_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &config_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -3179,10 +2980,6 @@ static struct clk_branch gcc_aggre0_noc_mpu_cfg_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_aggre0_noc_mpu_cfg_ahb_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &config_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -3195,11 +2992,6 @@ static struct clk_branch gcc_qspi_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_qspi_ahb_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &periph_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -3348,10 +3140,6 @@ static struct clk_branch gcc_mss_cfg_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_mss_cfg_ahb_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &config_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -3364,10 +3152,6 @@ static struct clk_branch gcc_mss_mnoc_bimc_axi_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_mss_mnoc_bimc_axi_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &system_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -3380,10 +3164,6 @@ static struct clk_branch gcc_mss_snoc_axi_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_mss_snoc_axi_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &system_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -3396,10 +3176,6 @@ static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_mss_q6_bimc_axi_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &system_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -3495,9 +3271,6 @@ static struct clk_regmap *gcc_msm8996_clocks[] = {
- [GPLL0] = &gpll0.clkr,
- [GPLL4_EARLY] = &gpll4_early.clkr,
- [GPLL4] = &gpll4.clkr,
-- [SYSTEM_NOC_CLK_SRC] = &system_noc_clk_src.clkr,
-- [CONFIG_NOC_CLK_SRC] = &config_noc_clk_src.clkr,
-- [PERIPH_NOC_CLK_SRC] = &periph_noc_clk_src.clkr,
- [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
- [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
- [USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr,
---
-2.42.0
-
+++ /dev/null
-From c4230c7cbbd3a56e1203f942c449d429d0f7e522 Mon Sep 17 00:00:00 2001
-From: Sasha Levin <sashal@kernel.org>
-Date: Tue, 28 Dec 2021 07:54:11 +0300
-Subject: clk: qcom: gcc-msm8996: use ARRAY_SIZE instead of specifying
- num_parents
-
-From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-
-[ Upstream commit ed96df3d461eeb2c40cb06ca5fd51644d0f4a2c0 ]
-
-Use ARRAY_SIZE() instead of manually specifying num_parents. This makes
-adding/removing entries to/from parent_data easy and errorproof.
-
-Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Link: https://lore.kernel.org/r/20211228045415.20543-13-dmitry.baryshkov@linaro.org
-Stable-dep-of: 4afda5f6bcdf ("clk: qcom: gcc-msm8996: Remove RPM bus clocks")
-Signed-off-by: Sasha Levin <sashal@kernel.org>
----
- drivers/clk/qcom/gcc-msm8996.c | 122 ++++++++++++++++-----------------
- 1 file changed, 61 insertions(+), 61 deletions(-)
-
-diff --git a/drivers/clk/qcom/gcc-msm8996.c b/drivers/clk/qcom/gcc-msm8996.c
-index 9b1674b28d45d..d95814025c65e 100644
---- a/drivers/clk/qcom/gcc-msm8996.c
-+++ b/drivers/clk/qcom/gcc-msm8996.c
-@@ -290,7 +290,7 @@ static struct clk_rcg2 system_noc_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "system_noc_clk_src",
- .parent_names = gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div,
-- .num_parents = 7,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -310,7 +310,7 @@ static struct clk_rcg2 config_noc_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "config_noc_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -332,7 +332,7 @@ static struct clk_rcg2 periph_noc_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "periph_noc_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -353,7 +353,7 @@ static struct clk_rcg2 usb30_master_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "usb30_master_clk_src",
- .parent_names = gcc_xo_gpll0_gpll0_early_div,
-- .num_parents = 3,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -371,7 +371,7 @@ static struct clk_rcg2 usb30_mock_utmi_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "usb30_mock_utmi_clk_src",
- .parent_names = gcc_xo_gpll0_gpll0_early_div,
-- .num_parents = 3,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -389,7 +389,7 @@ static struct clk_rcg2 usb3_phy_aux_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "usb3_phy_aux_clk_src",
- .parent_names = gcc_xo_sleep_clk,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_sleep_clk),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -408,7 +408,7 @@ static struct clk_rcg2 usb20_master_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "usb20_master_clk_src",
- .parent_names = gcc_xo_gpll0_gpll0_early_div,
-- .num_parents = 3,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -421,7 +421,7 @@ static struct clk_rcg2 usb20_mock_utmi_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "usb20_mock_utmi_clk_src",
- .parent_names = gcc_xo_gpll0_gpll0_early_div,
-- .num_parents = 3,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -447,7 +447,7 @@ static struct clk_rcg2 sdcc1_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "sdcc1_apps_clk_src",
- .parent_names = gcc_xo_gpll0_gpll4_gpll0_early_div,
-- .num_parents = 4,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_gpll0_early_div),
- .ops = &clk_rcg2_floor_ops,
- },
- };
-@@ -467,7 +467,7 @@ static struct clk_rcg2 sdcc1_ice_core_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "sdcc1_ice_core_clk_src",
- .parent_names = gcc_xo_gpll0_gpll4_gpll0_early_div,
-- .num_parents = 4,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_gpll0_early_div),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -492,7 +492,7 @@ static struct clk_rcg2 sdcc2_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "sdcc2_apps_clk_src",
- .parent_names = gcc_xo_gpll0_gpll4,
-- .num_parents = 3,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
- .ops = &clk_rcg2_floor_ops,
- },
- };
-@@ -506,7 +506,7 @@ static struct clk_rcg2 sdcc3_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "sdcc3_apps_clk_src",
- .parent_names = gcc_xo_gpll0_gpll4,
-- .num_parents = 3,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
- .ops = &clk_rcg2_floor_ops,
- },
- };
-@@ -530,7 +530,7 @@ static struct clk_rcg2 sdcc4_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "sdcc4_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_floor_ops,
- },
- };
-@@ -555,7 +555,7 @@ static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup1_spi_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -574,7 +574,7 @@ static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup1_i2c_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -607,7 +607,7 @@ static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_uart1_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -621,7 +621,7 @@ static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup2_spi_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -634,7 +634,7 @@ static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup2_i2c_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -648,7 +648,7 @@ static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_uart2_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -662,7 +662,7 @@ static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup3_spi_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -675,7 +675,7 @@ static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup3_i2c_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -689,7 +689,7 @@ static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_uart3_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -703,7 +703,7 @@ static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup4_spi_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -716,7 +716,7 @@ static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup4_i2c_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -730,7 +730,7 @@ static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_uart4_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -744,7 +744,7 @@ static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup5_spi_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -757,7 +757,7 @@ static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup5_i2c_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -771,7 +771,7 @@ static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_uart5_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -785,7 +785,7 @@ static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup6_spi_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -798,7 +798,7 @@ static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup6_i2c_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -812,7 +812,7 @@ static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_uart6_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -826,7 +826,7 @@ static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_qup1_spi_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -839,7 +839,7 @@ static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_qup1_i2c_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -853,7 +853,7 @@ static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_uart1_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -867,7 +867,7 @@ static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_qup2_spi_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -880,7 +880,7 @@ static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_qup2_i2c_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -894,7 +894,7 @@ static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_uart2_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -908,7 +908,7 @@ static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_qup3_spi_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -921,7 +921,7 @@ static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_qup3_i2c_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -935,7 +935,7 @@ static struct clk_rcg2 blsp2_uart3_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_uart3_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -949,7 +949,7 @@ static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_qup4_spi_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -962,7 +962,7 @@ static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_qup4_i2c_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -976,7 +976,7 @@ static struct clk_rcg2 blsp2_uart4_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_uart4_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -990,7 +990,7 @@ static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_qup5_spi_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1003,7 +1003,7 @@ static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_qup5_i2c_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1017,7 +1017,7 @@ static struct clk_rcg2 blsp2_uart5_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_uart5_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1031,7 +1031,7 @@ static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_qup6_spi_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1044,7 +1044,7 @@ static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_qup6_i2c_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1058,7 +1058,7 @@ static struct clk_rcg2 blsp2_uart6_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_uart6_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1076,7 +1076,7 @@ static struct clk_rcg2 pdm2_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "pdm2_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1095,7 +1095,7 @@ static struct clk_rcg2 tsif_ref_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "tsif_ref_clk_src",
- .parent_names = gcc_xo_gpll0_aud_ref_clk,
-- .num_parents = 3,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_aud_ref_clk),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1107,7 +1107,7 @@ static struct clk_rcg2 gcc_sleep_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "gcc_sleep_clk_src",
- .parent_names = gcc_sleep_clk,
-- .num_parents = 1,
-+ .num_parents = ARRAY_SIZE(gcc_sleep_clk),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1120,7 +1120,7 @@ static struct clk_rcg2 hmss_rbcpr_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "hmss_rbcpr_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1132,7 +1132,7 @@ static struct clk_rcg2 hmss_gpll0_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "hmss_gpll0_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1153,7 +1153,7 @@ static struct clk_rcg2 gp1_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "gp1_clk_src",
- .parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
-- .num_parents = 4,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk_gpll0_early_div),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1167,7 +1167,7 @@ static struct clk_rcg2 gp2_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "gp2_clk_src",
- .parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
-- .num_parents = 4,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk_gpll0_early_div),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1181,7 +1181,7 @@ static struct clk_rcg2 gp3_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "gp3_clk_src",
- .parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
-- .num_parents = 4,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk_gpll0_early_div),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1200,7 +1200,7 @@ static struct clk_rcg2 pcie_aux_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "pcie_aux_clk_src",
- .parent_names = gcc_xo_sleep_clk,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_sleep_clk),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1221,7 +1221,7 @@ static struct clk_rcg2 ufs_axi_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "ufs_axi_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1241,7 +1241,7 @@ static struct clk_rcg2 ufs_ice_core_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "ufs_ice_core_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1262,7 +1262,7 @@ static struct clk_rcg2 qspi_ser_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "qspi_ser_clk_src",
- .parent_names = gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div,
-- .num_parents = 6,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div),
- .ops = &clk_rcg2_ops,
- },
- };
---
-2.42.0
-
+++ /dev/null
-From 53f0f100154c9d71ca6b983b88fa6a71330270c6 Mon Sep 17 00:00:00 2001
-From: Sasha Levin <sashal@kernel.org>
-Date: Tue, 28 Dec 2021 07:54:14 +0300
-Subject: clk: qcom: gcc-msm8996: use parent_hws/_data instead of parent_names
-
-From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-
-[ Upstream commit b3867679d460d67aaef5aa76e4512197a5375514 ]
-
-Convert the clock driver to specify parent data rather than parent
-names, to actually bind using 'clock-names' specified in the DTS rather
-than global clock names. Use parent_hws where possible to refer parent
-clocks directly, skipping the lookup.
-
-Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Link: https://lore.kernel.org/r/20211228045415.20543-16-dmitry.baryshkov@linaro.org
-Stable-dep-of: 4afda5f6bcdf ("clk: qcom: gcc-msm8996: Remove RPM bus clocks")
-Signed-off-by: Sasha Levin <sashal@kernel.org>
----
- drivers/clk/qcom/gcc-msm8996.c | 678 ++++++++++++++++++++++-----------
- 1 file changed, 463 insertions(+), 215 deletions(-)
-
-diff --git a/drivers/clk/qcom/gcc-msm8996.c b/drivers/clk/qcom/gcc-msm8996.c
-index 8531f2f3665fe..6b36024583b4a 100644
---- a/drivers/clk/qcom/gcc-msm8996.c
-+++ b/drivers/clk/qcom/gcc-msm8996.c
-@@ -38,7 +38,9 @@ static struct clk_fixed_factor xo = {
- .div = 1,
- .hw.init = &(struct clk_init_data){
- .name = "xo",
-- .parent_names = (const char *[]){ "xo_board" },
-+ .parent_data = &(const struct clk_parent_data){
-+ .fw_name = "cxo", .name = "xo_board",
-+ },
- .num_parents = 1,
- .ops = &clk_fixed_factor_ops,
- },
-@@ -52,7 +54,9 @@ static struct clk_alpha_pll gpll0_early = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gpll0_early",
-- .parent_names = (const char *[]){ "xo" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &xo.hw,
-+ },
- .num_parents = 1,
- .ops = &clk_alpha_pll_ops,
- },
-@@ -64,7 +68,9 @@ static struct clk_fixed_factor gpll0_early_div = {
- .div = 2,
- .hw.init = &(struct clk_init_data){
- .name = "gpll0_early_div",
-- .parent_names = (const char *[]){ "gpll0_early" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &gpll0_early.clkr.hw,
-+ },
- .num_parents = 1,
- .ops = &clk_fixed_factor_ops,
- },
-@@ -75,7 +81,9 @@ static struct clk_alpha_pll_postdiv gpll0 = {
- .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
- .clkr.hw.init = &(struct clk_init_data){
- .name = "gpll0",
-- .parent_names = (const char *[]){ "gpll0_early" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &gpll0_early.clkr.hw,
-+ },
- .num_parents = 1,
- .ops = &clk_alpha_pll_postdiv_ops,
- },
-@@ -88,7 +96,9 @@ static struct clk_branch gcc_mmss_gpll0_div_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_mmss_gpll0_div_clk",
-- .parent_names = (const char *[]){ "gpll0" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &gpll0.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -103,7 +113,9 @@ static struct clk_branch gcc_mss_gpll0_div_clk = {
- .enable_mask = BIT(2),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_mss_gpll0_div_clk",
-- .parent_names = (const char *[]){ "gpll0" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &gpll0.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops
-@@ -119,7 +131,9 @@ static struct clk_alpha_pll gpll4_early = {
- .enable_mask = BIT(4),
- .hw.init = &(struct clk_init_data){
- .name = "gpll4_early",
-- .parent_names = (const char *[]){ "xo" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &xo.hw,
-+ },
- .num_parents = 1,
- .ops = &clk_alpha_pll_ops,
- },
-@@ -131,7 +145,9 @@ static struct clk_alpha_pll_postdiv gpll4 = {
- .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
- .clkr.hw.init = &(struct clk_init_data){
- .name = "gpll4",
-- .parent_names = (const char *[]){ "gpll4_early" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &gpll4_early.clkr.hw,
-+ },
- .num_parents = 1,
- .ops = &clk_alpha_pll_postdiv_ops,
- },
-@@ -141,8 +157,8 @@ static const struct parent_map gcc_sleep_clk_map[] = {
- { P_SLEEP_CLK, 5 }
- };
-
--static const char * const gcc_sleep_clk[] = {
-- "sleep_clk"
-+static const struct clk_parent_data gcc_sleep_clk[] = {
-+ { .fw_name = "sleep_clk", .name = "sleep_clk" }
- };
-
- static const struct parent_map gcc_xo_gpll0_map[] = {
-@@ -150,9 +166,9 @@ static const struct parent_map gcc_xo_gpll0_map[] = {
- { P_GPLL0, 1 }
- };
-
--static const char * const gcc_xo_gpll0[] = {
-- "xo",
-- "gpll0"
-+static const struct clk_parent_data gcc_xo_gpll0[] = {
-+ { .hw = &xo.hw },
-+ { .hw = &gpll0.clkr.hw }
- };
-
- static const struct parent_map gcc_xo_sleep_clk_map[] = {
-@@ -160,9 +176,9 @@ static const struct parent_map gcc_xo_sleep_clk_map[] = {
- { P_SLEEP_CLK, 5 }
- };
-
--static const char * const gcc_xo_sleep_clk[] = {
-- "xo",
-- "sleep_clk"
-+static const struct clk_parent_data gcc_xo_sleep_clk[] = {
-+ { .hw = &xo.hw },
-+ { .fw_name = "sleep_clk", .name = "sleep_clk" }
- };
-
- static const struct parent_map gcc_xo_gpll0_gpll0_early_div_map[] = {
-@@ -171,10 +187,10 @@ static const struct parent_map gcc_xo_gpll0_gpll0_early_div_map[] = {
- { P_GPLL0_EARLY_DIV, 6 }
- };
-
--static const char * const gcc_xo_gpll0_gpll0_early_div[] = {
-- "xo",
-- "gpll0",
-- "gpll0_early_div"
-+static const struct clk_parent_data gcc_xo_gpll0_gpll0_early_div[] = {
-+ { .hw = &xo.hw },
-+ { .hw = &gpll0.clkr.hw },
-+ { .hw = &gpll0_early_div.hw }
- };
-
- static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
-@@ -183,10 +199,10 @@ static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
- { P_GPLL4, 5 }
- };
-
--static const char * const gcc_xo_gpll0_gpll4[] = {
-- "xo",
-- "gpll0",
-- "gpll4"
-+static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = {
-+ { .hw = &xo.hw },
-+ { .hw = &gpll0.clkr.hw },
-+ { .hw = &gpll4.clkr.hw }
- };
-
- static const struct parent_map gcc_xo_gpll0_aud_ref_clk_map[] = {
-@@ -195,10 +211,10 @@ static const struct parent_map gcc_xo_gpll0_aud_ref_clk_map[] = {
- { P_AUD_REF_CLK, 2 }
- };
-
--static const char * const gcc_xo_gpll0_aud_ref_clk[] = {
-- "xo",
-- "gpll0",
-- "aud_ref_clk"
-+static const struct clk_parent_data gcc_xo_gpll0_aud_ref_clk[] = {
-+ { .hw = &xo.hw },
-+ { .hw = &gpll0.clkr.hw },
-+ { .fw_name = "aud_ref_clk", .name = "aud_ref_clk" }
- };
-
- static const struct parent_map gcc_xo_gpll0_sleep_clk_gpll0_early_div_map[] = {
-@@ -208,11 +224,11 @@ static const struct parent_map gcc_xo_gpll0_sleep_clk_gpll0_early_div_map[] = {
- { P_GPLL0_EARLY_DIV, 6 }
- };
-
--static const char * const gcc_xo_gpll0_sleep_clk_gpll0_early_div[] = {
-- "xo",
-- "gpll0",
-- "sleep_clk",
-- "gpll0_early_div"
-+static const struct clk_parent_data gcc_xo_gpll0_sleep_clk_gpll0_early_div[] = {
-+ { .hw = &xo.hw },
-+ { .hw = &gpll0.clkr.hw },
-+ { .fw_name = "sleep_clk", .name = "sleep_clk" },
-+ { .hw = &gpll0_early_div.hw }
- };
-
- static const struct parent_map gcc_xo_gpll0_gpll4_gpll0_early_div_map[] = {
-@@ -222,11 +238,11 @@ static const struct parent_map gcc_xo_gpll0_gpll4_gpll0_early_div_map[] = {
- { P_GPLL0_EARLY_DIV, 6 }
- };
-
--static const char * const gcc_xo_gpll0_gpll4_gpll0_early_div[] = {
-- "xo",
-- "gpll0",
-- "gpll4",
-- "gpll0_early_div"
-+static const struct clk_parent_data gcc_xo_gpll0_gpll4_gpll0_early_div[] = {
-+ { .hw = &xo.hw },
-+ { .hw = &gpll0.clkr.hw },
-+ { .hw = &gpll4.clkr.hw },
-+ { .hw = &gpll0_early_div.hw }
- };
-
- static const struct freq_tbl ftbl_system_noc_clk_src[] = {
-@@ -246,7 +262,7 @@ static struct clk_rcg2 system_noc_clk_src = {
- .freq_tbl = ftbl_system_noc_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "system_noc_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll0_early_div,
-+ .parent_data = gcc_xo_gpll0_gpll0_early_div,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div),
- .ops = &clk_rcg2_ops,
- },
-@@ -266,7 +282,7 @@ static struct clk_rcg2 config_noc_clk_src = {
- .freq_tbl = ftbl_config_noc_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "config_noc_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -288,7 +304,7 @@ static struct clk_rcg2 periph_noc_clk_src = {
- .freq_tbl = ftbl_periph_noc_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "periph_noc_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -309,7 +325,7 @@ static struct clk_rcg2 usb30_master_clk_src = {
- .freq_tbl = ftbl_usb30_master_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "usb30_master_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll0_early_div,
-+ .parent_data = gcc_xo_gpll0_gpll0_early_div,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div),
- .ops = &clk_rcg2_ops,
- },
-@@ -327,7 +343,7 @@ static struct clk_rcg2 usb30_mock_utmi_clk_src = {
- .freq_tbl = ftbl_usb30_mock_utmi_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "usb30_mock_utmi_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll0_early_div,
-+ .parent_data = gcc_xo_gpll0_gpll0_early_div,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div),
- .ops = &clk_rcg2_ops,
- },
-@@ -345,7 +361,7 @@ static struct clk_rcg2 usb3_phy_aux_clk_src = {
- .freq_tbl = ftbl_usb3_phy_aux_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "usb3_phy_aux_clk_src",
-- .parent_names = gcc_xo_sleep_clk,
-+ .parent_data = gcc_xo_sleep_clk,
- .num_parents = ARRAY_SIZE(gcc_xo_sleep_clk),
- .ops = &clk_rcg2_ops,
- },
-@@ -364,7 +380,7 @@ static struct clk_rcg2 usb20_master_clk_src = {
- .freq_tbl = ftbl_usb20_master_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "usb20_master_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll0_early_div,
-+ .parent_data = gcc_xo_gpll0_gpll0_early_div,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div),
- .ops = &clk_rcg2_ops,
- },
-@@ -377,7 +393,7 @@ static struct clk_rcg2 usb20_mock_utmi_clk_src = {
- .freq_tbl = ftbl_usb30_mock_utmi_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "usb20_mock_utmi_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll0_early_div,
-+ .parent_data = gcc_xo_gpll0_gpll0_early_div,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div),
- .ops = &clk_rcg2_ops,
- },
-@@ -403,7 +419,7 @@ static struct clk_rcg2 sdcc1_apps_clk_src = {
- .freq_tbl = ftbl_sdcc1_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "sdcc1_apps_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll4_gpll0_early_div,
-+ .parent_data = gcc_xo_gpll0_gpll4_gpll0_early_div,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_gpll0_early_div),
- .ops = &clk_rcg2_floor_ops,
- },
-@@ -423,7 +439,7 @@ static struct clk_rcg2 sdcc1_ice_core_clk_src = {
- .freq_tbl = ftbl_sdcc1_ice_core_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "sdcc1_ice_core_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll4_gpll0_early_div,
-+ .parent_data = gcc_xo_gpll0_gpll4_gpll0_early_div,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_gpll0_early_div),
- .ops = &clk_rcg2_ops,
- },
-@@ -448,7 +464,7 @@ static struct clk_rcg2 sdcc2_apps_clk_src = {
- .freq_tbl = ftbl_sdcc2_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "sdcc2_apps_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll4,
-+ .parent_data = gcc_xo_gpll0_gpll4,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
- .ops = &clk_rcg2_floor_ops,
- },
-@@ -462,7 +478,7 @@ static struct clk_rcg2 sdcc3_apps_clk_src = {
- .freq_tbl = ftbl_sdcc2_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "sdcc3_apps_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll4,
-+ .parent_data = gcc_xo_gpll0_gpll4,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
- .ops = &clk_rcg2_floor_ops,
- },
-@@ -486,7 +502,7 @@ static struct clk_rcg2 sdcc4_apps_clk_src = {
- .freq_tbl = ftbl_sdcc4_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "sdcc4_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_floor_ops,
- },
-@@ -511,7 +527,7 @@ static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup1_spi_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -530,7 +546,7 @@ static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup1_i2c_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -563,7 +579,7 @@ static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_uart1_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -577,7 +593,7 @@ static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup2_spi_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -590,7 +606,7 @@ static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup2_i2c_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -604,7 +620,7 @@ static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_uart2_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -618,7 +634,7 @@ static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup3_spi_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -631,7 +647,7 @@ static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup3_i2c_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -645,7 +661,7 @@ static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_uart3_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -659,7 +675,7 @@ static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup4_spi_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -672,7 +688,7 @@ static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup4_i2c_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -686,7 +702,7 @@ static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_uart4_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -700,7 +716,7 @@ static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup5_spi_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -713,7 +729,7 @@ static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup5_i2c_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -727,7 +743,7 @@ static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_uart5_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -741,7 +757,7 @@ static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup6_spi_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -754,7 +770,7 @@ static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup6_i2c_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -768,7 +784,7 @@ static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_uart6_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -782,7 +798,7 @@ static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_qup1_spi_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -795,7 +811,7 @@ static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_qup1_i2c_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -809,7 +825,7 @@ static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_uart1_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -823,7 +839,7 @@ static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_qup2_spi_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -836,7 +852,7 @@ static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_qup2_i2c_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -850,7 +866,7 @@ static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_uart2_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -864,7 +880,7 @@ static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_qup3_spi_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -877,7 +893,7 @@ static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_qup3_i2c_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -891,7 +907,7 @@ static struct clk_rcg2 blsp2_uart3_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_uart3_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -905,7 +921,7 @@ static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_qup4_spi_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -918,7 +934,7 @@ static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_qup4_i2c_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -932,7 +948,7 @@ static struct clk_rcg2 blsp2_uart4_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_uart4_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -946,7 +962,7 @@ static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_qup5_spi_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -959,7 +975,7 @@ static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_qup5_i2c_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -973,7 +989,7 @@ static struct clk_rcg2 blsp2_uart5_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_uart5_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -987,7 +1003,7 @@ static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_qup6_spi_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -1000,7 +1016,7 @@ static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_qup6_i2c_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -1014,7 +1030,7 @@ static struct clk_rcg2 blsp2_uart6_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_uart6_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -1032,7 +1048,7 @@ static struct clk_rcg2 pdm2_clk_src = {
- .freq_tbl = ftbl_pdm2_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "pdm2_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -1051,7 +1067,7 @@ static struct clk_rcg2 tsif_ref_clk_src = {
- .freq_tbl = ftbl_tsif_ref_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "tsif_ref_clk_src",
-- .parent_names = gcc_xo_gpll0_aud_ref_clk,
-+ .parent_data = gcc_xo_gpll0_aud_ref_clk,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_aud_ref_clk),
- .ops = &clk_rcg2_ops,
- },
-@@ -1063,7 +1079,7 @@ static struct clk_rcg2 gcc_sleep_clk_src = {
- .parent_map = gcc_sleep_clk_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "gcc_sleep_clk_src",
-- .parent_names = gcc_sleep_clk,
-+ .parent_data = gcc_sleep_clk,
- .num_parents = ARRAY_SIZE(gcc_sleep_clk),
- .ops = &clk_rcg2_ops,
- },
-@@ -1076,7 +1092,7 @@ static struct clk_rcg2 hmss_rbcpr_clk_src = {
- .freq_tbl = ftbl_usb30_mock_utmi_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "hmss_rbcpr_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -1088,7 +1104,7 @@ static struct clk_rcg2 hmss_gpll0_clk_src = {
- .parent_map = gcc_xo_gpll0_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "hmss_gpll0_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -1109,7 +1125,7 @@ static struct clk_rcg2 gp1_clk_src = {
- .freq_tbl = ftbl_gp1_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "gp1_clk_src",
-- .parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
-+ .parent_data = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk_gpll0_early_div),
- .ops = &clk_rcg2_ops,
- },
-@@ -1123,7 +1139,7 @@ static struct clk_rcg2 gp2_clk_src = {
- .freq_tbl = ftbl_gp1_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "gp2_clk_src",
-- .parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
-+ .parent_data = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk_gpll0_early_div),
- .ops = &clk_rcg2_ops,
- },
-@@ -1137,7 +1153,7 @@ static struct clk_rcg2 gp3_clk_src = {
- .freq_tbl = ftbl_gp1_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "gp3_clk_src",
-- .parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
-+ .parent_data = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk_gpll0_early_div),
- .ops = &clk_rcg2_ops,
- },
-@@ -1156,7 +1172,7 @@ static struct clk_rcg2 pcie_aux_clk_src = {
- .freq_tbl = ftbl_pcie_aux_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "pcie_aux_clk_src",
-- .parent_names = gcc_xo_sleep_clk,
-+ .parent_data = gcc_xo_sleep_clk,
- .num_parents = ARRAY_SIZE(gcc_xo_sleep_clk),
- .ops = &clk_rcg2_ops,
- },
-@@ -1177,7 +1193,7 @@ static struct clk_rcg2 ufs_axi_clk_src = {
- .freq_tbl = ftbl_ufs_axi_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "ufs_axi_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -1197,7 +1213,7 @@ static struct clk_rcg2 ufs_ice_core_clk_src = {
- .freq_tbl = ftbl_ufs_ice_core_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "ufs_ice_core_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -1218,7 +1234,7 @@ static struct clk_rcg2 qspi_ser_clk_src = {
- .freq_tbl = ftbl_qspi_ser_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "qspi_ser_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll4_gpll0_early_div,
-+ .parent_data = gcc_xo_gpll0_gpll4_gpll0_early_div,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_gpll0_early_div),
- .ops = &clk_rcg2_ops,
- },
-@@ -1231,7 +1247,9 @@ static struct clk_branch gcc_sys_noc_usb3_axi_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_sys_noc_usb3_axi_clk",
-- .parent_names = (const char *[]){ "usb30_master_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &usb30_master_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1246,7 +1264,9 @@ static struct clk_branch gcc_sys_noc_ufs_axi_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_sys_noc_ufs_axi_clk",
-- .parent_names = (const char *[]){ "ufs_axi_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &ufs_axi_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1261,7 +1281,9 @@ static struct clk_branch gcc_periph_noc_usb20_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_periph_noc_usb20_ahb_clk",
-- .parent_names = (const char *[]){ "usb20_master_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &usb20_master_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1276,7 +1298,9 @@ static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_mmss_noc_cfg_ahb_clk",
-- .parent_names = (const char *[]){ "config_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &config_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
- .ops = &clk_branch2_ops,
-@@ -1304,7 +1328,9 @@ static struct clk_branch gcc_usb30_master_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_usb30_master_clk",
-- .parent_names = (const char *[]){ "usb30_master_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &usb30_master_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1319,7 +1345,9 @@ static struct clk_branch gcc_usb30_sleep_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_usb30_sleep_clk",
-- .parent_names = (const char *[]){ "gcc_sleep_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &gcc_sleep_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1334,7 +1362,9 @@ static struct clk_branch gcc_usb30_mock_utmi_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_usb30_mock_utmi_clk",
-- .parent_names = (const char *[]){ "usb30_mock_utmi_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &usb30_mock_utmi_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1349,7 +1379,9 @@ static struct clk_branch gcc_usb3_phy_aux_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_usb3_phy_aux_clk",
-- .parent_names = (const char *[]){ "usb3_phy_aux_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &usb3_phy_aux_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1365,7 +1397,9 @@ static struct clk_branch gcc_usb3_phy_pipe_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_usb3_phy_pipe_clk",
-- .parent_names = (const char *[]){ "usb3_phy_pipe_clk_src" },
-+ .parent_data = &(const struct clk_parent_data){
-+ .fw_name = "usb3_phy_pipe_clk_src", .name = "usb3_phy_pipe_clk_src",
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1380,7 +1414,9 @@ static struct clk_branch gcc_usb20_master_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_usb20_master_clk",
-- .parent_names = (const char *[]){ "usb20_master_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &usb20_master_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1395,7 +1431,9 @@ static struct clk_branch gcc_usb20_sleep_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_usb20_sleep_clk",
-- .parent_names = (const char *[]){ "gcc_sleep_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &gcc_sleep_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1410,7 +1448,9 @@ static struct clk_branch gcc_usb20_mock_utmi_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_usb20_mock_utmi_clk",
-- .parent_names = (const char *[]){ "usb20_mock_utmi_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &usb20_mock_utmi_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1425,7 +1465,9 @@ static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_usb_phy_cfg_ahb2phy_clk",
-- .parent_names = (const char *[]){ "periph_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &periph_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1440,7 +1482,9 @@ static struct clk_branch gcc_sdcc1_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_sdcc1_apps_clk",
-- .parent_names = (const char *[]){ "sdcc1_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &sdcc1_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1455,7 +1499,9 @@ static struct clk_branch gcc_sdcc1_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_sdcc1_ahb_clk",
-- .parent_names = (const char *[]){ "periph_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &periph_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1470,7 +1516,9 @@ static struct clk_branch gcc_sdcc1_ice_core_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_sdcc1_ice_core_clk",
-- .parent_names = (const char *[]){ "sdcc1_ice_core_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &sdcc1_ice_core_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1485,7 +1533,9 @@ static struct clk_branch gcc_sdcc2_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_sdcc2_apps_clk",
-- .parent_names = (const char *[]){ "sdcc2_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &sdcc2_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1500,7 +1550,9 @@ static struct clk_branch gcc_sdcc2_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_sdcc2_ahb_clk",
-- .parent_names = (const char *[]){ "periph_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &periph_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1515,7 +1567,9 @@ static struct clk_branch gcc_sdcc3_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_sdcc3_apps_clk",
-- .parent_names = (const char *[]){ "sdcc3_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &sdcc3_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1530,7 +1584,9 @@ static struct clk_branch gcc_sdcc3_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_sdcc3_ahb_clk",
-- .parent_names = (const char *[]){ "periph_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &periph_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1545,7 +1601,9 @@ static struct clk_branch gcc_sdcc4_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_sdcc4_apps_clk",
-- .parent_names = (const char *[]){ "sdcc4_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &sdcc4_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1560,7 +1618,9 @@ static struct clk_branch gcc_sdcc4_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_sdcc4_ahb_clk",
-- .parent_names = (const char *[]){ "periph_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &periph_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1576,7 +1636,9 @@ static struct clk_branch gcc_blsp1_ahb_clk = {
- .enable_mask = BIT(17),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_ahb_clk",
-- .parent_names = (const char *[]){ "periph_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &periph_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1592,7 +1654,9 @@ static struct clk_branch gcc_blsp1_sleep_clk = {
- .enable_mask = BIT(16),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_sleep_clk",
-- .parent_names = (const char *[]){ "gcc_sleep_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &gcc_sleep_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1607,7 +1671,9 @@ static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_qup1_spi_apps_clk",
-- .parent_names = (const char *[]){ "blsp1_qup1_spi_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp1_qup1_spi_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1622,7 +1688,9 @@ static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_qup1_i2c_apps_clk",
-- .parent_names = (const char *[]){ "blsp1_qup1_i2c_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp1_qup1_i2c_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1637,7 +1705,9 @@ static struct clk_branch gcc_blsp1_uart1_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_uart1_apps_clk",
-- .parent_names = (const char *[]){ "blsp1_uart1_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp1_uart1_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1652,7 +1722,9 @@ static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_qup2_spi_apps_clk",
-- .parent_names = (const char *[]){ "blsp1_qup2_spi_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp1_qup2_spi_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1667,7 +1739,9 @@ static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_qup2_i2c_apps_clk",
-- .parent_names = (const char *[]){ "blsp1_qup2_i2c_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp1_qup2_i2c_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1682,7 +1756,9 @@ static struct clk_branch gcc_blsp1_uart2_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_uart2_apps_clk",
-- .parent_names = (const char *[]){ "blsp1_uart2_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp1_uart2_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1697,7 +1773,9 @@ static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_qup3_spi_apps_clk",
-- .parent_names = (const char *[]){ "blsp1_qup3_spi_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp1_qup3_spi_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1712,7 +1790,9 @@ static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_qup3_i2c_apps_clk",
-- .parent_names = (const char *[]){ "blsp1_qup3_i2c_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp1_qup3_i2c_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1727,7 +1807,9 @@ static struct clk_branch gcc_blsp1_uart3_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_uart3_apps_clk",
-- .parent_names = (const char *[]){ "blsp1_uart3_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp1_uart3_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1742,7 +1824,9 @@ static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_qup4_spi_apps_clk",
-- .parent_names = (const char *[]){ "blsp1_qup4_spi_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp1_qup4_spi_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1757,7 +1841,9 @@ static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_qup4_i2c_apps_clk",
-- .parent_names = (const char *[]){ "blsp1_qup4_i2c_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp1_qup4_i2c_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1772,7 +1858,9 @@ static struct clk_branch gcc_blsp1_uart4_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_uart4_apps_clk",
-- .parent_names = (const char *[]){ "blsp1_uart4_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp1_uart4_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1787,7 +1875,9 @@ static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_qup5_spi_apps_clk",
-- .parent_names = (const char *[]){ "blsp1_qup5_spi_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp1_qup5_spi_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1802,7 +1892,9 @@ static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_qup5_i2c_apps_clk",
-- .parent_names = (const char *[]){ "blsp1_qup5_i2c_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp1_qup5_i2c_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1817,7 +1909,9 @@ static struct clk_branch gcc_blsp1_uart5_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_uart5_apps_clk",
-- .parent_names = (const char *[]){ "blsp1_uart5_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp1_uart5_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1832,7 +1926,9 @@ static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_qup6_spi_apps_clk",
-- .parent_names = (const char *[]){ "blsp1_qup6_spi_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp1_qup6_spi_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1847,7 +1943,9 @@ static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_qup6_i2c_apps_clk",
-- .parent_names = (const char *[]){ "blsp1_qup6_i2c_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp1_qup6_i2c_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1862,7 +1960,9 @@ static struct clk_branch gcc_blsp1_uart6_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_uart6_apps_clk",
-- .parent_names = (const char *[]){ "blsp1_uart6_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp1_uart6_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1878,7 +1978,9 @@ static struct clk_branch gcc_blsp2_ahb_clk = {
- .enable_mask = BIT(15),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp2_ahb_clk",
-- .parent_names = (const char *[]){ "periph_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &periph_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1894,7 +1996,9 @@ static struct clk_branch gcc_blsp2_sleep_clk = {
- .enable_mask = BIT(14),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp2_sleep_clk",
-- .parent_names = (const char *[]){ "gcc_sleep_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &gcc_sleep_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1909,7 +2013,9 @@ static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp2_qup1_spi_apps_clk",
-- .parent_names = (const char *[]){ "blsp2_qup1_spi_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp2_qup1_spi_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1924,7 +2030,9 @@ static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp2_qup1_i2c_apps_clk",
-- .parent_names = (const char *[]){ "blsp2_qup1_i2c_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp2_qup1_i2c_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1939,7 +2047,9 @@ static struct clk_branch gcc_blsp2_uart1_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp2_uart1_apps_clk",
-- .parent_names = (const char *[]){ "blsp2_uart1_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp2_uart1_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1954,7 +2064,9 @@ static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp2_qup2_spi_apps_clk",
-- .parent_names = (const char *[]){ "blsp2_qup2_spi_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp2_qup2_spi_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1969,7 +2081,9 @@ static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp2_qup2_i2c_apps_clk",
-- .parent_names = (const char *[]){ "blsp2_qup2_i2c_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp2_qup2_i2c_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1984,7 +2098,9 @@ static struct clk_branch gcc_blsp2_uart2_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp2_uart2_apps_clk",
-- .parent_names = (const char *[]){ "blsp2_uart2_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp2_uart2_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1999,7 +2115,9 @@ static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp2_qup3_spi_apps_clk",
-- .parent_names = (const char *[]){ "blsp2_qup3_spi_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp2_qup3_spi_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2014,7 +2132,9 @@ static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp2_qup3_i2c_apps_clk",
-- .parent_names = (const char *[]){ "blsp2_qup3_i2c_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp2_qup3_i2c_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2029,7 +2149,9 @@ static struct clk_branch gcc_blsp2_uart3_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp2_uart3_apps_clk",
-- .parent_names = (const char *[]){ "blsp2_uart3_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp2_uart3_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2044,7 +2166,9 @@ static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp2_qup4_spi_apps_clk",
-- .parent_names = (const char *[]){ "blsp2_qup4_spi_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp2_qup4_spi_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2059,7 +2183,9 @@ static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp2_qup4_i2c_apps_clk",
-- .parent_names = (const char *[]){ "blsp2_qup4_i2c_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp2_qup4_i2c_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2074,7 +2200,9 @@ static struct clk_branch gcc_blsp2_uart4_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp2_uart4_apps_clk",
-- .parent_names = (const char *[]){ "blsp2_uart4_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp2_uart4_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2089,7 +2217,9 @@ static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp2_qup5_spi_apps_clk",
-- .parent_names = (const char *[]){ "blsp2_qup5_spi_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp2_qup5_spi_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2104,7 +2234,9 @@ static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp2_qup5_i2c_apps_clk",
-- .parent_names = (const char *[]){ "blsp2_qup5_i2c_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp2_qup5_i2c_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2119,7 +2251,9 @@ static struct clk_branch gcc_blsp2_uart5_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp2_uart5_apps_clk",
-- .parent_names = (const char *[]){ "blsp2_uart5_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp2_uart5_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2134,7 +2268,9 @@ static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp2_qup6_spi_apps_clk",
-- .parent_names = (const char *[]){ "blsp2_qup6_spi_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp2_qup6_spi_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2149,7 +2285,9 @@ static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp2_qup6_i2c_apps_clk",
-- .parent_names = (const char *[]){ "blsp2_qup6_i2c_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp2_qup6_i2c_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2164,7 +2302,9 @@ static struct clk_branch gcc_blsp2_uart6_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp2_uart6_apps_clk",
-- .parent_names = (const char *[]){ "blsp2_uart6_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp2_uart6_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2179,7 +2319,9 @@ static struct clk_branch gcc_pdm_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pdm_ahb_clk",
-- .parent_names = (const char *[]){ "periph_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &periph_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2194,7 +2336,9 @@ static struct clk_branch gcc_pdm2_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pdm2_clk",
-- .parent_names = (const char *[]){ "pdm2_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &pdm2_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2210,7 +2354,9 @@ static struct clk_branch gcc_prng_ahb_clk = {
- .enable_mask = BIT(13),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_prng_ahb_clk",
-- .parent_names = (const char *[]){ "config_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &config_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2225,7 +2371,9 @@ static struct clk_branch gcc_tsif_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_tsif_ahb_clk",
-- .parent_names = (const char *[]){ "periph_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &periph_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2240,7 +2388,9 @@ static struct clk_branch gcc_tsif_ref_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_tsif_ref_clk",
-- .parent_names = (const char *[]){ "tsif_ref_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &tsif_ref_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2255,7 +2405,9 @@ static struct clk_branch gcc_tsif_inactivity_timers_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_tsif_inactivity_timers_clk",
-- .parent_names = (const char *[]){ "gcc_sleep_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &gcc_sleep_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2271,7 +2423,9 @@ static struct clk_branch gcc_boot_rom_ahb_clk = {
- .enable_mask = BIT(10),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_boot_rom_ahb_clk",
-- .parent_names = (const char *[]){ "config_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &config_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2299,7 +2453,9 @@ static struct clk_branch gcc_hmss_rbcpr_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_hmss_rbcpr_clk",
-- .parent_names = (const char *[]){ "hmss_rbcpr_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &hmss_rbcpr_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2314,7 +2470,9 @@ static struct clk_branch gcc_gp1_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_gp1_clk",
-- .parent_names = (const char *[]){ "gp1_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &gp1_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2329,7 +2487,9 @@ static struct clk_branch gcc_gp2_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_gp2_clk",
-- .parent_names = (const char *[]){ "gp2_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &gp2_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2344,7 +2504,9 @@ static struct clk_branch gcc_gp3_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_gp3_clk",
-- .parent_names = (const char *[]){ "gp3_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &gp3_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2359,7 +2521,9 @@ static struct clk_branch gcc_pcie_0_slv_axi_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie_0_slv_axi_clk",
-- .parent_names = (const char *[]){ "system_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &system_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2374,7 +2538,9 @@ static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie_0_mstr_axi_clk",
-- .parent_names = (const char *[]){ "system_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &system_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2389,7 +2555,9 @@ static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie_0_cfg_ahb_clk",
-- .parent_names = (const char *[]){ "config_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &config_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2404,7 +2572,9 @@ static struct clk_branch gcc_pcie_0_aux_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie_0_aux_clk",
-- .parent_names = (const char *[]){ "pcie_aux_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &pcie_aux_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2420,7 +2590,9 @@ static struct clk_branch gcc_pcie_0_pipe_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie_0_pipe_clk",
-- .parent_names = (const char *[]){ "pcie_0_pipe_clk_src" },
-+ .parent_data = &(const struct clk_parent_data){
-+ .fw_name = "pcie_0_pipe_clk_src", .name = "pcie_0_pipe_clk_src",
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2435,7 +2607,9 @@ static struct clk_branch gcc_pcie_1_slv_axi_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie_1_slv_axi_clk",
-- .parent_names = (const char *[]){ "system_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &system_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2450,7 +2624,9 @@ static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie_1_mstr_axi_clk",
-- .parent_names = (const char *[]){ "system_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &system_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2465,7 +2641,9 @@ static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie_1_cfg_ahb_clk",
-- .parent_names = (const char *[]){ "config_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &config_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2480,7 +2658,9 @@ static struct clk_branch gcc_pcie_1_aux_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie_1_aux_clk",
-- .parent_names = (const char *[]){ "pcie_aux_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &pcie_aux_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2496,7 +2676,9 @@ static struct clk_branch gcc_pcie_1_pipe_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie_1_pipe_clk",
-- .parent_names = (const char *[]){ "pcie_1_pipe_clk_src" },
-+ .parent_data = &(const struct clk_parent_data){
-+ .fw_name = "pcie_1_pipe_clk_src", .name = "pcie_1_pipe_clk_src",
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2511,7 +2693,9 @@ static struct clk_branch gcc_pcie_2_slv_axi_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie_2_slv_axi_clk",
-- .parent_names = (const char *[]){ "system_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &system_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2526,7 +2710,9 @@ static struct clk_branch gcc_pcie_2_mstr_axi_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie_2_mstr_axi_clk",
-- .parent_names = (const char *[]){ "system_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &system_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2541,7 +2727,9 @@ static struct clk_branch gcc_pcie_2_cfg_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie_2_cfg_ahb_clk",
-- .parent_names = (const char *[]){ "config_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &config_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2556,7 +2744,9 @@ static struct clk_branch gcc_pcie_2_aux_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie_2_aux_clk",
-- .parent_names = (const char *[]){ "pcie_aux_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &pcie_aux_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2572,7 +2762,9 @@ static struct clk_branch gcc_pcie_2_pipe_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie_2_pipe_clk",
-- .parent_names = (const char *[]){ "pcie_2_pipe_clk_src" },
-+ .parent_data = &(const struct clk_parent_data){
-+ .fw_name = "pcie_2_pipe_clk_src", .name = "pcie_2_pipe_clk_src",
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2587,7 +2779,9 @@ static struct clk_branch gcc_pcie_phy_cfg_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie_phy_cfg_ahb_clk",
-- .parent_names = (const char *[]){ "config_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &config_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2602,7 +2796,9 @@ static struct clk_branch gcc_pcie_phy_aux_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie_phy_aux_clk",
-- .parent_names = (const char *[]){ "pcie_aux_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &pcie_aux_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2617,7 +2813,9 @@ static struct clk_branch gcc_ufs_axi_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_ufs_axi_clk",
-- .parent_names = (const char *[]){ "ufs_axi_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &ufs_axi_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2632,7 +2830,9 @@ static struct clk_branch gcc_ufs_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_ufs_ahb_clk",
-- .parent_names = (const char *[]){ "config_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &config_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2645,7 +2845,9 @@ static struct clk_fixed_factor ufs_tx_cfg_clk_src = {
- .div = 16,
- .hw.init = &(struct clk_init_data){
- .name = "ufs_tx_cfg_clk_src",
-- .parent_names = (const char *[]){ "ufs_axi_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &ufs_axi_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_fixed_factor_ops,
-@@ -2659,7 +2861,9 @@ static struct clk_branch gcc_ufs_tx_cfg_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_ufs_tx_cfg_clk",
-- .parent_names = (const char *[]){ "ufs_tx_cfg_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &ufs_tx_cfg_clk_src.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2672,7 +2876,9 @@ static struct clk_fixed_factor ufs_rx_cfg_clk_src = {
- .div = 16,
- .hw.init = &(struct clk_init_data){
- .name = "ufs_rx_cfg_clk_src",
-- .parent_names = (const char *[]){ "ufs_axi_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &ufs_axi_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_fixed_factor_ops,
-@@ -2712,7 +2918,9 @@ static struct clk_branch gcc_ufs_rx_cfg_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_ufs_rx_cfg_clk",
-- .parent_names = (const char *[]){ "ufs_rx_cfg_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &ufs_rx_cfg_clk_src.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2728,7 +2936,9 @@ static struct clk_branch gcc_ufs_tx_symbol_0_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_ufs_tx_symbol_0_clk",
-- .parent_names = (const char *[]){ "ufs_tx_symbol_0_clk_src" },
-+ .parent_data = &(const struct clk_parent_data){
-+ .fw_name = "ufs_tx_symbol_0_clk_src", .name = "ufs_tx_symbol_0_clk_src",
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2744,7 +2954,9 @@ static struct clk_branch gcc_ufs_rx_symbol_0_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_ufs_rx_symbol_0_clk",
-- .parent_names = (const char *[]){ "ufs_rx_symbol_0_clk_src" },
-+ .parent_data = &(const struct clk_parent_data){
-+ .fw_name = "ufs_rx_symbol_0_clk_src", .name = "ufs_rx_symbol_0_clk_src",
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2760,7 +2972,9 @@ static struct clk_branch gcc_ufs_rx_symbol_1_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_ufs_rx_symbol_1_clk",
-- .parent_names = (const char *[]){ "ufs_rx_symbol_1_clk_src" },
-+ .parent_data = &(const struct clk_parent_data){
-+ .fw_name = "ufs_rx_symbol_1_clk_src", .name = "ufs_rx_symbol_1_clk_src",
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2773,7 +2987,9 @@ static struct clk_fixed_factor ufs_ice_core_postdiv_clk_src = {
- .div = 2,
- .hw.init = &(struct clk_init_data){
- .name = "ufs_ice_core_postdiv_clk_src",
-- .parent_names = (const char *[]){ "ufs_ice_core_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &ufs_ice_core_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_fixed_factor_ops,
-@@ -2787,7 +3003,9 @@ static struct clk_branch gcc_ufs_unipro_core_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_ufs_unipro_core_clk",
-- .parent_names = (const char *[]){ "ufs_ice_core_postdiv_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &ufs_ice_core_postdiv_clk_src.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2802,7 +3020,9 @@ static struct clk_branch gcc_ufs_ice_core_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_ufs_ice_core_clk",
-- .parent_names = (const char *[]){ "ufs_ice_core_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &ufs_ice_core_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2841,7 +3061,9 @@ static struct clk_branch gcc_aggre0_snoc_axi_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_aggre0_snoc_axi_clk",
-- .parent_names = (const char *[]){ "system_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &system_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
- .ops = &clk_branch2_ops,
-@@ -2856,7 +3078,9 @@ static struct clk_branch gcc_aggre0_cnoc_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_aggre0_cnoc_ahb_clk",
-- .parent_names = (const char *[]){ "config_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &config_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
- .ops = &clk_branch2_ops,
-@@ -2871,7 +3095,9 @@ static struct clk_branch gcc_smmu_aggre0_axi_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_smmu_aggre0_axi_clk",
-- .parent_names = (const char *[]){ "system_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &system_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
- .ops = &clk_branch2_ops,
-@@ -2886,7 +3112,9 @@ static struct clk_branch gcc_smmu_aggre0_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_smmu_aggre0_ahb_clk",
-- .parent_names = (const char *[]){ "config_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &config_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
- .ops = &clk_branch2_ops,
-@@ -2901,7 +3129,9 @@ static struct clk_branch gcc_aggre2_ufs_axi_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_aggre2_ufs_axi_clk",
-- .parent_names = (const char *[]){ "ufs_axi_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &ufs_axi_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2916,7 +3146,9 @@ static struct clk_branch gcc_aggre2_usb3_axi_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_aggre2_usb3_axi_clk",
-- .parent_names = (const char *[]){ "usb30_master_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &usb30_master_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2931,7 +3163,9 @@ static struct clk_branch gcc_dcc_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_dcc_ahb_clk",
-- .parent_names = (const char *[]){ "config_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &config_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .ops = &clk_branch2_ops,
- },
-@@ -2945,7 +3179,9 @@ static struct clk_branch gcc_aggre0_noc_mpu_cfg_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_aggre0_noc_mpu_cfg_ahb_clk",
-- .parent_names = (const char *[]){ "config_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &config_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .ops = &clk_branch2_ops,
- },
-@@ -2959,7 +3195,9 @@ static struct clk_branch gcc_qspi_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_qspi_ahb_clk",
-- .parent_names = (const char *[]){ "periph_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &periph_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2974,7 +3212,9 @@ static struct clk_branch gcc_qspi_ser_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_qspi_ser_clk",
-- .parent_names = (const char *[]){ "qspi_ser_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &qspi_ser_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3108,7 +3348,9 @@ static struct clk_branch gcc_mss_cfg_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_mss_cfg_ahb_clk",
-- .parent_names = (const char *[]){ "config_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &config_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .ops = &clk_branch2_ops,
- },
-@@ -3122,7 +3364,9 @@ static struct clk_branch gcc_mss_mnoc_bimc_axi_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_mss_mnoc_bimc_axi_clk",
-- .parent_names = (const char *[]){ "system_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &system_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .ops = &clk_branch2_ops,
- },
-@@ -3136,7 +3380,9 @@ static struct clk_branch gcc_mss_snoc_axi_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_mss_snoc_axi_clk",
-- .parent_names = (const char *[]){ "system_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &system_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .ops = &clk_branch2_ops,
- },
-@@ -3150,7 +3396,9 @@ static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_mss_q6_bimc_axi_clk",
-- .parent_names = (const char *[]){ "system_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &system_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .ops = &clk_branch2_ops,
- },
---
-2.42.0
-
net-add-dev_stats_read-helper.patch
ipvlan-properly-track-tx_errors.patch
regmap-debugfs-fix-a-erroneous-check-after-snprintf.patch
-clk-qcom-gcc-msm8996-use-array_size-instead-of-speci.patch
-clk-qcom-gcc-msm8996-drop-unsupported-clock-sources.patch
-clk-qcom-gcc-msm8996-move-clock-parent-tables-down.patch
-clk-qcom-gcc-msm8996-use-parent_hws-_data-instead-of.patch
-clk-qcom-gcc-msm8996-remove-rpm-bus-clocks.patch
clk-qcom-clk-rcg2-fix-clock-rate-overflow-for-high-p.patch
clk-qcom-mmcc-msm8998-add-hardware-clockgating-regis.patch
clk-qcom-mmcc-msm8998-don-t-check-halt-bit-on-some-b.patch
+++ /dev/null
-From 6deb0edb736574297922aed9e13ccedb386f1b4d Mon Sep 17 00:00:00 2001
-From: Sasha Levin <sashal@kernel.org>
-Date: Tue, 28 Dec 2021 07:54:12 +0300
-Subject: clk: qcom: gcc-msm8996: drop unsupported clock sources
-
-From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-
-[ Upstream commit b554a687b4971ae137e92ee3feddc38e85a38d60 ]
-
-In preparation of updating the msm8996 gcc driver, drop all unsupported
-GPLL sources (gpll1/gpll1_early_div, gpll2/gpll2_early and gpll3).
-Downstream kernel also does not provide support for these GPLL sources,
-so it is safe to drop them.
-
-Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Link: https://lore.kernel.org/r/20211228045415.20543-14-dmitry.baryshkov@linaro.org
-Stable-dep-of: 4afda5f6bcdf ("clk: qcom: gcc-msm8996: Remove RPM bus clocks")
-Signed-off-by: Sasha Levin <sashal@kernel.org>
----
- drivers/clk/qcom/gcc-msm8996.c | 55 ++++------------------------------
- 1 file changed, 6 insertions(+), 49 deletions(-)
-
-diff --git a/drivers/clk/qcom/gcc-msm8996.c b/drivers/clk/qcom/gcc-msm8996.c
-index d95814025c65e..4c85b3935a819 100644
---- a/drivers/clk/qcom/gcc-msm8996.c
-+++ b/drivers/clk/qcom/gcc-msm8996.c
-@@ -27,15 +27,10 @@
- enum {
- P_XO,
- P_GPLL0,
-- P_GPLL2,
-- P_GPLL3,
-- P_GPLL1,
-- P_GPLL2_EARLY,
- P_GPLL0_EARLY_DIV,
- P_SLEEP_CLK,
- P_GPLL4,
- P_AUD_REF_CLK,
-- P_GPLL1_EARLY_DIV
- };
-
- static const struct parent_map gcc_sleep_clk_map[] = {
-@@ -130,44 +125,6 @@ static const char * const gcc_xo_gpll0_gpll4_gpll0_early_div[] = {
- "gpll0_early_div"
- };
-
--static const struct parent_map gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div_map[] = {
-- { P_XO, 0 },
-- { P_GPLL0, 1 },
-- { P_GPLL1_EARLY_DIV, 3 },
-- { P_GPLL1, 4 },
-- { P_GPLL4, 5 },
-- { P_GPLL0_EARLY_DIV, 6 }
--};
--
--static const char * const gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div[] = {
-- "xo",
-- "gpll0",
-- "gpll1_early_div",
-- "gpll1",
-- "gpll4",
-- "gpll0_early_div"
--};
--
--static const struct parent_map gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div_map[] = {
-- { P_XO, 0 },
-- { P_GPLL0, 1 },
-- { P_GPLL2, 2 },
-- { P_GPLL3, 3 },
-- { P_GPLL1, 4 },
-- { P_GPLL2_EARLY, 5 },
-- { P_GPLL0_EARLY_DIV, 6 }
--};
--
--static const char * const gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div[] = {
-- "xo",
-- "gpll0",
-- "gpll2",
-- "gpll3",
-- "gpll1",
-- "gpll2_early",
-- "gpll0_early_div"
--};
--
- static struct clk_fixed_factor xo = {
- .mult = 1,
- .div = 1,
-@@ -285,12 +242,12 @@ static const struct freq_tbl ftbl_system_noc_clk_src[] = {
- static struct clk_rcg2 system_noc_clk_src = {
- .cmd_rcgr = 0x0401c,
- .hid_width = 5,
-- .parent_map = gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div_map,
-+ .parent_map = gcc_xo_gpll0_gpll0_early_div_map,
- .freq_tbl = ftbl_system_noc_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "system_noc_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div,
-- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div),
-+ .parent_names = gcc_xo_gpll0_gpll0_early_div,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1257,12 +1214,12 @@ static const struct freq_tbl ftbl_qspi_ser_clk_src[] = {
- static struct clk_rcg2 qspi_ser_clk_src = {
- .cmd_rcgr = 0x8b00c,
- .hid_width = 5,
-- .parent_map = gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div_map,
-+ .parent_map = gcc_xo_gpll0_gpll4_gpll0_early_div_map,
- .freq_tbl = ftbl_qspi_ser_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "qspi_ser_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div,
-- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div),
-+ .parent_names = gcc_xo_gpll0_gpll4_gpll0_early_div,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_gpll0_early_div),
- .ops = &clk_rcg2_ops,
- },
- };
---
-2.42.0
-
+++ /dev/null
-From 2a8dabd8d0b8c34e0d9370ba081e1277d05f94e1 Mon Sep 17 00:00:00 2001
-From: Sasha Levin <sashal@kernel.org>
-Date: Tue, 28 Dec 2021 07:54:13 +0300
-Subject: clk: qcom: gcc-msm8996: move clock parent tables down
-
-From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-
-[ Upstream commit 1a2789cff03ccdeb70084157387f4a7bf4d2099f ]
-
-Move clock parent tables down, after the GPLL declrataions, so that we
-can use gpll hw clock fields in the next commit.
-
-Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
-Reviewed-by: Stephen Boyd <sboyd@kernel.org>
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Link: https://lore.kernel.org/r/20211228045415.20543-15-dmitry.baryshkov@linaro.org
-Stable-dep-of: 4afda5f6bcdf ("clk: qcom: gcc-msm8996: Remove RPM bus clocks")
-Signed-off-by: Sasha Levin <sashal@kernel.org>
----
- drivers/clk/qcom/gcc-msm8996.c | 184 ++++++++++++++++-----------------
- 1 file changed, 92 insertions(+), 92 deletions(-)
-
-diff --git a/drivers/clk/qcom/gcc-msm8996.c b/drivers/clk/qcom/gcc-msm8996.c
-index 4c85b3935a819..8531f2f3665fe 100644
---- a/drivers/clk/qcom/gcc-msm8996.c
-+++ b/drivers/clk/qcom/gcc-msm8996.c
-@@ -33,98 +33,6 @@ enum {
- P_AUD_REF_CLK,
- };
-
--static const struct parent_map gcc_sleep_clk_map[] = {
-- { P_SLEEP_CLK, 5 }
--};
--
--static const char * const gcc_sleep_clk[] = {
-- "sleep_clk"
--};
--
--static const struct parent_map gcc_xo_gpll0_map[] = {
-- { P_XO, 0 },
-- { P_GPLL0, 1 }
--};
--
--static const char * const gcc_xo_gpll0[] = {
-- "xo",
-- "gpll0"
--};
--
--static const struct parent_map gcc_xo_sleep_clk_map[] = {
-- { P_XO, 0 },
-- { P_SLEEP_CLK, 5 }
--};
--
--static const char * const gcc_xo_sleep_clk[] = {
-- "xo",
-- "sleep_clk"
--};
--
--static const struct parent_map gcc_xo_gpll0_gpll0_early_div_map[] = {
-- { P_XO, 0 },
-- { P_GPLL0, 1 },
-- { P_GPLL0_EARLY_DIV, 6 }
--};
--
--static const char * const gcc_xo_gpll0_gpll0_early_div[] = {
-- "xo",
-- "gpll0",
-- "gpll0_early_div"
--};
--
--static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
-- { P_XO, 0 },
-- { P_GPLL0, 1 },
-- { P_GPLL4, 5 }
--};
--
--static const char * const gcc_xo_gpll0_gpll4[] = {
-- "xo",
-- "gpll0",
-- "gpll4"
--};
--
--static const struct parent_map gcc_xo_gpll0_aud_ref_clk_map[] = {
-- { P_XO, 0 },
-- { P_GPLL0, 1 },
-- { P_AUD_REF_CLK, 2 }
--};
--
--static const char * const gcc_xo_gpll0_aud_ref_clk[] = {
-- "xo",
-- "gpll0",
-- "aud_ref_clk"
--};
--
--static const struct parent_map gcc_xo_gpll0_sleep_clk_gpll0_early_div_map[] = {
-- { P_XO, 0 },
-- { P_GPLL0, 1 },
-- { P_SLEEP_CLK, 5 },
-- { P_GPLL0_EARLY_DIV, 6 }
--};
--
--static const char * const gcc_xo_gpll0_sleep_clk_gpll0_early_div[] = {
-- "xo",
-- "gpll0",
-- "sleep_clk",
-- "gpll0_early_div"
--};
--
--static const struct parent_map gcc_xo_gpll0_gpll4_gpll0_early_div_map[] = {
-- { P_XO, 0 },
-- { P_GPLL0, 1 },
-- { P_GPLL4, 5 },
-- { P_GPLL0_EARLY_DIV, 6 }
--};
--
--static const char * const gcc_xo_gpll0_gpll4_gpll0_early_div[] = {
-- "xo",
-- "gpll0",
-- "gpll4",
-- "gpll0_early_div"
--};
--
- static struct clk_fixed_factor xo = {
- .mult = 1,
- .div = 1,
-@@ -229,6 +137,98 @@ static struct clk_alpha_pll_postdiv gpll4 = {
- },
- };
-
-+static const struct parent_map gcc_sleep_clk_map[] = {
-+ { P_SLEEP_CLK, 5 }
-+};
-+
-+static const char * const gcc_sleep_clk[] = {
-+ "sleep_clk"
-+};
-+
-+static const struct parent_map gcc_xo_gpll0_map[] = {
-+ { P_XO, 0 },
-+ { P_GPLL0, 1 }
-+};
-+
-+static const char * const gcc_xo_gpll0[] = {
-+ "xo",
-+ "gpll0"
-+};
-+
-+static const struct parent_map gcc_xo_sleep_clk_map[] = {
-+ { P_XO, 0 },
-+ { P_SLEEP_CLK, 5 }
-+};
-+
-+static const char * const gcc_xo_sleep_clk[] = {
-+ "xo",
-+ "sleep_clk"
-+};
-+
-+static const struct parent_map gcc_xo_gpll0_gpll0_early_div_map[] = {
-+ { P_XO, 0 },
-+ { P_GPLL0, 1 },
-+ { P_GPLL0_EARLY_DIV, 6 }
-+};
-+
-+static const char * const gcc_xo_gpll0_gpll0_early_div[] = {
-+ "xo",
-+ "gpll0",
-+ "gpll0_early_div"
-+};
-+
-+static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
-+ { P_XO, 0 },
-+ { P_GPLL0, 1 },
-+ { P_GPLL4, 5 }
-+};
-+
-+static const char * const gcc_xo_gpll0_gpll4[] = {
-+ "xo",
-+ "gpll0",
-+ "gpll4"
-+};
-+
-+static const struct parent_map gcc_xo_gpll0_aud_ref_clk_map[] = {
-+ { P_XO, 0 },
-+ { P_GPLL0, 1 },
-+ { P_AUD_REF_CLK, 2 }
-+};
-+
-+static const char * const gcc_xo_gpll0_aud_ref_clk[] = {
-+ "xo",
-+ "gpll0",
-+ "aud_ref_clk"
-+};
-+
-+static const struct parent_map gcc_xo_gpll0_sleep_clk_gpll0_early_div_map[] = {
-+ { P_XO, 0 },
-+ { P_GPLL0, 1 },
-+ { P_SLEEP_CLK, 5 },
-+ { P_GPLL0_EARLY_DIV, 6 }
-+};
-+
-+static const char * const gcc_xo_gpll0_sleep_clk_gpll0_early_div[] = {
-+ "xo",
-+ "gpll0",
-+ "sleep_clk",
-+ "gpll0_early_div"
-+};
-+
-+static const struct parent_map gcc_xo_gpll0_gpll4_gpll0_early_div_map[] = {
-+ { P_XO, 0 },
-+ { P_GPLL0, 1 },
-+ { P_GPLL4, 5 },
-+ { P_GPLL0_EARLY_DIV, 6 }
-+};
-+
-+static const char * const gcc_xo_gpll0_gpll4_gpll0_early_div[] = {
-+ "xo",
-+ "gpll0",
-+ "gpll4",
-+ "gpll0_early_div"
-+};
-+
- static const struct freq_tbl ftbl_system_noc_clk_src[] = {
- F(19200000, P_XO, 1, 0, 0),
- F(50000000, P_GPLL0_EARLY_DIV, 6, 0, 0),
---
-2.42.0
-
+++ /dev/null
-From 783e6719b00d27745f10d2aeb57ad31cbeeeb7c7 Mon Sep 17 00:00:00 2001
-From: Sasha Levin <sashal@kernel.org>
-Date: Thu, 31 Aug 2023 11:39:14 +0200
-Subject: clk: qcom: gcc-msm8996: Remove RPM bus clocks
-
-From: Konrad Dybcio <konrad.dybcio@linaro.org>
-
-[ Upstream commit 4afda5f6bcdf673ef2556fcfa458daf3a5a648d8 ]
-
-The GCC driver contains clocks that are owned (meaning configured and
-scaled) by the RPM core.
-
-Remove them from Linux to stop interjecting the RPM's logic.
-
-Fixes: b1e010c0730a ("clk: qcom: Add MSM8996 Global Clock Control (GCC) driver")
-Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
-Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-Link: https://lore.kernel.org/r/20230830-topic-rpmbusclocks8996gcc-v1-1-9e99bedcdc3b@linaro.org
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Signed-off-by: Sasha Levin <sashal@kernel.org>
----
- drivers/clk/qcom/gcc-msm8996.c | 237 +--------------------------------
- 1 file changed, 5 insertions(+), 232 deletions(-)
-
-diff --git a/drivers/clk/qcom/gcc-msm8996.c b/drivers/clk/qcom/gcc-msm8996.c
-index 6b36024583b4a..2d79a73da1055 100644
---- a/drivers/clk/qcom/gcc-msm8996.c
-+++ b/drivers/clk/qcom/gcc-msm8996.c
-@@ -245,71 +245,6 @@ static const struct clk_parent_data gcc_xo_gpll0_gpll4_gpll0_early_div[] = {
- { .hw = &gpll0_early_div.hw }
- };
-
--static const struct freq_tbl ftbl_system_noc_clk_src[] = {
-- F(19200000, P_XO, 1, 0, 0),
-- F(50000000, P_GPLL0_EARLY_DIV, 6, 0, 0),
-- F(100000000, P_GPLL0, 6, 0, 0),
-- F(150000000, P_GPLL0, 4, 0, 0),
-- F(200000000, P_GPLL0, 3, 0, 0),
-- F(240000000, P_GPLL0, 2.5, 0, 0),
-- { }
--};
--
--static struct clk_rcg2 system_noc_clk_src = {
-- .cmd_rcgr = 0x0401c,
-- .hid_width = 5,
-- .parent_map = gcc_xo_gpll0_gpll0_early_div_map,
-- .freq_tbl = ftbl_system_noc_clk_src,
-- .clkr.hw.init = &(struct clk_init_data){
-- .name = "system_noc_clk_src",
-- .parent_data = gcc_xo_gpll0_gpll0_early_div,
-- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div),
-- .ops = &clk_rcg2_ops,
-- },
--};
--
--static const struct freq_tbl ftbl_config_noc_clk_src[] = {
-- F(19200000, P_XO, 1, 0, 0),
-- F(37500000, P_GPLL0, 16, 0, 0),
-- F(75000000, P_GPLL0, 8, 0, 0),
-- { }
--};
--
--static struct clk_rcg2 config_noc_clk_src = {
-- .cmd_rcgr = 0x0500c,
-- .hid_width = 5,
-- .parent_map = gcc_xo_gpll0_map,
-- .freq_tbl = ftbl_config_noc_clk_src,
-- .clkr.hw.init = &(struct clk_init_data){
-- .name = "config_noc_clk_src",
-- .parent_data = gcc_xo_gpll0,
-- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
-- .ops = &clk_rcg2_ops,
-- },
--};
--
--static const struct freq_tbl ftbl_periph_noc_clk_src[] = {
-- F(19200000, P_XO, 1, 0, 0),
-- F(37500000, P_GPLL0, 16, 0, 0),
-- F(50000000, P_GPLL0, 12, 0, 0),
-- F(75000000, P_GPLL0, 8, 0, 0),
-- F(100000000, P_GPLL0, 6, 0, 0),
-- { }
--};
--
--static struct clk_rcg2 periph_noc_clk_src = {
-- .cmd_rcgr = 0x06014,
-- .hid_width = 5,
-- .parent_map = gcc_xo_gpll0_map,
-- .freq_tbl = ftbl_periph_noc_clk_src,
-- .clkr.hw.init = &(struct clk_init_data){
-- .name = "periph_noc_clk_src",
-- .parent_data = gcc_xo_gpll0,
-- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
-- .ops = &clk_rcg2_ops,
-- },
--};
--
- static const struct freq_tbl ftbl_usb30_master_clk_src[] = {
- F(19200000, P_XO, 1, 0, 0),
- F(120000000, P_GPLL0, 5, 0, 0),
-@@ -1298,11 +1233,7 @@ static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_mmss_noc_cfg_ahb_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &config_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
-+ .flags = CLK_IGNORE_UNUSED,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -1465,11 +1396,6 @@ static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_usb_phy_cfg_ahb2phy_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &periph_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -1499,11 +1425,6 @@ static struct clk_branch gcc_sdcc1_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_sdcc1_ahb_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &periph_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -1550,11 +1471,6 @@ static struct clk_branch gcc_sdcc2_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_sdcc2_ahb_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &periph_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -1584,11 +1500,6 @@ static struct clk_branch gcc_sdcc3_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_sdcc3_ahb_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &periph_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -1618,11 +1529,6 @@ static struct clk_branch gcc_sdcc4_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_sdcc4_ahb_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &periph_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -1636,11 +1542,6 @@ static struct clk_branch gcc_blsp1_ahb_clk = {
- .enable_mask = BIT(17),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_ahb_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &periph_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -1978,11 +1879,6 @@ static struct clk_branch gcc_blsp2_ahb_clk = {
- .enable_mask = BIT(15),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp2_ahb_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &periph_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -2319,11 +2215,6 @@ static struct clk_branch gcc_pdm_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pdm_ahb_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &periph_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -2354,11 +2245,6 @@ static struct clk_branch gcc_prng_ahb_clk = {
- .enable_mask = BIT(13),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_prng_ahb_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &config_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -2371,11 +2257,6 @@ static struct clk_branch gcc_tsif_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_tsif_ahb_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &periph_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -2423,11 +2304,6 @@ static struct clk_branch gcc_boot_rom_ahb_clk = {
- .enable_mask = BIT(10),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_boot_rom_ahb_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &config_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -2521,11 +2397,6 @@ static struct clk_branch gcc_pcie_0_slv_axi_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie_0_slv_axi_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &system_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -2538,11 +2409,6 @@ static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie_0_mstr_axi_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &system_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -2555,11 +2421,6 @@ static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie_0_cfg_ahb_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &config_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -2607,11 +2468,6 @@ static struct clk_branch gcc_pcie_1_slv_axi_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie_1_slv_axi_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &system_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -2624,11 +2480,6 @@ static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie_1_mstr_axi_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &system_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -2641,11 +2492,6 @@ static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie_1_cfg_ahb_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &config_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -2693,11 +2539,6 @@ static struct clk_branch gcc_pcie_2_slv_axi_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie_2_slv_axi_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &system_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -2710,11 +2551,6 @@ static struct clk_branch gcc_pcie_2_mstr_axi_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie_2_mstr_axi_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &system_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -2727,11 +2563,6 @@ static struct clk_branch gcc_pcie_2_cfg_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie_2_cfg_ahb_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &config_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -2779,11 +2610,6 @@ static struct clk_branch gcc_pcie_phy_cfg_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie_phy_cfg_ahb_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &config_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -2830,11 +2656,6 @@ static struct clk_branch gcc_ufs_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_ufs_ahb_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &config_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -3061,11 +2882,7 @@ static struct clk_branch gcc_aggre0_snoc_axi_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_aggre0_snoc_axi_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &system_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
-+ .flags = CLK_IS_CRITICAL,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -3078,11 +2895,7 @@ static struct clk_branch gcc_aggre0_cnoc_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_aggre0_cnoc_ahb_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &config_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
-+ .flags = CLK_IS_CRITICAL,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -3095,11 +2908,7 @@ static struct clk_branch gcc_smmu_aggre0_axi_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_smmu_aggre0_axi_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &system_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
-+ .flags = CLK_IS_CRITICAL,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -3112,11 +2921,7 @@ static struct clk_branch gcc_smmu_aggre0_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_smmu_aggre0_ahb_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &config_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
-+ .flags = CLK_IS_CRITICAL,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -3163,10 +2968,6 @@ static struct clk_branch gcc_dcc_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_dcc_ahb_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &config_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -3179,10 +2980,6 @@ static struct clk_branch gcc_aggre0_noc_mpu_cfg_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_aggre0_noc_mpu_cfg_ahb_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &config_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -3195,11 +2992,6 @@ static struct clk_branch gcc_qspi_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_qspi_ahb_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &periph_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -3348,10 +3140,6 @@ static struct clk_branch gcc_mss_cfg_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_mss_cfg_ahb_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &config_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -3364,10 +3152,6 @@ static struct clk_branch gcc_mss_mnoc_bimc_axi_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_mss_mnoc_bimc_axi_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &system_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -3380,10 +3164,6 @@ static struct clk_branch gcc_mss_snoc_axi_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_mss_snoc_axi_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &system_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -3396,10 +3176,6 @@ static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_mss_q6_bimc_axi_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &system_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -3495,9 +3271,6 @@ static struct clk_regmap *gcc_msm8996_clocks[] = {
- [GPLL0] = &gpll0.clkr,
- [GPLL4_EARLY] = &gpll4_early.clkr,
- [GPLL4] = &gpll4.clkr,
-- [SYSTEM_NOC_CLK_SRC] = &system_noc_clk_src.clkr,
-- [CONFIG_NOC_CLK_SRC] = &config_noc_clk_src.clkr,
-- [PERIPH_NOC_CLK_SRC] = &periph_noc_clk_src.clkr,
- [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
- [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
- [USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr,
---
-2.42.0
-
+++ /dev/null
-From fb74a203f8a020b7db1e36bf34c90943cf3233b4 Mon Sep 17 00:00:00 2001
-From: Sasha Levin <sashal@kernel.org>
-Date: Tue, 28 Dec 2021 07:54:11 +0300
-Subject: clk: qcom: gcc-msm8996: use ARRAY_SIZE instead of specifying
- num_parents
-
-From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-
-[ Upstream commit ed96df3d461eeb2c40cb06ca5fd51644d0f4a2c0 ]
-
-Use ARRAY_SIZE() instead of manually specifying num_parents. This makes
-adding/removing entries to/from parent_data easy and errorproof.
-
-Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Link: https://lore.kernel.org/r/20211228045415.20543-13-dmitry.baryshkov@linaro.org
-Stable-dep-of: 4afda5f6bcdf ("clk: qcom: gcc-msm8996: Remove RPM bus clocks")
-Signed-off-by: Sasha Levin <sashal@kernel.org>
----
- drivers/clk/qcom/gcc-msm8996.c | 122 ++++++++++++++++-----------------
- 1 file changed, 61 insertions(+), 61 deletions(-)
-
-diff --git a/drivers/clk/qcom/gcc-msm8996.c b/drivers/clk/qcom/gcc-msm8996.c
-index 9b1674b28d45d..d95814025c65e 100644
---- a/drivers/clk/qcom/gcc-msm8996.c
-+++ b/drivers/clk/qcom/gcc-msm8996.c
-@@ -290,7 +290,7 @@ static struct clk_rcg2 system_noc_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "system_noc_clk_src",
- .parent_names = gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div,
-- .num_parents = 7,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -310,7 +310,7 @@ static struct clk_rcg2 config_noc_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "config_noc_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -332,7 +332,7 @@ static struct clk_rcg2 periph_noc_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "periph_noc_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -353,7 +353,7 @@ static struct clk_rcg2 usb30_master_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "usb30_master_clk_src",
- .parent_names = gcc_xo_gpll0_gpll0_early_div,
-- .num_parents = 3,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -371,7 +371,7 @@ static struct clk_rcg2 usb30_mock_utmi_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "usb30_mock_utmi_clk_src",
- .parent_names = gcc_xo_gpll0_gpll0_early_div,
-- .num_parents = 3,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -389,7 +389,7 @@ static struct clk_rcg2 usb3_phy_aux_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "usb3_phy_aux_clk_src",
- .parent_names = gcc_xo_sleep_clk,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_sleep_clk),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -408,7 +408,7 @@ static struct clk_rcg2 usb20_master_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "usb20_master_clk_src",
- .parent_names = gcc_xo_gpll0_gpll0_early_div,
-- .num_parents = 3,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -421,7 +421,7 @@ static struct clk_rcg2 usb20_mock_utmi_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "usb20_mock_utmi_clk_src",
- .parent_names = gcc_xo_gpll0_gpll0_early_div,
-- .num_parents = 3,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -447,7 +447,7 @@ static struct clk_rcg2 sdcc1_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "sdcc1_apps_clk_src",
- .parent_names = gcc_xo_gpll0_gpll4_gpll0_early_div,
-- .num_parents = 4,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_gpll0_early_div),
- .ops = &clk_rcg2_floor_ops,
- },
- };
-@@ -467,7 +467,7 @@ static struct clk_rcg2 sdcc1_ice_core_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "sdcc1_ice_core_clk_src",
- .parent_names = gcc_xo_gpll0_gpll4_gpll0_early_div,
-- .num_parents = 4,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_gpll0_early_div),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -492,7 +492,7 @@ static struct clk_rcg2 sdcc2_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "sdcc2_apps_clk_src",
- .parent_names = gcc_xo_gpll0_gpll4,
-- .num_parents = 3,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
- .ops = &clk_rcg2_floor_ops,
- },
- };
-@@ -506,7 +506,7 @@ static struct clk_rcg2 sdcc3_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "sdcc3_apps_clk_src",
- .parent_names = gcc_xo_gpll0_gpll4,
-- .num_parents = 3,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
- .ops = &clk_rcg2_floor_ops,
- },
- };
-@@ -530,7 +530,7 @@ static struct clk_rcg2 sdcc4_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "sdcc4_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_floor_ops,
- },
- };
-@@ -555,7 +555,7 @@ static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup1_spi_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -574,7 +574,7 @@ static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup1_i2c_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -607,7 +607,7 @@ static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_uart1_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -621,7 +621,7 @@ static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup2_spi_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -634,7 +634,7 @@ static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup2_i2c_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -648,7 +648,7 @@ static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_uart2_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -662,7 +662,7 @@ static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup3_spi_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -675,7 +675,7 @@ static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup3_i2c_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -689,7 +689,7 @@ static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_uart3_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -703,7 +703,7 @@ static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup4_spi_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -716,7 +716,7 @@ static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup4_i2c_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -730,7 +730,7 @@ static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_uart4_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -744,7 +744,7 @@ static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup5_spi_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -757,7 +757,7 @@ static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup5_i2c_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -771,7 +771,7 @@ static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_uart5_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -785,7 +785,7 @@ static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup6_spi_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -798,7 +798,7 @@ static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup6_i2c_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -812,7 +812,7 @@ static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_uart6_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -826,7 +826,7 @@ static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_qup1_spi_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -839,7 +839,7 @@ static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_qup1_i2c_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -853,7 +853,7 @@ static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_uart1_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -867,7 +867,7 @@ static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_qup2_spi_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -880,7 +880,7 @@ static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_qup2_i2c_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -894,7 +894,7 @@ static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_uart2_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -908,7 +908,7 @@ static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_qup3_spi_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -921,7 +921,7 @@ static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_qup3_i2c_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -935,7 +935,7 @@ static struct clk_rcg2 blsp2_uart3_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_uart3_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -949,7 +949,7 @@ static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_qup4_spi_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -962,7 +962,7 @@ static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_qup4_i2c_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -976,7 +976,7 @@ static struct clk_rcg2 blsp2_uart4_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_uart4_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -990,7 +990,7 @@ static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_qup5_spi_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1003,7 +1003,7 @@ static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_qup5_i2c_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1017,7 +1017,7 @@ static struct clk_rcg2 blsp2_uart5_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_uart5_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1031,7 +1031,7 @@ static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_qup6_spi_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1044,7 +1044,7 @@ static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_qup6_i2c_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1058,7 +1058,7 @@ static struct clk_rcg2 blsp2_uart6_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_uart6_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1076,7 +1076,7 @@ static struct clk_rcg2 pdm2_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "pdm2_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1095,7 +1095,7 @@ static struct clk_rcg2 tsif_ref_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "tsif_ref_clk_src",
- .parent_names = gcc_xo_gpll0_aud_ref_clk,
-- .num_parents = 3,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_aud_ref_clk),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1107,7 +1107,7 @@ static struct clk_rcg2 gcc_sleep_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "gcc_sleep_clk_src",
- .parent_names = gcc_sleep_clk,
-- .num_parents = 1,
-+ .num_parents = ARRAY_SIZE(gcc_sleep_clk),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1120,7 +1120,7 @@ static struct clk_rcg2 hmss_rbcpr_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "hmss_rbcpr_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1132,7 +1132,7 @@ static struct clk_rcg2 hmss_gpll0_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "hmss_gpll0_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1153,7 +1153,7 @@ static struct clk_rcg2 gp1_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "gp1_clk_src",
- .parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
-- .num_parents = 4,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk_gpll0_early_div),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1167,7 +1167,7 @@ static struct clk_rcg2 gp2_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "gp2_clk_src",
- .parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
-- .num_parents = 4,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk_gpll0_early_div),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1181,7 +1181,7 @@ static struct clk_rcg2 gp3_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "gp3_clk_src",
- .parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
-- .num_parents = 4,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk_gpll0_early_div),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1200,7 +1200,7 @@ static struct clk_rcg2 pcie_aux_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "pcie_aux_clk_src",
- .parent_names = gcc_xo_sleep_clk,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_sleep_clk),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1221,7 +1221,7 @@ static struct clk_rcg2 ufs_axi_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "ufs_axi_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1241,7 +1241,7 @@ static struct clk_rcg2 ufs_ice_core_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "ufs_ice_core_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1262,7 +1262,7 @@ static struct clk_rcg2 qspi_ser_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "qspi_ser_clk_src",
- .parent_names = gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div,
-- .num_parents = 6,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div),
- .ops = &clk_rcg2_ops,
- },
- };
---
-2.42.0
-
+++ /dev/null
-From 2c539d7b261e3a9e80e634d0a8dbb891641c152b Mon Sep 17 00:00:00 2001
-From: Sasha Levin <sashal@kernel.org>
-Date: Tue, 28 Dec 2021 07:54:14 +0300
-Subject: clk: qcom: gcc-msm8996: use parent_hws/_data instead of parent_names
-
-From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-
-[ Upstream commit b3867679d460d67aaef5aa76e4512197a5375514 ]
-
-Convert the clock driver to specify parent data rather than parent
-names, to actually bind using 'clock-names' specified in the DTS rather
-than global clock names. Use parent_hws where possible to refer parent
-clocks directly, skipping the lookup.
-
-Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Link: https://lore.kernel.org/r/20211228045415.20543-16-dmitry.baryshkov@linaro.org
-Stable-dep-of: 4afda5f6bcdf ("clk: qcom: gcc-msm8996: Remove RPM bus clocks")
-Signed-off-by: Sasha Levin <sashal@kernel.org>
----
- drivers/clk/qcom/gcc-msm8996.c | 678 ++++++++++++++++++++++-----------
- 1 file changed, 463 insertions(+), 215 deletions(-)
-
-diff --git a/drivers/clk/qcom/gcc-msm8996.c b/drivers/clk/qcom/gcc-msm8996.c
-index 8531f2f3665fe..6b36024583b4a 100644
---- a/drivers/clk/qcom/gcc-msm8996.c
-+++ b/drivers/clk/qcom/gcc-msm8996.c
-@@ -38,7 +38,9 @@ static struct clk_fixed_factor xo = {
- .div = 1,
- .hw.init = &(struct clk_init_data){
- .name = "xo",
-- .parent_names = (const char *[]){ "xo_board" },
-+ .parent_data = &(const struct clk_parent_data){
-+ .fw_name = "cxo", .name = "xo_board",
-+ },
- .num_parents = 1,
- .ops = &clk_fixed_factor_ops,
- },
-@@ -52,7 +54,9 @@ static struct clk_alpha_pll gpll0_early = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gpll0_early",
-- .parent_names = (const char *[]){ "xo" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &xo.hw,
-+ },
- .num_parents = 1,
- .ops = &clk_alpha_pll_ops,
- },
-@@ -64,7 +68,9 @@ static struct clk_fixed_factor gpll0_early_div = {
- .div = 2,
- .hw.init = &(struct clk_init_data){
- .name = "gpll0_early_div",
-- .parent_names = (const char *[]){ "gpll0_early" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &gpll0_early.clkr.hw,
-+ },
- .num_parents = 1,
- .ops = &clk_fixed_factor_ops,
- },
-@@ -75,7 +81,9 @@ static struct clk_alpha_pll_postdiv gpll0 = {
- .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
- .clkr.hw.init = &(struct clk_init_data){
- .name = "gpll0",
-- .parent_names = (const char *[]){ "gpll0_early" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &gpll0_early.clkr.hw,
-+ },
- .num_parents = 1,
- .ops = &clk_alpha_pll_postdiv_ops,
- },
-@@ -88,7 +96,9 @@ static struct clk_branch gcc_mmss_gpll0_div_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_mmss_gpll0_div_clk",
-- .parent_names = (const char *[]){ "gpll0" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &gpll0.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -103,7 +113,9 @@ static struct clk_branch gcc_mss_gpll0_div_clk = {
- .enable_mask = BIT(2),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_mss_gpll0_div_clk",
-- .parent_names = (const char *[]){ "gpll0" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &gpll0.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops
-@@ -119,7 +131,9 @@ static struct clk_alpha_pll gpll4_early = {
- .enable_mask = BIT(4),
- .hw.init = &(struct clk_init_data){
- .name = "gpll4_early",
-- .parent_names = (const char *[]){ "xo" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &xo.hw,
-+ },
- .num_parents = 1,
- .ops = &clk_alpha_pll_ops,
- },
-@@ -131,7 +145,9 @@ static struct clk_alpha_pll_postdiv gpll4 = {
- .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
- .clkr.hw.init = &(struct clk_init_data){
- .name = "gpll4",
-- .parent_names = (const char *[]){ "gpll4_early" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &gpll4_early.clkr.hw,
-+ },
- .num_parents = 1,
- .ops = &clk_alpha_pll_postdiv_ops,
- },
-@@ -141,8 +157,8 @@ static const struct parent_map gcc_sleep_clk_map[] = {
- { P_SLEEP_CLK, 5 }
- };
-
--static const char * const gcc_sleep_clk[] = {
-- "sleep_clk"
-+static const struct clk_parent_data gcc_sleep_clk[] = {
-+ { .fw_name = "sleep_clk", .name = "sleep_clk" }
- };
-
- static const struct parent_map gcc_xo_gpll0_map[] = {
-@@ -150,9 +166,9 @@ static const struct parent_map gcc_xo_gpll0_map[] = {
- { P_GPLL0, 1 }
- };
-
--static const char * const gcc_xo_gpll0[] = {
-- "xo",
-- "gpll0"
-+static const struct clk_parent_data gcc_xo_gpll0[] = {
-+ { .hw = &xo.hw },
-+ { .hw = &gpll0.clkr.hw }
- };
-
- static const struct parent_map gcc_xo_sleep_clk_map[] = {
-@@ -160,9 +176,9 @@ static const struct parent_map gcc_xo_sleep_clk_map[] = {
- { P_SLEEP_CLK, 5 }
- };
-
--static const char * const gcc_xo_sleep_clk[] = {
-- "xo",
-- "sleep_clk"
-+static const struct clk_parent_data gcc_xo_sleep_clk[] = {
-+ { .hw = &xo.hw },
-+ { .fw_name = "sleep_clk", .name = "sleep_clk" }
- };
-
- static const struct parent_map gcc_xo_gpll0_gpll0_early_div_map[] = {
-@@ -171,10 +187,10 @@ static const struct parent_map gcc_xo_gpll0_gpll0_early_div_map[] = {
- { P_GPLL0_EARLY_DIV, 6 }
- };
-
--static const char * const gcc_xo_gpll0_gpll0_early_div[] = {
-- "xo",
-- "gpll0",
-- "gpll0_early_div"
-+static const struct clk_parent_data gcc_xo_gpll0_gpll0_early_div[] = {
-+ { .hw = &xo.hw },
-+ { .hw = &gpll0.clkr.hw },
-+ { .hw = &gpll0_early_div.hw }
- };
-
- static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
-@@ -183,10 +199,10 @@ static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
- { P_GPLL4, 5 }
- };
-
--static const char * const gcc_xo_gpll0_gpll4[] = {
-- "xo",
-- "gpll0",
-- "gpll4"
-+static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = {
-+ { .hw = &xo.hw },
-+ { .hw = &gpll0.clkr.hw },
-+ { .hw = &gpll4.clkr.hw }
- };
-
- static const struct parent_map gcc_xo_gpll0_aud_ref_clk_map[] = {
-@@ -195,10 +211,10 @@ static const struct parent_map gcc_xo_gpll0_aud_ref_clk_map[] = {
- { P_AUD_REF_CLK, 2 }
- };
-
--static const char * const gcc_xo_gpll0_aud_ref_clk[] = {
-- "xo",
-- "gpll0",
-- "aud_ref_clk"
-+static const struct clk_parent_data gcc_xo_gpll0_aud_ref_clk[] = {
-+ { .hw = &xo.hw },
-+ { .hw = &gpll0.clkr.hw },
-+ { .fw_name = "aud_ref_clk", .name = "aud_ref_clk" }
- };
-
- static const struct parent_map gcc_xo_gpll0_sleep_clk_gpll0_early_div_map[] = {
-@@ -208,11 +224,11 @@ static const struct parent_map gcc_xo_gpll0_sleep_clk_gpll0_early_div_map[] = {
- { P_GPLL0_EARLY_DIV, 6 }
- };
-
--static const char * const gcc_xo_gpll0_sleep_clk_gpll0_early_div[] = {
-- "xo",
-- "gpll0",
-- "sleep_clk",
-- "gpll0_early_div"
-+static const struct clk_parent_data gcc_xo_gpll0_sleep_clk_gpll0_early_div[] = {
-+ { .hw = &xo.hw },
-+ { .hw = &gpll0.clkr.hw },
-+ { .fw_name = "sleep_clk", .name = "sleep_clk" },
-+ { .hw = &gpll0_early_div.hw }
- };
-
- static const struct parent_map gcc_xo_gpll0_gpll4_gpll0_early_div_map[] = {
-@@ -222,11 +238,11 @@ static const struct parent_map gcc_xo_gpll0_gpll4_gpll0_early_div_map[] = {
- { P_GPLL0_EARLY_DIV, 6 }
- };
-
--static const char * const gcc_xo_gpll0_gpll4_gpll0_early_div[] = {
-- "xo",
-- "gpll0",
-- "gpll4",
-- "gpll0_early_div"
-+static const struct clk_parent_data gcc_xo_gpll0_gpll4_gpll0_early_div[] = {
-+ { .hw = &xo.hw },
-+ { .hw = &gpll0.clkr.hw },
-+ { .hw = &gpll4.clkr.hw },
-+ { .hw = &gpll0_early_div.hw }
- };
-
- static const struct freq_tbl ftbl_system_noc_clk_src[] = {
-@@ -246,7 +262,7 @@ static struct clk_rcg2 system_noc_clk_src = {
- .freq_tbl = ftbl_system_noc_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "system_noc_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll0_early_div,
-+ .parent_data = gcc_xo_gpll0_gpll0_early_div,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div),
- .ops = &clk_rcg2_ops,
- },
-@@ -266,7 +282,7 @@ static struct clk_rcg2 config_noc_clk_src = {
- .freq_tbl = ftbl_config_noc_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "config_noc_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -288,7 +304,7 @@ static struct clk_rcg2 periph_noc_clk_src = {
- .freq_tbl = ftbl_periph_noc_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "periph_noc_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -309,7 +325,7 @@ static struct clk_rcg2 usb30_master_clk_src = {
- .freq_tbl = ftbl_usb30_master_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "usb30_master_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll0_early_div,
-+ .parent_data = gcc_xo_gpll0_gpll0_early_div,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div),
- .ops = &clk_rcg2_ops,
- },
-@@ -327,7 +343,7 @@ static struct clk_rcg2 usb30_mock_utmi_clk_src = {
- .freq_tbl = ftbl_usb30_mock_utmi_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "usb30_mock_utmi_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll0_early_div,
-+ .parent_data = gcc_xo_gpll0_gpll0_early_div,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div),
- .ops = &clk_rcg2_ops,
- },
-@@ -345,7 +361,7 @@ static struct clk_rcg2 usb3_phy_aux_clk_src = {
- .freq_tbl = ftbl_usb3_phy_aux_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "usb3_phy_aux_clk_src",
-- .parent_names = gcc_xo_sleep_clk,
-+ .parent_data = gcc_xo_sleep_clk,
- .num_parents = ARRAY_SIZE(gcc_xo_sleep_clk),
- .ops = &clk_rcg2_ops,
- },
-@@ -364,7 +380,7 @@ static struct clk_rcg2 usb20_master_clk_src = {
- .freq_tbl = ftbl_usb20_master_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "usb20_master_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll0_early_div,
-+ .parent_data = gcc_xo_gpll0_gpll0_early_div,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div),
- .ops = &clk_rcg2_ops,
- },
-@@ -377,7 +393,7 @@ static struct clk_rcg2 usb20_mock_utmi_clk_src = {
- .freq_tbl = ftbl_usb30_mock_utmi_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "usb20_mock_utmi_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll0_early_div,
-+ .parent_data = gcc_xo_gpll0_gpll0_early_div,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div),
- .ops = &clk_rcg2_ops,
- },
-@@ -403,7 +419,7 @@ static struct clk_rcg2 sdcc1_apps_clk_src = {
- .freq_tbl = ftbl_sdcc1_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "sdcc1_apps_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll4_gpll0_early_div,
-+ .parent_data = gcc_xo_gpll0_gpll4_gpll0_early_div,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_gpll0_early_div),
- .ops = &clk_rcg2_floor_ops,
- },
-@@ -423,7 +439,7 @@ static struct clk_rcg2 sdcc1_ice_core_clk_src = {
- .freq_tbl = ftbl_sdcc1_ice_core_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "sdcc1_ice_core_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll4_gpll0_early_div,
-+ .parent_data = gcc_xo_gpll0_gpll4_gpll0_early_div,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_gpll0_early_div),
- .ops = &clk_rcg2_ops,
- },
-@@ -448,7 +464,7 @@ static struct clk_rcg2 sdcc2_apps_clk_src = {
- .freq_tbl = ftbl_sdcc2_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "sdcc2_apps_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll4,
-+ .parent_data = gcc_xo_gpll0_gpll4,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
- .ops = &clk_rcg2_floor_ops,
- },
-@@ -462,7 +478,7 @@ static struct clk_rcg2 sdcc3_apps_clk_src = {
- .freq_tbl = ftbl_sdcc2_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "sdcc3_apps_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll4,
-+ .parent_data = gcc_xo_gpll0_gpll4,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
- .ops = &clk_rcg2_floor_ops,
- },
-@@ -486,7 +502,7 @@ static struct clk_rcg2 sdcc4_apps_clk_src = {
- .freq_tbl = ftbl_sdcc4_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "sdcc4_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_floor_ops,
- },
-@@ -511,7 +527,7 @@ static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup1_spi_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -530,7 +546,7 @@ static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup1_i2c_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -563,7 +579,7 @@ static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_uart1_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -577,7 +593,7 @@ static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup2_spi_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -590,7 +606,7 @@ static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup2_i2c_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -604,7 +620,7 @@ static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_uart2_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -618,7 +634,7 @@ static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup3_spi_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -631,7 +647,7 @@ static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup3_i2c_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -645,7 +661,7 @@ static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_uart3_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -659,7 +675,7 @@ static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup4_spi_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -672,7 +688,7 @@ static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup4_i2c_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -686,7 +702,7 @@ static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_uart4_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -700,7 +716,7 @@ static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup5_spi_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -713,7 +729,7 @@ static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup5_i2c_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -727,7 +743,7 @@ static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_uart5_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -741,7 +757,7 @@ static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup6_spi_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -754,7 +770,7 @@ static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup6_i2c_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -768,7 +784,7 @@ static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_uart6_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -782,7 +798,7 @@ static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_qup1_spi_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -795,7 +811,7 @@ static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_qup1_i2c_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -809,7 +825,7 @@ static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_uart1_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -823,7 +839,7 @@ static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_qup2_spi_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -836,7 +852,7 @@ static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_qup2_i2c_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -850,7 +866,7 @@ static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_uart2_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -864,7 +880,7 @@ static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_qup3_spi_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -877,7 +893,7 @@ static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_qup3_i2c_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -891,7 +907,7 @@ static struct clk_rcg2 blsp2_uart3_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_uart3_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -905,7 +921,7 @@ static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_qup4_spi_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -918,7 +934,7 @@ static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_qup4_i2c_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -932,7 +948,7 @@ static struct clk_rcg2 blsp2_uart4_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_uart4_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -946,7 +962,7 @@ static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_qup5_spi_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -959,7 +975,7 @@ static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_qup5_i2c_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -973,7 +989,7 @@ static struct clk_rcg2 blsp2_uart5_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_uart5_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -987,7 +1003,7 @@ static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_qup6_spi_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -1000,7 +1016,7 @@ static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_qup6_i2c_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -1014,7 +1030,7 @@ static struct clk_rcg2 blsp2_uart6_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_uart6_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -1032,7 +1048,7 @@ static struct clk_rcg2 pdm2_clk_src = {
- .freq_tbl = ftbl_pdm2_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "pdm2_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -1051,7 +1067,7 @@ static struct clk_rcg2 tsif_ref_clk_src = {
- .freq_tbl = ftbl_tsif_ref_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "tsif_ref_clk_src",
-- .parent_names = gcc_xo_gpll0_aud_ref_clk,
-+ .parent_data = gcc_xo_gpll0_aud_ref_clk,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_aud_ref_clk),
- .ops = &clk_rcg2_ops,
- },
-@@ -1063,7 +1079,7 @@ static struct clk_rcg2 gcc_sleep_clk_src = {
- .parent_map = gcc_sleep_clk_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "gcc_sleep_clk_src",
-- .parent_names = gcc_sleep_clk,
-+ .parent_data = gcc_sleep_clk,
- .num_parents = ARRAY_SIZE(gcc_sleep_clk),
- .ops = &clk_rcg2_ops,
- },
-@@ -1076,7 +1092,7 @@ static struct clk_rcg2 hmss_rbcpr_clk_src = {
- .freq_tbl = ftbl_usb30_mock_utmi_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "hmss_rbcpr_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -1088,7 +1104,7 @@ static struct clk_rcg2 hmss_gpll0_clk_src = {
- .parent_map = gcc_xo_gpll0_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "hmss_gpll0_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -1109,7 +1125,7 @@ static struct clk_rcg2 gp1_clk_src = {
- .freq_tbl = ftbl_gp1_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "gp1_clk_src",
-- .parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
-+ .parent_data = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk_gpll0_early_div),
- .ops = &clk_rcg2_ops,
- },
-@@ -1123,7 +1139,7 @@ static struct clk_rcg2 gp2_clk_src = {
- .freq_tbl = ftbl_gp1_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "gp2_clk_src",
-- .parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
-+ .parent_data = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk_gpll0_early_div),
- .ops = &clk_rcg2_ops,
- },
-@@ -1137,7 +1153,7 @@ static struct clk_rcg2 gp3_clk_src = {
- .freq_tbl = ftbl_gp1_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "gp3_clk_src",
-- .parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
-+ .parent_data = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk_gpll0_early_div),
- .ops = &clk_rcg2_ops,
- },
-@@ -1156,7 +1172,7 @@ static struct clk_rcg2 pcie_aux_clk_src = {
- .freq_tbl = ftbl_pcie_aux_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "pcie_aux_clk_src",
-- .parent_names = gcc_xo_sleep_clk,
-+ .parent_data = gcc_xo_sleep_clk,
- .num_parents = ARRAY_SIZE(gcc_xo_sleep_clk),
- .ops = &clk_rcg2_ops,
- },
-@@ -1177,7 +1193,7 @@ static struct clk_rcg2 ufs_axi_clk_src = {
- .freq_tbl = ftbl_ufs_axi_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "ufs_axi_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -1197,7 +1213,7 @@ static struct clk_rcg2 ufs_ice_core_clk_src = {
- .freq_tbl = ftbl_ufs_ice_core_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "ufs_ice_core_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -1218,7 +1234,7 @@ static struct clk_rcg2 qspi_ser_clk_src = {
- .freq_tbl = ftbl_qspi_ser_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "qspi_ser_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll4_gpll0_early_div,
-+ .parent_data = gcc_xo_gpll0_gpll4_gpll0_early_div,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_gpll0_early_div),
- .ops = &clk_rcg2_ops,
- },
-@@ -1231,7 +1247,9 @@ static struct clk_branch gcc_sys_noc_usb3_axi_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_sys_noc_usb3_axi_clk",
-- .parent_names = (const char *[]){ "usb30_master_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &usb30_master_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1246,7 +1264,9 @@ static struct clk_branch gcc_sys_noc_ufs_axi_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_sys_noc_ufs_axi_clk",
-- .parent_names = (const char *[]){ "ufs_axi_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &ufs_axi_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1261,7 +1281,9 @@ static struct clk_branch gcc_periph_noc_usb20_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_periph_noc_usb20_ahb_clk",
-- .parent_names = (const char *[]){ "usb20_master_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &usb20_master_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1276,7 +1298,9 @@ static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_mmss_noc_cfg_ahb_clk",
-- .parent_names = (const char *[]){ "config_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &config_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
- .ops = &clk_branch2_ops,
-@@ -1304,7 +1328,9 @@ static struct clk_branch gcc_usb30_master_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_usb30_master_clk",
-- .parent_names = (const char *[]){ "usb30_master_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &usb30_master_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1319,7 +1345,9 @@ static struct clk_branch gcc_usb30_sleep_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_usb30_sleep_clk",
-- .parent_names = (const char *[]){ "gcc_sleep_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &gcc_sleep_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1334,7 +1362,9 @@ static struct clk_branch gcc_usb30_mock_utmi_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_usb30_mock_utmi_clk",
-- .parent_names = (const char *[]){ "usb30_mock_utmi_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &usb30_mock_utmi_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1349,7 +1379,9 @@ static struct clk_branch gcc_usb3_phy_aux_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_usb3_phy_aux_clk",
-- .parent_names = (const char *[]){ "usb3_phy_aux_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &usb3_phy_aux_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1365,7 +1397,9 @@ static struct clk_branch gcc_usb3_phy_pipe_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_usb3_phy_pipe_clk",
-- .parent_names = (const char *[]){ "usb3_phy_pipe_clk_src" },
-+ .parent_data = &(const struct clk_parent_data){
-+ .fw_name = "usb3_phy_pipe_clk_src", .name = "usb3_phy_pipe_clk_src",
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1380,7 +1414,9 @@ static struct clk_branch gcc_usb20_master_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_usb20_master_clk",
-- .parent_names = (const char *[]){ "usb20_master_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &usb20_master_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1395,7 +1431,9 @@ static struct clk_branch gcc_usb20_sleep_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_usb20_sleep_clk",
-- .parent_names = (const char *[]){ "gcc_sleep_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &gcc_sleep_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1410,7 +1448,9 @@ static struct clk_branch gcc_usb20_mock_utmi_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_usb20_mock_utmi_clk",
-- .parent_names = (const char *[]){ "usb20_mock_utmi_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &usb20_mock_utmi_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1425,7 +1465,9 @@ static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_usb_phy_cfg_ahb2phy_clk",
-- .parent_names = (const char *[]){ "periph_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &periph_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1440,7 +1482,9 @@ static struct clk_branch gcc_sdcc1_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_sdcc1_apps_clk",
-- .parent_names = (const char *[]){ "sdcc1_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &sdcc1_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1455,7 +1499,9 @@ static struct clk_branch gcc_sdcc1_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_sdcc1_ahb_clk",
-- .parent_names = (const char *[]){ "periph_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &periph_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1470,7 +1516,9 @@ static struct clk_branch gcc_sdcc1_ice_core_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_sdcc1_ice_core_clk",
-- .parent_names = (const char *[]){ "sdcc1_ice_core_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &sdcc1_ice_core_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1485,7 +1533,9 @@ static struct clk_branch gcc_sdcc2_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_sdcc2_apps_clk",
-- .parent_names = (const char *[]){ "sdcc2_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &sdcc2_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1500,7 +1550,9 @@ static struct clk_branch gcc_sdcc2_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_sdcc2_ahb_clk",
-- .parent_names = (const char *[]){ "periph_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &periph_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1515,7 +1567,9 @@ static struct clk_branch gcc_sdcc3_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_sdcc3_apps_clk",
-- .parent_names = (const char *[]){ "sdcc3_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &sdcc3_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1530,7 +1584,9 @@ static struct clk_branch gcc_sdcc3_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_sdcc3_ahb_clk",
-- .parent_names = (const char *[]){ "periph_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &periph_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1545,7 +1601,9 @@ static struct clk_branch gcc_sdcc4_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_sdcc4_apps_clk",
-- .parent_names = (const char *[]){ "sdcc4_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &sdcc4_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1560,7 +1618,9 @@ static struct clk_branch gcc_sdcc4_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_sdcc4_ahb_clk",
-- .parent_names = (const char *[]){ "periph_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &periph_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1576,7 +1636,9 @@ static struct clk_branch gcc_blsp1_ahb_clk = {
- .enable_mask = BIT(17),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_ahb_clk",
-- .parent_names = (const char *[]){ "periph_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &periph_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1592,7 +1654,9 @@ static struct clk_branch gcc_blsp1_sleep_clk = {
- .enable_mask = BIT(16),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_sleep_clk",
-- .parent_names = (const char *[]){ "gcc_sleep_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &gcc_sleep_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1607,7 +1671,9 @@ static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_qup1_spi_apps_clk",
-- .parent_names = (const char *[]){ "blsp1_qup1_spi_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp1_qup1_spi_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1622,7 +1688,9 @@ static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_qup1_i2c_apps_clk",
-- .parent_names = (const char *[]){ "blsp1_qup1_i2c_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp1_qup1_i2c_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1637,7 +1705,9 @@ static struct clk_branch gcc_blsp1_uart1_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_uart1_apps_clk",
-- .parent_names = (const char *[]){ "blsp1_uart1_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp1_uart1_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1652,7 +1722,9 @@ static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_qup2_spi_apps_clk",
-- .parent_names = (const char *[]){ "blsp1_qup2_spi_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp1_qup2_spi_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1667,7 +1739,9 @@ static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_qup2_i2c_apps_clk",
-- .parent_names = (const char *[]){ "blsp1_qup2_i2c_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp1_qup2_i2c_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1682,7 +1756,9 @@ static struct clk_branch gcc_blsp1_uart2_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_uart2_apps_clk",
-- .parent_names = (const char *[]){ "blsp1_uart2_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp1_uart2_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1697,7 +1773,9 @@ static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_qup3_spi_apps_clk",
-- .parent_names = (const char *[]){ "blsp1_qup3_spi_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp1_qup3_spi_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1712,7 +1790,9 @@ static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_qup3_i2c_apps_clk",
-- .parent_names = (const char *[]){ "blsp1_qup3_i2c_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp1_qup3_i2c_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1727,7 +1807,9 @@ static struct clk_branch gcc_blsp1_uart3_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_uart3_apps_clk",
-- .parent_names = (const char *[]){ "blsp1_uart3_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp1_uart3_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1742,7 +1824,9 @@ static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_qup4_spi_apps_clk",
-- .parent_names = (const char *[]){ "blsp1_qup4_spi_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp1_qup4_spi_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1757,7 +1841,9 @@ static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_qup4_i2c_apps_clk",
-- .parent_names = (const char *[]){ "blsp1_qup4_i2c_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp1_qup4_i2c_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1772,7 +1858,9 @@ static struct clk_branch gcc_blsp1_uart4_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_uart4_apps_clk",
-- .parent_names = (const char *[]){ "blsp1_uart4_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp1_uart4_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1787,7 +1875,9 @@ static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_qup5_spi_apps_clk",
-- .parent_names = (const char *[]){ "blsp1_qup5_spi_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp1_qup5_spi_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1802,7 +1892,9 @@ static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_qup5_i2c_apps_clk",
-- .parent_names = (const char *[]){ "blsp1_qup5_i2c_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp1_qup5_i2c_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1817,7 +1909,9 @@ static struct clk_branch gcc_blsp1_uart5_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_uart5_apps_clk",
-- .parent_names = (const char *[]){ "blsp1_uart5_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp1_uart5_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1832,7 +1926,9 @@ static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_qup6_spi_apps_clk",
-- .parent_names = (const char *[]){ "blsp1_qup6_spi_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp1_qup6_spi_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1847,7 +1943,9 @@ static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_qup6_i2c_apps_clk",
-- .parent_names = (const char *[]){ "blsp1_qup6_i2c_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp1_qup6_i2c_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1862,7 +1960,9 @@ static struct clk_branch gcc_blsp1_uart6_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_uart6_apps_clk",
-- .parent_names = (const char *[]){ "blsp1_uart6_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp1_uart6_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1878,7 +1978,9 @@ static struct clk_branch gcc_blsp2_ahb_clk = {
- .enable_mask = BIT(15),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp2_ahb_clk",
-- .parent_names = (const char *[]){ "periph_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &periph_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1894,7 +1996,9 @@ static struct clk_branch gcc_blsp2_sleep_clk = {
- .enable_mask = BIT(14),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp2_sleep_clk",
-- .parent_names = (const char *[]){ "gcc_sleep_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &gcc_sleep_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1909,7 +2013,9 @@ static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp2_qup1_spi_apps_clk",
-- .parent_names = (const char *[]){ "blsp2_qup1_spi_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp2_qup1_spi_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1924,7 +2030,9 @@ static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp2_qup1_i2c_apps_clk",
-- .parent_names = (const char *[]){ "blsp2_qup1_i2c_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp2_qup1_i2c_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1939,7 +2047,9 @@ static struct clk_branch gcc_blsp2_uart1_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp2_uart1_apps_clk",
-- .parent_names = (const char *[]){ "blsp2_uart1_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp2_uart1_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1954,7 +2064,9 @@ static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp2_qup2_spi_apps_clk",
-- .parent_names = (const char *[]){ "blsp2_qup2_spi_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp2_qup2_spi_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1969,7 +2081,9 @@ static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp2_qup2_i2c_apps_clk",
-- .parent_names = (const char *[]){ "blsp2_qup2_i2c_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp2_qup2_i2c_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1984,7 +2098,9 @@ static struct clk_branch gcc_blsp2_uart2_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp2_uart2_apps_clk",
-- .parent_names = (const char *[]){ "blsp2_uart2_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp2_uart2_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1999,7 +2115,9 @@ static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp2_qup3_spi_apps_clk",
-- .parent_names = (const char *[]){ "blsp2_qup3_spi_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp2_qup3_spi_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2014,7 +2132,9 @@ static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp2_qup3_i2c_apps_clk",
-- .parent_names = (const char *[]){ "blsp2_qup3_i2c_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp2_qup3_i2c_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2029,7 +2149,9 @@ static struct clk_branch gcc_blsp2_uart3_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp2_uart3_apps_clk",
-- .parent_names = (const char *[]){ "blsp2_uart3_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp2_uart3_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2044,7 +2166,9 @@ static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp2_qup4_spi_apps_clk",
-- .parent_names = (const char *[]){ "blsp2_qup4_spi_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp2_qup4_spi_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2059,7 +2183,9 @@ static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp2_qup4_i2c_apps_clk",
-- .parent_names = (const char *[]){ "blsp2_qup4_i2c_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp2_qup4_i2c_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2074,7 +2200,9 @@ static struct clk_branch gcc_blsp2_uart4_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp2_uart4_apps_clk",
-- .parent_names = (const char *[]){ "blsp2_uart4_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp2_uart4_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2089,7 +2217,9 @@ static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp2_qup5_spi_apps_clk",
-- .parent_names = (const char *[]){ "blsp2_qup5_spi_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp2_qup5_spi_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2104,7 +2234,9 @@ static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp2_qup5_i2c_apps_clk",
-- .parent_names = (const char *[]){ "blsp2_qup5_i2c_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp2_qup5_i2c_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2119,7 +2251,9 @@ static struct clk_branch gcc_blsp2_uart5_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp2_uart5_apps_clk",
-- .parent_names = (const char *[]){ "blsp2_uart5_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp2_uart5_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2134,7 +2268,9 @@ static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp2_qup6_spi_apps_clk",
-- .parent_names = (const char *[]){ "blsp2_qup6_spi_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp2_qup6_spi_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2149,7 +2285,9 @@ static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp2_qup6_i2c_apps_clk",
-- .parent_names = (const char *[]){ "blsp2_qup6_i2c_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp2_qup6_i2c_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2164,7 +2302,9 @@ static struct clk_branch gcc_blsp2_uart6_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp2_uart6_apps_clk",
-- .parent_names = (const char *[]){ "blsp2_uart6_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp2_uart6_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2179,7 +2319,9 @@ static struct clk_branch gcc_pdm_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pdm_ahb_clk",
-- .parent_names = (const char *[]){ "periph_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &periph_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2194,7 +2336,9 @@ static struct clk_branch gcc_pdm2_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pdm2_clk",
-- .parent_names = (const char *[]){ "pdm2_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &pdm2_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2210,7 +2354,9 @@ static struct clk_branch gcc_prng_ahb_clk = {
- .enable_mask = BIT(13),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_prng_ahb_clk",
-- .parent_names = (const char *[]){ "config_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &config_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2225,7 +2371,9 @@ static struct clk_branch gcc_tsif_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_tsif_ahb_clk",
-- .parent_names = (const char *[]){ "periph_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &periph_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2240,7 +2388,9 @@ static struct clk_branch gcc_tsif_ref_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_tsif_ref_clk",
-- .parent_names = (const char *[]){ "tsif_ref_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &tsif_ref_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2255,7 +2405,9 @@ static struct clk_branch gcc_tsif_inactivity_timers_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_tsif_inactivity_timers_clk",
-- .parent_names = (const char *[]){ "gcc_sleep_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &gcc_sleep_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2271,7 +2423,9 @@ static struct clk_branch gcc_boot_rom_ahb_clk = {
- .enable_mask = BIT(10),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_boot_rom_ahb_clk",
-- .parent_names = (const char *[]){ "config_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &config_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2299,7 +2453,9 @@ static struct clk_branch gcc_hmss_rbcpr_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_hmss_rbcpr_clk",
-- .parent_names = (const char *[]){ "hmss_rbcpr_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &hmss_rbcpr_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2314,7 +2470,9 @@ static struct clk_branch gcc_gp1_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_gp1_clk",
-- .parent_names = (const char *[]){ "gp1_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &gp1_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2329,7 +2487,9 @@ static struct clk_branch gcc_gp2_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_gp2_clk",
-- .parent_names = (const char *[]){ "gp2_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &gp2_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2344,7 +2504,9 @@ static struct clk_branch gcc_gp3_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_gp3_clk",
-- .parent_names = (const char *[]){ "gp3_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &gp3_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2359,7 +2521,9 @@ static struct clk_branch gcc_pcie_0_slv_axi_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie_0_slv_axi_clk",
-- .parent_names = (const char *[]){ "system_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &system_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2374,7 +2538,9 @@ static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie_0_mstr_axi_clk",
-- .parent_names = (const char *[]){ "system_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &system_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2389,7 +2555,9 @@ static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie_0_cfg_ahb_clk",
-- .parent_names = (const char *[]){ "config_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &config_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2404,7 +2572,9 @@ static struct clk_branch gcc_pcie_0_aux_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie_0_aux_clk",
-- .parent_names = (const char *[]){ "pcie_aux_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &pcie_aux_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2420,7 +2590,9 @@ static struct clk_branch gcc_pcie_0_pipe_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie_0_pipe_clk",
-- .parent_names = (const char *[]){ "pcie_0_pipe_clk_src" },
-+ .parent_data = &(const struct clk_parent_data){
-+ .fw_name = "pcie_0_pipe_clk_src", .name = "pcie_0_pipe_clk_src",
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2435,7 +2607,9 @@ static struct clk_branch gcc_pcie_1_slv_axi_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie_1_slv_axi_clk",
-- .parent_names = (const char *[]){ "system_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &system_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2450,7 +2624,9 @@ static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie_1_mstr_axi_clk",
-- .parent_names = (const char *[]){ "system_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &system_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2465,7 +2641,9 @@ static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie_1_cfg_ahb_clk",
-- .parent_names = (const char *[]){ "config_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &config_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2480,7 +2658,9 @@ static struct clk_branch gcc_pcie_1_aux_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie_1_aux_clk",
-- .parent_names = (const char *[]){ "pcie_aux_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &pcie_aux_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2496,7 +2676,9 @@ static struct clk_branch gcc_pcie_1_pipe_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie_1_pipe_clk",
-- .parent_names = (const char *[]){ "pcie_1_pipe_clk_src" },
-+ .parent_data = &(const struct clk_parent_data){
-+ .fw_name = "pcie_1_pipe_clk_src", .name = "pcie_1_pipe_clk_src",
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2511,7 +2693,9 @@ static struct clk_branch gcc_pcie_2_slv_axi_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie_2_slv_axi_clk",
-- .parent_names = (const char *[]){ "system_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &system_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2526,7 +2710,9 @@ static struct clk_branch gcc_pcie_2_mstr_axi_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie_2_mstr_axi_clk",
-- .parent_names = (const char *[]){ "system_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &system_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2541,7 +2727,9 @@ static struct clk_branch gcc_pcie_2_cfg_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie_2_cfg_ahb_clk",
-- .parent_names = (const char *[]){ "config_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &config_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2556,7 +2744,9 @@ static struct clk_branch gcc_pcie_2_aux_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie_2_aux_clk",
-- .parent_names = (const char *[]){ "pcie_aux_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &pcie_aux_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2572,7 +2762,9 @@ static struct clk_branch gcc_pcie_2_pipe_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie_2_pipe_clk",
-- .parent_names = (const char *[]){ "pcie_2_pipe_clk_src" },
-+ .parent_data = &(const struct clk_parent_data){
-+ .fw_name = "pcie_2_pipe_clk_src", .name = "pcie_2_pipe_clk_src",
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2587,7 +2779,9 @@ static struct clk_branch gcc_pcie_phy_cfg_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie_phy_cfg_ahb_clk",
-- .parent_names = (const char *[]){ "config_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &config_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2602,7 +2796,9 @@ static struct clk_branch gcc_pcie_phy_aux_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie_phy_aux_clk",
-- .parent_names = (const char *[]){ "pcie_aux_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &pcie_aux_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2617,7 +2813,9 @@ static struct clk_branch gcc_ufs_axi_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_ufs_axi_clk",
-- .parent_names = (const char *[]){ "ufs_axi_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &ufs_axi_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2632,7 +2830,9 @@ static struct clk_branch gcc_ufs_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_ufs_ahb_clk",
-- .parent_names = (const char *[]){ "config_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &config_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2645,7 +2845,9 @@ static struct clk_fixed_factor ufs_tx_cfg_clk_src = {
- .div = 16,
- .hw.init = &(struct clk_init_data){
- .name = "ufs_tx_cfg_clk_src",
-- .parent_names = (const char *[]){ "ufs_axi_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &ufs_axi_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_fixed_factor_ops,
-@@ -2659,7 +2861,9 @@ static struct clk_branch gcc_ufs_tx_cfg_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_ufs_tx_cfg_clk",
-- .parent_names = (const char *[]){ "ufs_tx_cfg_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &ufs_tx_cfg_clk_src.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2672,7 +2876,9 @@ static struct clk_fixed_factor ufs_rx_cfg_clk_src = {
- .div = 16,
- .hw.init = &(struct clk_init_data){
- .name = "ufs_rx_cfg_clk_src",
-- .parent_names = (const char *[]){ "ufs_axi_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &ufs_axi_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_fixed_factor_ops,
-@@ -2712,7 +2918,9 @@ static struct clk_branch gcc_ufs_rx_cfg_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_ufs_rx_cfg_clk",
-- .parent_names = (const char *[]){ "ufs_rx_cfg_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &ufs_rx_cfg_clk_src.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2728,7 +2936,9 @@ static struct clk_branch gcc_ufs_tx_symbol_0_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_ufs_tx_symbol_0_clk",
-- .parent_names = (const char *[]){ "ufs_tx_symbol_0_clk_src" },
-+ .parent_data = &(const struct clk_parent_data){
-+ .fw_name = "ufs_tx_symbol_0_clk_src", .name = "ufs_tx_symbol_0_clk_src",
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2744,7 +2954,9 @@ static struct clk_branch gcc_ufs_rx_symbol_0_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_ufs_rx_symbol_0_clk",
-- .parent_names = (const char *[]){ "ufs_rx_symbol_0_clk_src" },
-+ .parent_data = &(const struct clk_parent_data){
-+ .fw_name = "ufs_rx_symbol_0_clk_src", .name = "ufs_rx_symbol_0_clk_src",
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2760,7 +2972,9 @@ static struct clk_branch gcc_ufs_rx_symbol_1_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_ufs_rx_symbol_1_clk",
-- .parent_names = (const char *[]){ "ufs_rx_symbol_1_clk_src" },
-+ .parent_data = &(const struct clk_parent_data){
-+ .fw_name = "ufs_rx_symbol_1_clk_src", .name = "ufs_rx_symbol_1_clk_src",
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2773,7 +2987,9 @@ static struct clk_fixed_factor ufs_ice_core_postdiv_clk_src = {
- .div = 2,
- .hw.init = &(struct clk_init_data){
- .name = "ufs_ice_core_postdiv_clk_src",
-- .parent_names = (const char *[]){ "ufs_ice_core_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &ufs_ice_core_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_fixed_factor_ops,
-@@ -2787,7 +3003,9 @@ static struct clk_branch gcc_ufs_unipro_core_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_ufs_unipro_core_clk",
-- .parent_names = (const char *[]){ "ufs_ice_core_postdiv_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &ufs_ice_core_postdiv_clk_src.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2802,7 +3020,9 @@ static struct clk_branch gcc_ufs_ice_core_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_ufs_ice_core_clk",
-- .parent_names = (const char *[]){ "ufs_ice_core_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &ufs_ice_core_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2841,7 +3061,9 @@ static struct clk_branch gcc_aggre0_snoc_axi_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_aggre0_snoc_axi_clk",
-- .parent_names = (const char *[]){ "system_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &system_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
- .ops = &clk_branch2_ops,
-@@ -2856,7 +3078,9 @@ static struct clk_branch gcc_aggre0_cnoc_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_aggre0_cnoc_ahb_clk",
-- .parent_names = (const char *[]){ "config_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &config_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
- .ops = &clk_branch2_ops,
-@@ -2871,7 +3095,9 @@ static struct clk_branch gcc_smmu_aggre0_axi_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_smmu_aggre0_axi_clk",
-- .parent_names = (const char *[]){ "system_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &system_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
- .ops = &clk_branch2_ops,
-@@ -2886,7 +3112,9 @@ static struct clk_branch gcc_smmu_aggre0_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_smmu_aggre0_ahb_clk",
-- .parent_names = (const char *[]){ "config_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &config_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
- .ops = &clk_branch2_ops,
-@@ -2901,7 +3129,9 @@ static struct clk_branch gcc_aggre2_ufs_axi_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_aggre2_ufs_axi_clk",
-- .parent_names = (const char *[]){ "ufs_axi_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &ufs_axi_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2916,7 +3146,9 @@ static struct clk_branch gcc_aggre2_usb3_axi_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_aggre2_usb3_axi_clk",
-- .parent_names = (const char *[]){ "usb30_master_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &usb30_master_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2931,7 +3163,9 @@ static struct clk_branch gcc_dcc_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_dcc_ahb_clk",
-- .parent_names = (const char *[]){ "config_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &config_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .ops = &clk_branch2_ops,
- },
-@@ -2945,7 +3179,9 @@ static struct clk_branch gcc_aggre0_noc_mpu_cfg_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_aggre0_noc_mpu_cfg_ahb_clk",
-- .parent_names = (const char *[]){ "config_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &config_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .ops = &clk_branch2_ops,
- },
-@@ -2959,7 +3195,9 @@ static struct clk_branch gcc_qspi_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_qspi_ahb_clk",
-- .parent_names = (const char *[]){ "periph_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &periph_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2974,7 +3212,9 @@ static struct clk_branch gcc_qspi_ser_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_qspi_ser_clk",
-- .parent_names = (const char *[]){ "qspi_ser_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &qspi_ser_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3108,7 +3348,9 @@ static struct clk_branch gcc_mss_cfg_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_mss_cfg_ahb_clk",
-- .parent_names = (const char *[]){ "config_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &config_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .ops = &clk_branch2_ops,
- },
-@@ -3122,7 +3364,9 @@ static struct clk_branch gcc_mss_mnoc_bimc_axi_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_mss_mnoc_bimc_axi_clk",
-- .parent_names = (const char *[]){ "system_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &system_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .ops = &clk_branch2_ops,
- },
-@@ -3136,7 +3380,9 @@ static struct clk_branch gcc_mss_snoc_axi_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_mss_snoc_axi_clk",
-- .parent_names = (const char *[]){ "system_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &system_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .ops = &clk_branch2_ops,
- },
-@@ -3150,7 +3396,9 @@ static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_mss_q6_bimc_axi_clk",
-- .parent_names = (const char *[]){ "system_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &system_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .ops = &clk_branch2_ops,
- },
---
-2.42.0
-
ipvlan-properly-track-tx_errors.patch
regmap-debugfs-fix-a-erroneous-check-after-snprintf.patch
spi-tegra-fix-missing-irq-check-in-tegra_slink_probe.patch
-clk-qcom-gcc-msm8996-use-array_size-instead-of-speci.patch
-clk-qcom-gcc-msm8996-drop-unsupported-clock-sources.patch
-clk-qcom-gcc-msm8996-move-clock-parent-tables-down.patch
-clk-qcom-gcc-msm8996-use-parent_hws-_data-instead-of.patch
-clk-qcom-gcc-msm8996-remove-rpm-bus-clocks.patch
clk-qcom-clk-rcg2-fix-clock-rate-overflow-for-high-p.patch
clk-qcom-mmcc-msm8998-don-t-check-halt-bit-on-some-b.patch
clk-qcom-mmcc-msm8998-fix-the-smmu-gdsc.patch
+++ /dev/null
-From db779ffb82bc2173ae7849246192a92d9e32c5f5 Mon Sep 17 00:00:00 2001
-From: Sasha Levin <sashal@kernel.org>
-Date: Tue, 28 Dec 2021 07:54:12 +0300
-Subject: clk: qcom: gcc-msm8996: drop unsupported clock sources
-
-From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-
-[ Upstream commit b554a687b4971ae137e92ee3feddc38e85a38d60 ]
-
-In preparation of updating the msm8996 gcc driver, drop all unsupported
-GPLL sources (gpll1/gpll1_early_div, gpll2/gpll2_early and gpll3).
-Downstream kernel also does not provide support for these GPLL sources,
-so it is safe to drop them.
-
-Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Link: https://lore.kernel.org/r/20211228045415.20543-14-dmitry.baryshkov@linaro.org
-Stable-dep-of: 4afda5f6bcdf ("clk: qcom: gcc-msm8996: Remove RPM bus clocks")
-Signed-off-by: Sasha Levin <sashal@kernel.org>
----
- drivers/clk/qcom/gcc-msm8996.c | 55 ++++------------------------------
- 1 file changed, 6 insertions(+), 49 deletions(-)
-
-diff --git a/drivers/clk/qcom/gcc-msm8996.c b/drivers/clk/qcom/gcc-msm8996.c
-index bb6bf4f1476f1..a166f4cdc0d49 100644
---- a/drivers/clk/qcom/gcc-msm8996.c
-+++ b/drivers/clk/qcom/gcc-msm8996.c
-@@ -27,15 +27,10 @@
- enum {
- P_XO,
- P_GPLL0,
-- P_GPLL2,
-- P_GPLL3,
-- P_GPLL1,
-- P_GPLL2_EARLY,
- P_GPLL0_EARLY_DIV,
- P_SLEEP_CLK,
- P_GPLL4,
- P_AUD_REF_CLK,
-- P_GPLL1_EARLY_DIV
- };
-
- static const struct parent_map gcc_sleep_clk_map[] = {
-@@ -130,44 +125,6 @@ static const char * const gcc_xo_gpll0_gpll4_gpll0_early_div[] = {
- "gpll0_early_div"
- };
-
--static const struct parent_map gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div_map[] = {
-- { P_XO, 0 },
-- { P_GPLL0, 1 },
-- { P_GPLL1_EARLY_DIV, 3 },
-- { P_GPLL1, 4 },
-- { P_GPLL4, 5 },
-- { P_GPLL0_EARLY_DIV, 6 }
--};
--
--static const char * const gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div[] = {
-- "xo",
-- "gpll0",
-- "gpll1_early_div",
-- "gpll1",
-- "gpll4",
-- "gpll0_early_div"
--};
--
--static const struct parent_map gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div_map[] = {
-- { P_XO, 0 },
-- { P_GPLL0, 1 },
-- { P_GPLL2, 2 },
-- { P_GPLL3, 3 },
-- { P_GPLL1, 4 },
-- { P_GPLL2_EARLY, 5 },
-- { P_GPLL0_EARLY_DIV, 6 }
--};
--
--static const char * const gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div[] = {
-- "xo",
-- "gpll0",
-- "gpll2",
-- "gpll3",
-- "gpll1",
-- "gpll2_early",
-- "gpll0_early_div"
--};
--
- static struct clk_fixed_factor xo = {
- .mult = 1,
- .div = 1,
-@@ -285,12 +242,12 @@ static const struct freq_tbl ftbl_system_noc_clk_src[] = {
- static struct clk_rcg2 system_noc_clk_src = {
- .cmd_rcgr = 0x0401c,
- .hid_width = 5,
-- .parent_map = gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div_map,
-+ .parent_map = gcc_xo_gpll0_gpll0_early_div_map,
- .freq_tbl = ftbl_system_noc_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "system_noc_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div,
-- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div),
-+ .parent_names = gcc_xo_gpll0_gpll0_early_div,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1257,12 +1214,12 @@ static const struct freq_tbl ftbl_qspi_ser_clk_src[] = {
- static struct clk_rcg2 qspi_ser_clk_src = {
- .cmd_rcgr = 0x8b00c,
- .hid_width = 5,
-- .parent_map = gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div_map,
-+ .parent_map = gcc_xo_gpll0_gpll4_gpll0_early_div_map,
- .freq_tbl = ftbl_qspi_ser_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "qspi_ser_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div,
-- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div),
-+ .parent_names = gcc_xo_gpll0_gpll4_gpll0_early_div,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_gpll0_early_div),
- .ops = &clk_rcg2_ops,
- },
- };
---
-2.42.0
-
+++ /dev/null
-From f8f51b556fddeae69ee1b248657ffda0731ab063 Mon Sep 17 00:00:00 2001
-From: Sasha Levin <sashal@kernel.org>
-Date: Tue, 28 Dec 2021 07:54:13 +0300
-Subject: clk: qcom: gcc-msm8996: move clock parent tables down
-
-From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-
-[ Upstream commit 1a2789cff03ccdeb70084157387f4a7bf4d2099f ]
-
-Move clock parent tables down, after the GPLL declrataions, so that we
-can use gpll hw clock fields in the next commit.
-
-Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
-Reviewed-by: Stephen Boyd <sboyd@kernel.org>
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Link: https://lore.kernel.org/r/20211228045415.20543-15-dmitry.baryshkov@linaro.org
-Stable-dep-of: 4afda5f6bcdf ("clk: qcom: gcc-msm8996: Remove RPM bus clocks")
-Signed-off-by: Sasha Levin <sashal@kernel.org>
----
- drivers/clk/qcom/gcc-msm8996.c | 184 ++++++++++++++++-----------------
- 1 file changed, 92 insertions(+), 92 deletions(-)
-
-diff --git a/drivers/clk/qcom/gcc-msm8996.c b/drivers/clk/qcom/gcc-msm8996.c
-index a166f4cdc0d49..dbfbdef4044c7 100644
---- a/drivers/clk/qcom/gcc-msm8996.c
-+++ b/drivers/clk/qcom/gcc-msm8996.c
-@@ -33,98 +33,6 @@ enum {
- P_AUD_REF_CLK,
- };
-
--static const struct parent_map gcc_sleep_clk_map[] = {
-- { P_SLEEP_CLK, 5 }
--};
--
--static const char * const gcc_sleep_clk[] = {
-- "sleep_clk"
--};
--
--static const struct parent_map gcc_xo_gpll0_map[] = {
-- { P_XO, 0 },
-- { P_GPLL0, 1 }
--};
--
--static const char * const gcc_xo_gpll0[] = {
-- "xo",
-- "gpll0"
--};
--
--static const struct parent_map gcc_xo_sleep_clk_map[] = {
-- { P_XO, 0 },
-- { P_SLEEP_CLK, 5 }
--};
--
--static const char * const gcc_xo_sleep_clk[] = {
-- "xo",
-- "sleep_clk"
--};
--
--static const struct parent_map gcc_xo_gpll0_gpll0_early_div_map[] = {
-- { P_XO, 0 },
-- { P_GPLL0, 1 },
-- { P_GPLL0_EARLY_DIV, 6 }
--};
--
--static const char * const gcc_xo_gpll0_gpll0_early_div[] = {
-- "xo",
-- "gpll0",
-- "gpll0_early_div"
--};
--
--static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
-- { P_XO, 0 },
-- { P_GPLL0, 1 },
-- { P_GPLL4, 5 }
--};
--
--static const char * const gcc_xo_gpll0_gpll4[] = {
-- "xo",
-- "gpll0",
-- "gpll4"
--};
--
--static const struct parent_map gcc_xo_gpll0_aud_ref_clk_map[] = {
-- { P_XO, 0 },
-- { P_GPLL0, 1 },
-- { P_AUD_REF_CLK, 2 }
--};
--
--static const char * const gcc_xo_gpll0_aud_ref_clk[] = {
-- "xo",
-- "gpll0",
-- "aud_ref_clk"
--};
--
--static const struct parent_map gcc_xo_gpll0_sleep_clk_gpll0_early_div_map[] = {
-- { P_XO, 0 },
-- { P_GPLL0, 1 },
-- { P_SLEEP_CLK, 5 },
-- { P_GPLL0_EARLY_DIV, 6 }
--};
--
--static const char * const gcc_xo_gpll0_sleep_clk_gpll0_early_div[] = {
-- "xo",
-- "gpll0",
-- "sleep_clk",
-- "gpll0_early_div"
--};
--
--static const struct parent_map gcc_xo_gpll0_gpll4_gpll0_early_div_map[] = {
-- { P_XO, 0 },
-- { P_GPLL0, 1 },
-- { P_GPLL4, 5 },
-- { P_GPLL0_EARLY_DIV, 6 }
--};
--
--static const char * const gcc_xo_gpll0_gpll4_gpll0_early_div[] = {
-- "xo",
-- "gpll0",
-- "gpll4",
-- "gpll0_early_div"
--};
--
- static struct clk_fixed_factor xo = {
- .mult = 1,
- .div = 1,
-@@ -229,6 +137,98 @@ static struct clk_alpha_pll_postdiv gpll4 = {
- },
- };
-
-+static const struct parent_map gcc_sleep_clk_map[] = {
-+ { P_SLEEP_CLK, 5 }
-+};
-+
-+static const char * const gcc_sleep_clk[] = {
-+ "sleep_clk"
-+};
-+
-+static const struct parent_map gcc_xo_gpll0_map[] = {
-+ { P_XO, 0 },
-+ { P_GPLL0, 1 }
-+};
-+
-+static const char * const gcc_xo_gpll0[] = {
-+ "xo",
-+ "gpll0"
-+};
-+
-+static const struct parent_map gcc_xo_sleep_clk_map[] = {
-+ { P_XO, 0 },
-+ { P_SLEEP_CLK, 5 }
-+};
-+
-+static const char * const gcc_xo_sleep_clk[] = {
-+ "xo",
-+ "sleep_clk"
-+};
-+
-+static const struct parent_map gcc_xo_gpll0_gpll0_early_div_map[] = {
-+ { P_XO, 0 },
-+ { P_GPLL0, 1 },
-+ { P_GPLL0_EARLY_DIV, 6 }
-+};
-+
-+static const char * const gcc_xo_gpll0_gpll0_early_div[] = {
-+ "xo",
-+ "gpll0",
-+ "gpll0_early_div"
-+};
-+
-+static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
-+ { P_XO, 0 },
-+ { P_GPLL0, 1 },
-+ { P_GPLL4, 5 }
-+};
-+
-+static const char * const gcc_xo_gpll0_gpll4[] = {
-+ "xo",
-+ "gpll0",
-+ "gpll4"
-+};
-+
-+static const struct parent_map gcc_xo_gpll0_aud_ref_clk_map[] = {
-+ { P_XO, 0 },
-+ { P_GPLL0, 1 },
-+ { P_AUD_REF_CLK, 2 }
-+};
-+
-+static const char * const gcc_xo_gpll0_aud_ref_clk[] = {
-+ "xo",
-+ "gpll0",
-+ "aud_ref_clk"
-+};
-+
-+static const struct parent_map gcc_xo_gpll0_sleep_clk_gpll0_early_div_map[] = {
-+ { P_XO, 0 },
-+ { P_GPLL0, 1 },
-+ { P_SLEEP_CLK, 5 },
-+ { P_GPLL0_EARLY_DIV, 6 }
-+};
-+
-+static const char * const gcc_xo_gpll0_sleep_clk_gpll0_early_div[] = {
-+ "xo",
-+ "gpll0",
-+ "sleep_clk",
-+ "gpll0_early_div"
-+};
-+
-+static const struct parent_map gcc_xo_gpll0_gpll4_gpll0_early_div_map[] = {
-+ { P_XO, 0 },
-+ { P_GPLL0, 1 },
-+ { P_GPLL4, 5 },
-+ { P_GPLL0_EARLY_DIV, 6 }
-+};
-+
-+static const char * const gcc_xo_gpll0_gpll4_gpll0_early_div[] = {
-+ "xo",
-+ "gpll0",
-+ "gpll4",
-+ "gpll0_early_div"
-+};
-+
- static const struct freq_tbl ftbl_system_noc_clk_src[] = {
- F(19200000, P_XO, 1, 0, 0),
- F(50000000, P_GPLL0_EARLY_DIV, 6, 0, 0),
---
-2.42.0
-
+++ /dev/null
-From 218c4a0134c3f832d8738b1294d2fe81f6de4877 Mon Sep 17 00:00:00 2001
-From: Sasha Levin <sashal@kernel.org>
-Date: Thu, 31 Aug 2023 11:39:14 +0200
-Subject: clk: qcom: gcc-msm8996: Remove RPM bus clocks
-
-From: Konrad Dybcio <konrad.dybcio@linaro.org>
-
-[ Upstream commit 4afda5f6bcdf673ef2556fcfa458daf3a5a648d8 ]
-
-The GCC driver contains clocks that are owned (meaning configured and
-scaled) by the RPM core.
-
-Remove them from Linux to stop interjecting the RPM's logic.
-
-Fixes: b1e010c0730a ("clk: qcom: Add MSM8996 Global Clock Control (GCC) driver")
-Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
-Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-Link: https://lore.kernel.org/r/20230830-topic-rpmbusclocks8996gcc-v1-1-9e99bedcdc3b@linaro.org
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Signed-off-by: Sasha Levin <sashal@kernel.org>
----
- drivers/clk/qcom/gcc-msm8996.c | 237 +--------------------------------
- 1 file changed, 5 insertions(+), 232 deletions(-)
-
-diff --git a/drivers/clk/qcom/gcc-msm8996.c b/drivers/clk/qcom/gcc-msm8996.c
-index 5b5ee4b7ae81f..824eb03a5f3e7 100644
---- a/drivers/clk/qcom/gcc-msm8996.c
-+++ b/drivers/clk/qcom/gcc-msm8996.c
-@@ -245,71 +245,6 @@ static const struct clk_parent_data gcc_xo_gpll0_gpll4_gpll0_early_div[] = {
- { .hw = &gpll0_early_div.hw }
- };
-
--static const struct freq_tbl ftbl_system_noc_clk_src[] = {
-- F(19200000, P_XO, 1, 0, 0),
-- F(50000000, P_GPLL0_EARLY_DIV, 6, 0, 0),
-- F(100000000, P_GPLL0, 6, 0, 0),
-- F(150000000, P_GPLL0, 4, 0, 0),
-- F(200000000, P_GPLL0, 3, 0, 0),
-- F(240000000, P_GPLL0, 2.5, 0, 0),
-- { }
--};
--
--static struct clk_rcg2 system_noc_clk_src = {
-- .cmd_rcgr = 0x0401c,
-- .hid_width = 5,
-- .parent_map = gcc_xo_gpll0_gpll0_early_div_map,
-- .freq_tbl = ftbl_system_noc_clk_src,
-- .clkr.hw.init = &(struct clk_init_data){
-- .name = "system_noc_clk_src",
-- .parent_data = gcc_xo_gpll0_gpll0_early_div,
-- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div),
-- .ops = &clk_rcg2_ops,
-- },
--};
--
--static const struct freq_tbl ftbl_config_noc_clk_src[] = {
-- F(19200000, P_XO, 1, 0, 0),
-- F(37500000, P_GPLL0, 16, 0, 0),
-- F(75000000, P_GPLL0, 8, 0, 0),
-- { }
--};
--
--static struct clk_rcg2 config_noc_clk_src = {
-- .cmd_rcgr = 0x0500c,
-- .hid_width = 5,
-- .parent_map = gcc_xo_gpll0_map,
-- .freq_tbl = ftbl_config_noc_clk_src,
-- .clkr.hw.init = &(struct clk_init_data){
-- .name = "config_noc_clk_src",
-- .parent_data = gcc_xo_gpll0,
-- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
-- .ops = &clk_rcg2_ops,
-- },
--};
--
--static const struct freq_tbl ftbl_periph_noc_clk_src[] = {
-- F(19200000, P_XO, 1, 0, 0),
-- F(37500000, P_GPLL0, 16, 0, 0),
-- F(50000000, P_GPLL0, 12, 0, 0),
-- F(75000000, P_GPLL0, 8, 0, 0),
-- F(100000000, P_GPLL0, 6, 0, 0),
-- { }
--};
--
--static struct clk_rcg2 periph_noc_clk_src = {
-- .cmd_rcgr = 0x06014,
-- .hid_width = 5,
-- .parent_map = gcc_xo_gpll0_map,
-- .freq_tbl = ftbl_periph_noc_clk_src,
-- .clkr.hw.init = &(struct clk_init_data){
-- .name = "periph_noc_clk_src",
-- .parent_data = gcc_xo_gpll0,
-- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
-- .ops = &clk_rcg2_ops,
-- },
--};
--
- static const struct freq_tbl ftbl_usb30_master_clk_src[] = {
- F(19200000, P_XO, 1, 0, 0),
- F(120000000, P_GPLL0, 5, 0, 0),
-@@ -1298,11 +1233,7 @@ static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_mmss_noc_cfg_ahb_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &config_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
-+ .flags = CLK_IGNORE_UNUSED,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -1465,11 +1396,6 @@ static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_usb_phy_cfg_ahb2phy_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &periph_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -1499,11 +1425,6 @@ static struct clk_branch gcc_sdcc1_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_sdcc1_ahb_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &periph_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -1550,11 +1471,6 @@ static struct clk_branch gcc_sdcc2_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_sdcc2_ahb_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &periph_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -1584,11 +1500,6 @@ static struct clk_branch gcc_sdcc3_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_sdcc3_ahb_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &periph_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -1618,11 +1529,6 @@ static struct clk_branch gcc_sdcc4_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_sdcc4_ahb_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &periph_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -1636,11 +1542,6 @@ static struct clk_branch gcc_blsp1_ahb_clk = {
- .enable_mask = BIT(17),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_ahb_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &periph_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -1978,11 +1879,6 @@ static struct clk_branch gcc_blsp2_ahb_clk = {
- .enable_mask = BIT(15),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp2_ahb_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &periph_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -2319,11 +2215,6 @@ static struct clk_branch gcc_pdm_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pdm_ahb_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &periph_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -2354,11 +2245,6 @@ static struct clk_branch gcc_prng_ahb_clk = {
- .enable_mask = BIT(13),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_prng_ahb_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &config_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -2371,11 +2257,6 @@ static struct clk_branch gcc_tsif_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_tsif_ahb_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &periph_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -2423,11 +2304,6 @@ static struct clk_branch gcc_boot_rom_ahb_clk = {
- .enable_mask = BIT(10),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_boot_rom_ahb_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &config_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -2521,11 +2397,6 @@ static struct clk_branch gcc_pcie_0_slv_axi_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie_0_slv_axi_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &system_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -2538,11 +2409,6 @@ static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie_0_mstr_axi_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &system_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -2555,11 +2421,6 @@ static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie_0_cfg_ahb_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &config_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -2607,11 +2468,6 @@ static struct clk_branch gcc_pcie_1_slv_axi_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie_1_slv_axi_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &system_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -2624,11 +2480,6 @@ static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie_1_mstr_axi_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &system_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -2641,11 +2492,6 @@ static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie_1_cfg_ahb_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &config_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -2693,11 +2539,6 @@ static struct clk_branch gcc_pcie_2_slv_axi_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie_2_slv_axi_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &system_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -2710,11 +2551,6 @@ static struct clk_branch gcc_pcie_2_mstr_axi_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie_2_mstr_axi_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &system_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -2727,11 +2563,6 @@ static struct clk_branch gcc_pcie_2_cfg_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie_2_cfg_ahb_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &config_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -2779,11 +2610,6 @@ static struct clk_branch gcc_pcie_phy_cfg_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie_phy_cfg_ahb_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &config_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -2830,11 +2656,6 @@ static struct clk_branch gcc_ufs_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_ufs_ahb_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &config_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -3061,11 +2882,7 @@ static struct clk_branch gcc_aggre0_snoc_axi_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_aggre0_snoc_axi_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &system_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
-+ .flags = CLK_IS_CRITICAL,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -3078,11 +2895,7 @@ static struct clk_branch gcc_aggre0_cnoc_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_aggre0_cnoc_ahb_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &config_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
-+ .flags = CLK_IS_CRITICAL,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -3095,11 +2908,7 @@ static struct clk_branch gcc_smmu_aggre0_axi_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_smmu_aggre0_axi_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &system_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
-+ .flags = CLK_IS_CRITICAL,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -3112,11 +2921,7 @@ static struct clk_branch gcc_smmu_aggre0_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_smmu_aggre0_ahb_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &config_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
-+ .flags = CLK_IS_CRITICAL,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -3163,10 +2968,6 @@ static struct clk_branch gcc_dcc_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_dcc_ahb_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &config_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -3179,10 +2980,6 @@ static struct clk_branch gcc_aggre0_noc_mpu_cfg_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_aggre0_noc_mpu_cfg_ahb_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &config_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -3195,11 +2992,6 @@ static struct clk_branch gcc_qspi_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_qspi_ahb_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &periph_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -3327,10 +3119,6 @@ static struct clk_branch gcc_mss_cfg_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_mss_cfg_ahb_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &config_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -3343,10 +3131,6 @@ static struct clk_branch gcc_mss_mnoc_bimc_axi_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_mss_mnoc_bimc_axi_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &system_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -3359,10 +3143,6 @@ static struct clk_branch gcc_mss_snoc_axi_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_mss_snoc_axi_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &system_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -3375,10 +3155,6 @@ static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_mss_q6_bimc_axi_clk",
-- .parent_hws = (const struct clk_hw*[]){
-- &system_noc_clk_src.clkr.hw,
-- },
-- .num_parents = 1,
- .ops = &clk_branch2_ops,
- },
- },
-@@ -3474,9 +3250,6 @@ static struct clk_regmap *gcc_msm8996_clocks[] = {
- [GPLL0] = &gpll0.clkr,
- [GPLL4_EARLY] = &gpll4_early.clkr,
- [GPLL4] = &gpll4.clkr,
-- [SYSTEM_NOC_CLK_SRC] = &system_noc_clk_src.clkr,
-- [CONFIG_NOC_CLK_SRC] = &config_noc_clk_src.clkr,
-- [PERIPH_NOC_CLK_SRC] = &periph_noc_clk_src.clkr,
- [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
- [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
- [USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr,
---
-2.42.0
-
+++ /dev/null
-From 5f8aed0d7f81c54b02a0bdfeafa52efbdd75ec72 Mon Sep 17 00:00:00 2001
-From: Sasha Levin <sashal@kernel.org>
-Date: Tue, 28 Dec 2021 07:54:11 +0300
-Subject: clk: qcom: gcc-msm8996: use ARRAY_SIZE instead of specifying
- num_parents
-
-From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-
-[ Upstream commit ed96df3d461eeb2c40cb06ca5fd51644d0f4a2c0 ]
-
-Use ARRAY_SIZE() instead of manually specifying num_parents. This makes
-adding/removing entries to/from parent_data easy and errorproof.
-
-Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Link: https://lore.kernel.org/r/20211228045415.20543-13-dmitry.baryshkov@linaro.org
-Stable-dep-of: 4afda5f6bcdf ("clk: qcom: gcc-msm8996: Remove RPM bus clocks")
-Signed-off-by: Sasha Levin <sashal@kernel.org>
----
- drivers/clk/qcom/gcc-msm8996.c | 122 ++++++++++++++++-----------------
- 1 file changed, 61 insertions(+), 61 deletions(-)
-
-diff --git a/drivers/clk/qcom/gcc-msm8996.c b/drivers/clk/qcom/gcc-msm8996.c
-index c1e1148f0261d..bb6bf4f1476f1 100644
---- a/drivers/clk/qcom/gcc-msm8996.c
-+++ b/drivers/clk/qcom/gcc-msm8996.c
-@@ -290,7 +290,7 @@ static struct clk_rcg2 system_noc_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "system_noc_clk_src",
- .parent_names = gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div,
-- .num_parents = 7,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -310,7 +310,7 @@ static struct clk_rcg2 config_noc_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "config_noc_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -332,7 +332,7 @@ static struct clk_rcg2 periph_noc_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "periph_noc_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -353,7 +353,7 @@ static struct clk_rcg2 usb30_master_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "usb30_master_clk_src",
- .parent_names = gcc_xo_gpll0_gpll0_early_div,
-- .num_parents = 3,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -371,7 +371,7 @@ static struct clk_rcg2 usb30_mock_utmi_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "usb30_mock_utmi_clk_src",
- .parent_names = gcc_xo_gpll0_gpll0_early_div,
-- .num_parents = 3,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -389,7 +389,7 @@ static struct clk_rcg2 usb3_phy_aux_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "usb3_phy_aux_clk_src",
- .parent_names = gcc_xo_sleep_clk,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_sleep_clk),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -408,7 +408,7 @@ static struct clk_rcg2 usb20_master_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "usb20_master_clk_src",
- .parent_names = gcc_xo_gpll0_gpll0_early_div,
-- .num_parents = 3,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -421,7 +421,7 @@ static struct clk_rcg2 usb20_mock_utmi_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "usb20_mock_utmi_clk_src",
- .parent_names = gcc_xo_gpll0_gpll0_early_div,
-- .num_parents = 3,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -447,7 +447,7 @@ static struct clk_rcg2 sdcc1_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "sdcc1_apps_clk_src",
- .parent_names = gcc_xo_gpll0_gpll4_gpll0_early_div,
-- .num_parents = 4,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_gpll0_early_div),
- .ops = &clk_rcg2_floor_ops,
- },
- };
-@@ -467,7 +467,7 @@ static struct clk_rcg2 sdcc1_ice_core_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "sdcc1_ice_core_clk_src",
- .parent_names = gcc_xo_gpll0_gpll4_gpll0_early_div,
-- .num_parents = 4,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_gpll0_early_div),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -492,7 +492,7 @@ static struct clk_rcg2 sdcc2_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "sdcc2_apps_clk_src",
- .parent_names = gcc_xo_gpll0_gpll4,
-- .num_parents = 3,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
- .ops = &clk_rcg2_floor_ops,
- },
- };
-@@ -506,7 +506,7 @@ static struct clk_rcg2 sdcc3_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "sdcc3_apps_clk_src",
- .parent_names = gcc_xo_gpll0_gpll4,
-- .num_parents = 3,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
- .ops = &clk_rcg2_floor_ops,
- },
- };
-@@ -530,7 +530,7 @@ static struct clk_rcg2 sdcc4_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "sdcc4_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_floor_ops,
- },
- };
-@@ -555,7 +555,7 @@ static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup1_spi_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -574,7 +574,7 @@ static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup1_i2c_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -607,7 +607,7 @@ static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_uart1_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -621,7 +621,7 @@ static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup2_spi_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -634,7 +634,7 @@ static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup2_i2c_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -648,7 +648,7 @@ static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_uart2_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -662,7 +662,7 @@ static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup3_spi_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -675,7 +675,7 @@ static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup3_i2c_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -689,7 +689,7 @@ static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_uart3_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -703,7 +703,7 @@ static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup4_spi_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -716,7 +716,7 @@ static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup4_i2c_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -730,7 +730,7 @@ static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_uart4_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -744,7 +744,7 @@ static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup5_spi_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -757,7 +757,7 @@ static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup5_i2c_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -771,7 +771,7 @@ static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_uart5_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -785,7 +785,7 @@ static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup6_spi_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -798,7 +798,7 @@ static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup6_i2c_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -812,7 +812,7 @@ static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_uart6_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -826,7 +826,7 @@ static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_qup1_spi_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -839,7 +839,7 @@ static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_qup1_i2c_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -853,7 +853,7 @@ static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_uart1_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -867,7 +867,7 @@ static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_qup2_spi_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -880,7 +880,7 @@ static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_qup2_i2c_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -894,7 +894,7 @@ static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_uart2_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -908,7 +908,7 @@ static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_qup3_spi_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -921,7 +921,7 @@ static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_qup3_i2c_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -935,7 +935,7 @@ static struct clk_rcg2 blsp2_uart3_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_uart3_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -949,7 +949,7 @@ static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_qup4_spi_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -962,7 +962,7 @@ static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_qup4_i2c_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -976,7 +976,7 @@ static struct clk_rcg2 blsp2_uart4_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_uart4_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -990,7 +990,7 @@ static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_qup5_spi_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1003,7 +1003,7 @@ static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_qup5_i2c_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1017,7 +1017,7 @@ static struct clk_rcg2 blsp2_uart5_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_uart5_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1031,7 +1031,7 @@ static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_qup6_spi_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1044,7 +1044,7 @@ static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_qup6_i2c_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1058,7 +1058,7 @@ static struct clk_rcg2 blsp2_uart6_apps_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_uart6_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1076,7 +1076,7 @@ static struct clk_rcg2 pdm2_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "pdm2_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1095,7 +1095,7 @@ static struct clk_rcg2 tsif_ref_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "tsif_ref_clk_src",
- .parent_names = gcc_xo_gpll0_aud_ref_clk,
-- .num_parents = 3,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_aud_ref_clk),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1107,7 +1107,7 @@ static struct clk_rcg2 gcc_sleep_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "gcc_sleep_clk_src",
- .parent_names = gcc_sleep_clk,
-- .num_parents = 1,
-+ .num_parents = ARRAY_SIZE(gcc_sleep_clk),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1120,7 +1120,7 @@ static struct clk_rcg2 hmss_rbcpr_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "hmss_rbcpr_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1132,7 +1132,7 @@ static struct clk_rcg2 hmss_gpll0_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "hmss_gpll0_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1153,7 +1153,7 @@ static struct clk_rcg2 gp1_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "gp1_clk_src",
- .parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
-- .num_parents = 4,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk_gpll0_early_div),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1167,7 +1167,7 @@ static struct clk_rcg2 gp2_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "gp2_clk_src",
- .parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
-- .num_parents = 4,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk_gpll0_early_div),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1181,7 +1181,7 @@ static struct clk_rcg2 gp3_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "gp3_clk_src",
- .parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
-- .num_parents = 4,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk_gpll0_early_div),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1200,7 +1200,7 @@ static struct clk_rcg2 pcie_aux_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "pcie_aux_clk_src",
- .parent_names = gcc_xo_sleep_clk,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_sleep_clk),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1221,7 +1221,7 @@ static struct clk_rcg2 ufs_axi_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "ufs_axi_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1241,7 +1241,7 @@ static struct clk_rcg2 ufs_ice_core_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "ufs_ice_core_clk_src",
- .parent_names = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1262,7 +1262,7 @@ static struct clk_rcg2 qspi_ser_clk_src = {
- .clkr.hw.init = &(struct clk_init_data){
- .name = "qspi_ser_clk_src",
- .parent_names = gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div,
-- .num_parents = 6,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div),
- .ops = &clk_rcg2_ops,
- },
- };
---
-2.42.0
-
+++ /dev/null
-From 147b6cc83355ffcb7ced885e9f034132c6264389 Mon Sep 17 00:00:00 2001
-From: Sasha Levin <sashal@kernel.org>
-Date: Tue, 28 Dec 2021 07:54:14 +0300
-Subject: clk: qcom: gcc-msm8996: use parent_hws/_data instead of parent_names
-
-From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-
-[ Upstream commit b3867679d460d67aaef5aa76e4512197a5375514 ]
-
-Convert the clock driver to specify parent data rather than parent
-names, to actually bind using 'clock-names' specified in the DTS rather
-than global clock names. Use parent_hws where possible to refer parent
-clocks directly, skipping the lookup.
-
-Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Link: https://lore.kernel.org/r/20211228045415.20543-16-dmitry.baryshkov@linaro.org
-Stable-dep-of: 4afda5f6bcdf ("clk: qcom: gcc-msm8996: Remove RPM bus clocks")
-Signed-off-by: Sasha Levin <sashal@kernel.org>
----
- drivers/clk/qcom/gcc-msm8996.c | 678 ++++++++++++++++++++++-----------
- 1 file changed, 463 insertions(+), 215 deletions(-)
-
-diff --git a/drivers/clk/qcom/gcc-msm8996.c b/drivers/clk/qcom/gcc-msm8996.c
-index dbfbdef4044c7..5b5ee4b7ae81f 100644
---- a/drivers/clk/qcom/gcc-msm8996.c
-+++ b/drivers/clk/qcom/gcc-msm8996.c
-@@ -38,7 +38,9 @@ static struct clk_fixed_factor xo = {
- .div = 1,
- .hw.init = &(struct clk_init_data){
- .name = "xo",
-- .parent_names = (const char *[]){ "xo_board" },
-+ .parent_data = &(const struct clk_parent_data){
-+ .fw_name = "cxo", .name = "xo_board",
-+ },
- .num_parents = 1,
- .ops = &clk_fixed_factor_ops,
- },
-@@ -52,7 +54,9 @@ static struct clk_alpha_pll gpll0_early = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gpll0_early",
-- .parent_names = (const char *[]){ "xo" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &xo.hw,
-+ },
- .num_parents = 1,
- .ops = &clk_alpha_pll_ops,
- },
-@@ -64,7 +68,9 @@ static struct clk_fixed_factor gpll0_early_div = {
- .div = 2,
- .hw.init = &(struct clk_init_data){
- .name = "gpll0_early_div",
-- .parent_names = (const char *[]){ "gpll0_early" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &gpll0_early.clkr.hw,
-+ },
- .num_parents = 1,
- .ops = &clk_fixed_factor_ops,
- },
-@@ -75,7 +81,9 @@ static struct clk_alpha_pll_postdiv gpll0 = {
- .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
- .clkr.hw.init = &(struct clk_init_data){
- .name = "gpll0",
-- .parent_names = (const char *[]){ "gpll0_early" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &gpll0_early.clkr.hw,
-+ },
- .num_parents = 1,
- .ops = &clk_alpha_pll_postdiv_ops,
- },
-@@ -88,7 +96,9 @@ static struct clk_branch gcc_mmss_gpll0_div_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_mmss_gpll0_div_clk",
-- .parent_names = (const char *[]){ "gpll0" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &gpll0.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -103,7 +113,9 @@ static struct clk_branch gcc_mss_gpll0_div_clk = {
- .enable_mask = BIT(2),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_mss_gpll0_div_clk",
-- .parent_names = (const char *[]){ "gpll0" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &gpll0.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops
-@@ -119,7 +131,9 @@ static struct clk_alpha_pll gpll4_early = {
- .enable_mask = BIT(4),
- .hw.init = &(struct clk_init_data){
- .name = "gpll4_early",
-- .parent_names = (const char *[]){ "xo" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &xo.hw,
-+ },
- .num_parents = 1,
- .ops = &clk_alpha_pll_ops,
- },
-@@ -131,7 +145,9 @@ static struct clk_alpha_pll_postdiv gpll4 = {
- .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
- .clkr.hw.init = &(struct clk_init_data){
- .name = "gpll4",
-- .parent_names = (const char *[]){ "gpll4_early" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &gpll4_early.clkr.hw,
-+ },
- .num_parents = 1,
- .ops = &clk_alpha_pll_postdiv_ops,
- },
-@@ -141,8 +157,8 @@ static const struct parent_map gcc_sleep_clk_map[] = {
- { P_SLEEP_CLK, 5 }
- };
-
--static const char * const gcc_sleep_clk[] = {
-- "sleep_clk"
-+static const struct clk_parent_data gcc_sleep_clk[] = {
-+ { .fw_name = "sleep_clk", .name = "sleep_clk" }
- };
-
- static const struct parent_map gcc_xo_gpll0_map[] = {
-@@ -150,9 +166,9 @@ static const struct parent_map gcc_xo_gpll0_map[] = {
- { P_GPLL0, 1 }
- };
-
--static const char * const gcc_xo_gpll0[] = {
-- "xo",
-- "gpll0"
-+static const struct clk_parent_data gcc_xo_gpll0[] = {
-+ { .hw = &xo.hw },
-+ { .hw = &gpll0.clkr.hw }
- };
-
- static const struct parent_map gcc_xo_sleep_clk_map[] = {
-@@ -160,9 +176,9 @@ static const struct parent_map gcc_xo_sleep_clk_map[] = {
- { P_SLEEP_CLK, 5 }
- };
-
--static const char * const gcc_xo_sleep_clk[] = {
-- "xo",
-- "sleep_clk"
-+static const struct clk_parent_data gcc_xo_sleep_clk[] = {
-+ { .hw = &xo.hw },
-+ { .fw_name = "sleep_clk", .name = "sleep_clk" }
- };
-
- static const struct parent_map gcc_xo_gpll0_gpll0_early_div_map[] = {
-@@ -171,10 +187,10 @@ static const struct parent_map gcc_xo_gpll0_gpll0_early_div_map[] = {
- { P_GPLL0_EARLY_DIV, 6 }
- };
-
--static const char * const gcc_xo_gpll0_gpll0_early_div[] = {
-- "xo",
-- "gpll0",
-- "gpll0_early_div"
-+static const struct clk_parent_data gcc_xo_gpll0_gpll0_early_div[] = {
-+ { .hw = &xo.hw },
-+ { .hw = &gpll0.clkr.hw },
-+ { .hw = &gpll0_early_div.hw }
- };
-
- static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
-@@ -183,10 +199,10 @@ static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
- { P_GPLL4, 5 }
- };
-
--static const char * const gcc_xo_gpll0_gpll4[] = {
-- "xo",
-- "gpll0",
-- "gpll4"
-+static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = {
-+ { .hw = &xo.hw },
-+ { .hw = &gpll0.clkr.hw },
-+ { .hw = &gpll4.clkr.hw }
- };
-
- static const struct parent_map gcc_xo_gpll0_aud_ref_clk_map[] = {
-@@ -195,10 +211,10 @@ static const struct parent_map gcc_xo_gpll0_aud_ref_clk_map[] = {
- { P_AUD_REF_CLK, 2 }
- };
-
--static const char * const gcc_xo_gpll0_aud_ref_clk[] = {
-- "xo",
-- "gpll0",
-- "aud_ref_clk"
-+static const struct clk_parent_data gcc_xo_gpll0_aud_ref_clk[] = {
-+ { .hw = &xo.hw },
-+ { .hw = &gpll0.clkr.hw },
-+ { .fw_name = "aud_ref_clk", .name = "aud_ref_clk" }
- };
-
- static const struct parent_map gcc_xo_gpll0_sleep_clk_gpll0_early_div_map[] = {
-@@ -208,11 +224,11 @@ static const struct parent_map gcc_xo_gpll0_sleep_clk_gpll0_early_div_map[] = {
- { P_GPLL0_EARLY_DIV, 6 }
- };
-
--static const char * const gcc_xo_gpll0_sleep_clk_gpll0_early_div[] = {
-- "xo",
-- "gpll0",
-- "sleep_clk",
-- "gpll0_early_div"
-+static const struct clk_parent_data gcc_xo_gpll0_sleep_clk_gpll0_early_div[] = {
-+ { .hw = &xo.hw },
-+ { .hw = &gpll0.clkr.hw },
-+ { .fw_name = "sleep_clk", .name = "sleep_clk" },
-+ { .hw = &gpll0_early_div.hw }
- };
-
- static const struct parent_map gcc_xo_gpll0_gpll4_gpll0_early_div_map[] = {
-@@ -222,11 +238,11 @@ static const struct parent_map gcc_xo_gpll0_gpll4_gpll0_early_div_map[] = {
- { P_GPLL0_EARLY_DIV, 6 }
- };
-
--static const char * const gcc_xo_gpll0_gpll4_gpll0_early_div[] = {
-- "xo",
-- "gpll0",
-- "gpll4",
-- "gpll0_early_div"
-+static const struct clk_parent_data gcc_xo_gpll0_gpll4_gpll0_early_div[] = {
-+ { .hw = &xo.hw },
-+ { .hw = &gpll0.clkr.hw },
-+ { .hw = &gpll4.clkr.hw },
-+ { .hw = &gpll0_early_div.hw }
- };
-
- static const struct freq_tbl ftbl_system_noc_clk_src[] = {
-@@ -246,7 +262,7 @@ static struct clk_rcg2 system_noc_clk_src = {
- .freq_tbl = ftbl_system_noc_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "system_noc_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll0_early_div,
-+ .parent_data = gcc_xo_gpll0_gpll0_early_div,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div),
- .ops = &clk_rcg2_ops,
- },
-@@ -266,7 +282,7 @@ static struct clk_rcg2 config_noc_clk_src = {
- .freq_tbl = ftbl_config_noc_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "config_noc_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -288,7 +304,7 @@ static struct clk_rcg2 periph_noc_clk_src = {
- .freq_tbl = ftbl_periph_noc_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "periph_noc_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -309,7 +325,7 @@ static struct clk_rcg2 usb30_master_clk_src = {
- .freq_tbl = ftbl_usb30_master_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "usb30_master_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll0_early_div,
-+ .parent_data = gcc_xo_gpll0_gpll0_early_div,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div),
- .ops = &clk_rcg2_ops,
- },
-@@ -327,7 +343,7 @@ static struct clk_rcg2 usb30_mock_utmi_clk_src = {
- .freq_tbl = ftbl_usb30_mock_utmi_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "usb30_mock_utmi_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll0_early_div,
-+ .parent_data = gcc_xo_gpll0_gpll0_early_div,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div),
- .ops = &clk_rcg2_ops,
- },
-@@ -345,7 +361,7 @@ static struct clk_rcg2 usb3_phy_aux_clk_src = {
- .freq_tbl = ftbl_usb3_phy_aux_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "usb3_phy_aux_clk_src",
-- .parent_names = gcc_xo_sleep_clk,
-+ .parent_data = gcc_xo_sleep_clk,
- .num_parents = ARRAY_SIZE(gcc_xo_sleep_clk),
- .ops = &clk_rcg2_ops,
- },
-@@ -364,7 +380,7 @@ static struct clk_rcg2 usb20_master_clk_src = {
- .freq_tbl = ftbl_usb20_master_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "usb20_master_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll0_early_div,
-+ .parent_data = gcc_xo_gpll0_gpll0_early_div,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div),
- .ops = &clk_rcg2_ops,
- },
-@@ -377,7 +393,7 @@ static struct clk_rcg2 usb20_mock_utmi_clk_src = {
- .freq_tbl = ftbl_usb30_mock_utmi_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "usb20_mock_utmi_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll0_early_div,
-+ .parent_data = gcc_xo_gpll0_gpll0_early_div,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div),
- .ops = &clk_rcg2_ops,
- },
-@@ -403,7 +419,7 @@ static struct clk_rcg2 sdcc1_apps_clk_src = {
- .freq_tbl = ftbl_sdcc1_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "sdcc1_apps_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll4_gpll0_early_div,
-+ .parent_data = gcc_xo_gpll0_gpll4_gpll0_early_div,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_gpll0_early_div),
- .ops = &clk_rcg2_floor_ops,
- },
-@@ -423,7 +439,7 @@ static struct clk_rcg2 sdcc1_ice_core_clk_src = {
- .freq_tbl = ftbl_sdcc1_ice_core_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "sdcc1_ice_core_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll4_gpll0_early_div,
-+ .parent_data = gcc_xo_gpll0_gpll4_gpll0_early_div,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_gpll0_early_div),
- .ops = &clk_rcg2_ops,
- },
-@@ -448,7 +464,7 @@ static struct clk_rcg2 sdcc2_apps_clk_src = {
- .freq_tbl = ftbl_sdcc2_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "sdcc2_apps_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll4,
-+ .parent_data = gcc_xo_gpll0_gpll4,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
- .ops = &clk_rcg2_floor_ops,
- },
-@@ -462,7 +478,7 @@ static struct clk_rcg2 sdcc3_apps_clk_src = {
- .freq_tbl = ftbl_sdcc2_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "sdcc3_apps_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll4,
-+ .parent_data = gcc_xo_gpll0_gpll4,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
- .ops = &clk_rcg2_floor_ops,
- },
-@@ -486,7 +502,7 @@ static struct clk_rcg2 sdcc4_apps_clk_src = {
- .freq_tbl = ftbl_sdcc4_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "sdcc4_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_floor_ops,
- },
-@@ -511,7 +527,7 @@ static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup1_spi_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -530,7 +546,7 @@ static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup1_i2c_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -563,7 +579,7 @@ static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_uart1_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -577,7 +593,7 @@ static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup2_spi_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -590,7 +606,7 @@ static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup2_i2c_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -604,7 +620,7 @@ static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_uart2_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -618,7 +634,7 @@ static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup3_spi_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -631,7 +647,7 @@ static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup3_i2c_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -645,7 +661,7 @@ static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_uart3_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -659,7 +675,7 @@ static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup4_spi_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -672,7 +688,7 @@ static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup4_i2c_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -686,7 +702,7 @@ static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_uart4_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -700,7 +716,7 @@ static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup5_spi_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -713,7 +729,7 @@ static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup5_i2c_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -727,7 +743,7 @@ static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_uart5_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -741,7 +757,7 @@ static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup6_spi_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -754,7 +770,7 @@ static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup6_i2c_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -768,7 +784,7 @@ static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_uart6_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -782,7 +798,7 @@ static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_qup1_spi_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -795,7 +811,7 @@ static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_qup1_i2c_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -809,7 +825,7 @@ static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_uart1_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -823,7 +839,7 @@ static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_qup2_spi_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -836,7 +852,7 @@ static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_qup2_i2c_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -850,7 +866,7 @@ static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_uart2_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -864,7 +880,7 @@ static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_qup3_spi_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -877,7 +893,7 @@ static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_qup3_i2c_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -891,7 +907,7 @@ static struct clk_rcg2 blsp2_uart3_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_uart3_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -905,7 +921,7 @@ static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_qup4_spi_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -918,7 +934,7 @@ static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_qup4_i2c_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -932,7 +948,7 @@ static struct clk_rcg2 blsp2_uart4_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_uart4_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -946,7 +962,7 @@ static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_qup5_spi_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -959,7 +975,7 @@ static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_qup5_i2c_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -973,7 +989,7 @@ static struct clk_rcg2 blsp2_uart5_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_uart5_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -987,7 +1003,7 @@ static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_qup6_spi_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -1000,7 +1016,7 @@ static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_qup6_i2c_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -1014,7 +1030,7 @@ static struct clk_rcg2 blsp2_uart6_apps_clk_src = {
- .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_uart6_apps_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -1032,7 +1048,7 @@ static struct clk_rcg2 pdm2_clk_src = {
- .freq_tbl = ftbl_pdm2_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "pdm2_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -1051,7 +1067,7 @@ static struct clk_rcg2 tsif_ref_clk_src = {
- .freq_tbl = ftbl_tsif_ref_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "tsif_ref_clk_src",
-- .parent_names = gcc_xo_gpll0_aud_ref_clk,
-+ .parent_data = gcc_xo_gpll0_aud_ref_clk,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_aud_ref_clk),
- .ops = &clk_rcg2_ops,
- },
-@@ -1063,7 +1079,7 @@ static struct clk_rcg2 gcc_sleep_clk_src = {
- .parent_map = gcc_sleep_clk_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "gcc_sleep_clk_src",
-- .parent_names = gcc_sleep_clk,
-+ .parent_data = gcc_sleep_clk,
- .num_parents = ARRAY_SIZE(gcc_sleep_clk),
- .ops = &clk_rcg2_ops,
- },
-@@ -1076,7 +1092,7 @@ static struct clk_rcg2 hmss_rbcpr_clk_src = {
- .freq_tbl = ftbl_usb30_mock_utmi_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "hmss_rbcpr_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -1088,7 +1104,7 @@ static struct clk_rcg2 hmss_gpll0_clk_src = {
- .parent_map = gcc_xo_gpll0_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "hmss_gpll0_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -1109,7 +1125,7 @@ static struct clk_rcg2 gp1_clk_src = {
- .freq_tbl = ftbl_gp1_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "gp1_clk_src",
-- .parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
-+ .parent_data = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk_gpll0_early_div),
- .ops = &clk_rcg2_ops,
- },
-@@ -1123,7 +1139,7 @@ static struct clk_rcg2 gp2_clk_src = {
- .freq_tbl = ftbl_gp1_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "gp2_clk_src",
-- .parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
-+ .parent_data = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk_gpll0_early_div),
- .ops = &clk_rcg2_ops,
- },
-@@ -1137,7 +1153,7 @@ static struct clk_rcg2 gp3_clk_src = {
- .freq_tbl = ftbl_gp1_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "gp3_clk_src",
-- .parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
-+ .parent_data = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk_gpll0_early_div),
- .ops = &clk_rcg2_ops,
- },
-@@ -1156,7 +1172,7 @@ static struct clk_rcg2 pcie_aux_clk_src = {
- .freq_tbl = ftbl_pcie_aux_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "pcie_aux_clk_src",
-- .parent_names = gcc_xo_sleep_clk,
-+ .parent_data = gcc_xo_sleep_clk,
- .num_parents = ARRAY_SIZE(gcc_xo_sleep_clk),
- .ops = &clk_rcg2_ops,
- },
-@@ -1177,7 +1193,7 @@ static struct clk_rcg2 ufs_axi_clk_src = {
- .freq_tbl = ftbl_ufs_axi_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "ufs_axi_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -1197,7 +1213,7 @@ static struct clk_rcg2 ufs_ice_core_clk_src = {
- .freq_tbl = ftbl_ufs_ice_core_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "ufs_ice_core_clk_src",
-- .parent_names = gcc_xo_gpll0,
-+ .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-@@ -1218,7 +1234,7 @@ static struct clk_rcg2 qspi_ser_clk_src = {
- .freq_tbl = ftbl_qspi_ser_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "qspi_ser_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll4_gpll0_early_div,
-+ .parent_data = gcc_xo_gpll0_gpll4_gpll0_early_div,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_gpll0_early_div),
- .ops = &clk_rcg2_ops,
- },
-@@ -1231,7 +1247,9 @@ static struct clk_branch gcc_sys_noc_usb3_axi_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_sys_noc_usb3_axi_clk",
-- .parent_names = (const char *[]){ "usb30_master_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &usb30_master_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1246,7 +1264,9 @@ static struct clk_branch gcc_sys_noc_ufs_axi_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_sys_noc_ufs_axi_clk",
-- .parent_names = (const char *[]){ "ufs_axi_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &ufs_axi_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1261,7 +1281,9 @@ static struct clk_branch gcc_periph_noc_usb20_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_periph_noc_usb20_ahb_clk",
-- .parent_names = (const char *[]){ "usb20_master_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &usb20_master_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1276,7 +1298,9 @@ static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_mmss_noc_cfg_ahb_clk",
-- .parent_names = (const char *[]){ "config_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &config_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
- .ops = &clk_branch2_ops,
-@@ -1304,7 +1328,9 @@ static struct clk_branch gcc_usb30_master_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_usb30_master_clk",
-- .parent_names = (const char *[]){ "usb30_master_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &usb30_master_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1319,7 +1345,9 @@ static struct clk_branch gcc_usb30_sleep_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_usb30_sleep_clk",
-- .parent_names = (const char *[]){ "gcc_sleep_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &gcc_sleep_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1334,7 +1362,9 @@ static struct clk_branch gcc_usb30_mock_utmi_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_usb30_mock_utmi_clk",
-- .parent_names = (const char *[]){ "usb30_mock_utmi_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &usb30_mock_utmi_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1349,7 +1379,9 @@ static struct clk_branch gcc_usb3_phy_aux_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_usb3_phy_aux_clk",
-- .parent_names = (const char *[]){ "usb3_phy_aux_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &usb3_phy_aux_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1365,7 +1397,9 @@ static struct clk_branch gcc_usb3_phy_pipe_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_usb3_phy_pipe_clk",
-- .parent_names = (const char *[]){ "usb3_phy_pipe_clk_src" },
-+ .parent_data = &(const struct clk_parent_data){
-+ .fw_name = "usb3_phy_pipe_clk_src", .name = "usb3_phy_pipe_clk_src",
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1380,7 +1414,9 @@ static struct clk_branch gcc_usb20_master_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_usb20_master_clk",
-- .parent_names = (const char *[]){ "usb20_master_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &usb20_master_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1395,7 +1431,9 @@ static struct clk_branch gcc_usb20_sleep_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_usb20_sleep_clk",
-- .parent_names = (const char *[]){ "gcc_sleep_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &gcc_sleep_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1410,7 +1448,9 @@ static struct clk_branch gcc_usb20_mock_utmi_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_usb20_mock_utmi_clk",
-- .parent_names = (const char *[]){ "usb20_mock_utmi_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &usb20_mock_utmi_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1425,7 +1465,9 @@ static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_usb_phy_cfg_ahb2phy_clk",
-- .parent_names = (const char *[]){ "periph_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &periph_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1440,7 +1482,9 @@ static struct clk_branch gcc_sdcc1_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_sdcc1_apps_clk",
-- .parent_names = (const char *[]){ "sdcc1_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &sdcc1_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1455,7 +1499,9 @@ static struct clk_branch gcc_sdcc1_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_sdcc1_ahb_clk",
-- .parent_names = (const char *[]){ "periph_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &periph_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1470,7 +1516,9 @@ static struct clk_branch gcc_sdcc1_ice_core_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_sdcc1_ice_core_clk",
-- .parent_names = (const char *[]){ "sdcc1_ice_core_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &sdcc1_ice_core_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1485,7 +1533,9 @@ static struct clk_branch gcc_sdcc2_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_sdcc2_apps_clk",
-- .parent_names = (const char *[]){ "sdcc2_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &sdcc2_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1500,7 +1550,9 @@ static struct clk_branch gcc_sdcc2_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_sdcc2_ahb_clk",
-- .parent_names = (const char *[]){ "periph_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &periph_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1515,7 +1567,9 @@ static struct clk_branch gcc_sdcc3_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_sdcc3_apps_clk",
-- .parent_names = (const char *[]){ "sdcc3_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &sdcc3_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1530,7 +1584,9 @@ static struct clk_branch gcc_sdcc3_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_sdcc3_ahb_clk",
-- .parent_names = (const char *[]){ "periph_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &periph_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1545,7 +1601,9 @@ static struct clk_branch gcc_sdcc4_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_sdcc4_apps_clk",
-- .parent_names = (const char *[]){ "sdcc4_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &sdcc4_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1560,7 +1618,9 @@ static struct clk_branch gcc_sdcc4_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_sdcc4_ahb_clk",
-- .parent_names = (const char *[]){ "periph_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &periph_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1576,7 +1636,9 @@ static struct clk_branch gcc_blsp1_ahb_clk = {
- .enable_mask = BIT(17),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_ahb_clk",
-- .parent_names = (const char *[]){ "periph_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &periph_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1592,7 +1654,9 @@ static struct clk_branch gcc_blsp1_sleep_clk = {
- .enable_mask = BIT(16),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_sleep_clk",
-- .parent_names = (const char *[]){ "gcc_sleep_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &gcc_sleep_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1607,7 +1671,9 @@ static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_qup1_spi_apps_clk",
-- .parent_names = (const char *[]){ "blsp1_qup1_spi_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp1_qup1_spi_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1622,7 +1688,9 @@ static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_qup1_i2c_apps_clk",
-- .parent_names = (const char *[]){ "blsp1_qup1_i2c_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp1_qup1_i2c_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1637,7 +1705,9 @@ static struct clk_branch gcc_blsp1_uart1_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_uart1_apps_clk",
-- .parent_names = (const char *[]){ "blsp1_uart1_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp1_uart1_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1652,7 +1722,9 @@ static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_qup2_spi_apps_clk",
-- .parent_names = (const char *[]){ "blsp1_qup2_spi_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp1_qup2_spi_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1667,7 +1739,9 @@ static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_qup2_i2c_apps_clk",
-- .parent_names = (const char *[]){ "blsp1_qup2_i2c_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp1_qup2_i2c_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1682,7 +1756,9 @@ static struct clk_branch gcc_blsp1_uart2_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_uart2_apps_clk",
-- .parent_names = (const char *[]){ "blsp1_uart2_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp1_uart2_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1697,7 +1773,9 @@ static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_qup3_spi_apps_clk",
-- .parent_names = (const char *[]){ "blsp1_qup3_spi_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp1_qup3_spi_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1712,7 +1790,9 @@ static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_qup3_i2c_apps_clk",
-- .parent_names = (const char *[]){ "blsp1_qup3_i2c_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp1_qup3_i2c_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1727,7 +1807,9 @@ static struct clk_branch gcc_blsp1_uart3_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_uart3_apps_clk",
-- .parent_names = (const char *[]){ "blsp1_uart3_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp1_uart3_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1742,7 +1824,9 @@ static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_qup4_spi_apps_clk",
-- .parent_names = (const char *[]){ "blsp1_qup4_spi_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp1_qup4_spi_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1757,7 +1841,9 @@ static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_qup4_i2c_apps_clk",
-- .parent_names = (const char *[]){ "blsp1_qup4_i2c_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp1_qup4_i2c_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1772,7 +1858,9 @@ static struct clk_branch gcc_blsp1_uart4_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_uart4_apps_clk",
-- .parent_names = (const char *[]){ "blsp1_uart4_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp1_uart4_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1787,7 +1875,9 @@ static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_qup5_spi_apps_clk",
-- .parent_names = (const char *[]){ "blsp1_qup5_spi_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp1_qup5_spi_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1802,7 +1892,9 @@ static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_qup5_i2c_apps_clk",
-- .parent_names = (const char *[]){ "blsp1_qup5_i2c_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp1_qup5_i2c_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1817,7 +1909,9 @@ static struct clk_branch gcc_blsp1_uart5_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_uart5_apps_clk",
-- .parent_names = (const char *[]){ "blsp1_uart5_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp1_uart5_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1832,7 +1926,9 @@ static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_qup6_spi_apps_clk",
-- .parent_names = (const char *[]){ "blsp1_qup6_spi_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp1_qup6_spi_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1847,7 +1943,9 @@ static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_qup6_i2c_apps_clk",
-- .parent_names = (const char *[]){ "blsp1_qup6_i2c_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp1_qup6_i2c_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1862,7 +1960,9 @@ static struct clk_branch gcc_blsp1_uart6_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_uart6_apps_clk",
-- .parent_names = (const char *[]){ "blsp1_uart6_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp1_uart6_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1878,7 +1978,9 @@ static struct clk_branch gcc_blsp2_ahb_clk = {
- .enable_mask = BIT(15),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp2_ahb_clk",
-- .parent_names = (const char *[]){ "periph_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &periph_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1894,7 +1996,9 @@ static struct clk_branch gcc_blsp2_sleep_clk = {
- .enable_mask = BIT(14),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp2_sleep_clk",
-- .parent_names = (const char *[]){ "gcc_sleep_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &gcc_sleep_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1909,7 +2013,9 @@ static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp2_qup1_spi_apps_clk",
-- .parent_names = (const char *[]){ "blsp2_qup1_spi_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp2_qup1_spi_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1924,7 +2030,9 @@ static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp2_qup1_i2c_apps_clk",
-- .parent_names = (const char *[]){ "blsp2_qup1_i2c_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp2_qup1_i2c_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1939,7 +2047,9 @@ static struct clk_branch gcc_blsp2_uart1_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp2_uart1_apps_clk",
-- .parent_names = (const char *[]){ "blsp2_uart1_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp2_uart1_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1954,7 +2064,9 @@ static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp2_qup2_spi_apps_clk",
-- .parent_names = (const char *[]){ "blsp2_qup2_spi_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp2_qup2_spi_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1969,7 +2081,9 @@ static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp2_qup2_i2c_apps_clk",
-- .parent_names = (const char *[]){ "blsp2_qup2_i2c_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp2_qup2_i2c_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1984,7 +2098,9 @@ static struct clk_branch gcc_blsp2_uart2_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp2_uart2_apps_clk",
-- .parent_names = (const char *[]){ "blsp2_uart2_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp2_uart2_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -1999,7 +2115,9 @@ static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp2_qup3_spi_apps_clk",
-- .parent_names = (const char *[]){ "blsp2_qup3_spi_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp2_qup3_spi_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2014,7 +2132,9 @@ static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp2_qup3_i2c_apps_clk",
-- .parent_names = (const char *[]){ "blsp2_qup3_i2c_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp2_qup3_i2c_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2029,7 +2149,9 @@ static struct clk_branch gcc_blsp2_uart3_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp2_uart3_apps_clk",
-- .parent_names = (const char *[]){ "blsp2_uart3_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp2_uart3_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2044,7 +2166,9 @@ static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp2_qup4_spi_apps_clk",
-- .parent_names = (const char *[]){ "blsp2_qup4_spi_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp2_qup4_spi_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2059,7 +2183,9 @@ static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp2_qup4_i2c_apps_clk",
-- .parent_names = (const char *[]){ "blsp2_qup4_i2c_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp2_qup4_i2c_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2074,7 +2200,9 @@ static struct clk_branch gcc_blsp2_uart4_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp2_uart4_apps_clk",
-- .parent_names = (const char *[]){ "blsp2_uart4_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp2_uart4_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2089,7 +2217,9 @@ static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp2_qup5_spi_apps_clk",
-- .parent_names = (const char *[]){ "blsp2_qup5_spi_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp2_qup5_spi_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2104,7 +2234,9 @@ static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp2_qup5_i2c_apps_clk",
-- .parent_names = (const char *[]){ "blsp2_qup5_i2c_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp2_qup5_i2c_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2119,7 +2251,9 @@ static struct clk_branch gcc_blsp2_uart5_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp2_uart5_apps_clk",
-- .parent_names = (const char *[]){ "blsp2_uart5_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp2_uart5_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2134,7 +2268,9 @@ static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp2_qup6_spi_apps_clk",
-- .parent_names = (const char *[]){ "blsp2_qup6_spi_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp2_qup6_spi_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2149,7 +2285,9 @@ static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp2_qup6_i2c_apps_clk",
-- .parent_names = (const char *[]){ "blsp2_qup6_i2c_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp2_qup6_i2c_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2164,7 +2302,9 @@ static struct clk_branch gcc_blsp2_uart6_apps_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp2_uart6_apps_clk",
-- .parent_names = (const char *[]){ "blsp2_uart6_apps_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &blsp2_uart6_apps_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2179,7 +2319,9 @@ static struct clk_branch gcc_pdm_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pdm_ahb_clk",
-- .parent_names = (const char *[]){ "periph_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &periph_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2194,7 +2336,9 @@ static struct clk_branch gcc_pdm2_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pdm2_clk",
-- .parent_names = (const char *[]){ "pdm2_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &pdm2_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2210,7 +2354,9 @@ static struct clk_branch gcc_prng_ahb_clk = {
- .enable_mask = BIT(13),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_prng_ahb_clk",
-- .parent_names = (const char *[]){ "config_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &config_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2225,7 +2371,9 @@ static struct clk_branch gcc_tsif_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_tsif_ahb_clk",
-- .parent_names = (const char *[]){ "periph_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &periph_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2240,7 +2388,9 @@ static struct clk_branch gcc_tsif_ref_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_tsif_ref_clk",
-- .parent_names = (const char *[]){ "tsif_ref_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &tsif_ref_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2255,7 +2405,9 @@ static struct clk_branch gcc_tsif_inactivity_timers_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_tsif_inactivity_timers_clk",
-- .parent_names = (const char *[]){ "gcc_sleep_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &gcc_sleep_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2271,7 +2423,9 @@ static struct clk_branch gcc_boot_rom_ahb_clk = {
- .enable_mask = BIT(10),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_boot_rom_ahb_clk",
-- .parent_names = (const char *[]){ "config_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &config_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2299,7 +2453,9 @@ static struct clk_branch gcc_hmss_rbcpr_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_hmss_rbcpr_clk",
-- .parent_names = (const char *[]){ "hmss_rbcpr_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &hmss_rbcpr_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2314,7 +2470,9 @@ static struct clk_branch gcc_gp1_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_gp1_clk",
-- .parent_names = (const char *[]){ "gp1_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &gp1_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2329,7 +2487,9 @@ static struct clk_branch gcc_gp2_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_gp2_clk",
-- .parent_names = (const char *[]){ "gp2_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &gp2_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2344,7 +2504,9 @@ static struct clk_branch gcc_gp3_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_gp3_clk",
-- .parent_names = (const char *[]){ "gp3_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &gp3_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2359,7 +2521,9 @@ static struct clk_branch gcc_pcie_0_slv_axi_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie_0_slv_axi_clk",
-- .parent_names = (const char *[]){ "system_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &system_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2374,7 +2538,9 @@ static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie_0_mstr_axi_clk",
-- .parent_names = (const char *[]){ "system_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &system_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2389,7 +2555,9 @@ static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie_0_cfg_ahb_clk",
-- .parent_names = (const char *[]){ "config_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &config_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2404,7 +2572,9 @@ static struct clk_branch gcc_pcie_0_aux_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie_0_aux_clk",
-- .parent_names = (const char *[]){ "pcie_aux_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &pcie_aux_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2420,7 +2590,9 @@ static struct clk_branch gcc_pcie_0_pipe_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie_0_pipe_clk",
-- .parent_names = (const char *[]){ "pcie_0_pipe_clk_src" },
-+ .parent_data = &(const struct clk_parent_data){
-+ .fw_name = "pcie_0_pipe_clk_src", .name = "pcie_0_pipe_clk_src",
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2435,7 +2607,9 @@ static struct clk_branch gcc_pcie_1_slv_axi_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie_1_slv_axi_clk",
-- .parent_names = (const char *[]){ "system_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &system_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2450,7 +2624,9 @@ static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie_1_mstr_axi_clk",
-- .parent_names = (const char *[]){ "system_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &system_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2465,7 +2641,9 @@ static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie_1_cfg_ahb_clk",
-- .parent_names = (const char *[]){ "config_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &config_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2480,7 +2658,9 @@ static struct clk_branch gcc_pcie_1_aux_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie_1_aux_clk",
-- .parent_names = (const char *[]){ "pcie_aux_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &pcie_aux_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2496,7 +2676,9 @@ static struct clk_branch gcc_pcie_1_pipe_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie_1_pipe_clk",
-- .parent_names = (const char *[]){ "pcie_1_pipe_clk_src" },
-+ .parent_data = &(const struct clk_parent_data){
-+ .fw_name = "pcie_1_pipe_clk_src", .name = "pcie_1_pipe_clk_src",
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2511,7 +2693,9 @@ static struct clk_branch gcc_pcie_2_slv_axi_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie_2_slv_axi_clk",
-- .parent_names = (const char *[]){ "system_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &system_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2526,7 +2710,9 @@ static struct clk_branch gcc_pcie_2_mstr_axi_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie_2_mstr_axi_clk",
-- .parent_names = (const char *[]){ "system_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &system_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2541,7 +2727,9 @@ static struct clk_branch gcc_pcie_2_cfg_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie_2_cfg_ahb_clk",
-- .parent_names = (const char *[]){ "config_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &config_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2556,7 +2744,9 @@ static struct clk_branch gcc_pcie_2_aux_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie_2_aux_clk",
-- .parent_names = (const char *[]){ "pcie_aux_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &pcie_aux_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2572,7 +2762,9 @@ static struct clk_branch gcc_pcie_2_pipe_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie_2_pipe_clk",
-- .parent_names = (const char *[]){ "pcie_2_pipe_clk_src" },
-+ .parent_data = &(const struct clk_parent_data){
-+ .fw_name = "pcie_2_pipe_clk_src", .name = "pcie_2_pipe_clk_src",
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2587,7 +2779,9 @@ static struct clk_branch gcc_pcie_phy_cfg_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie_phy_cfg_ahb_clk",
-- .parent_names = (const char *[]){ "config_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &config_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2602,7 +2796,9 @@ static struct clk_branch gcc_pcie_phy_aux_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie_phy_aux_clk",
-- .parent_names = (const char *[]){ "pcie_aux_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &pcie_aux_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2617,7 +2813,9 @@ static struct clk_branch gcc_ufs_axi_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_ufs_axi_clk",
-- .parent_names = (const char *[]){ "ufs_axi_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &ufs_axi_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2632,7 +2830,9 @@ static struct clk_branch gcc_ufs_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_ufs_ahb_clk",
-- .parent_names = (const char *[]){ "config_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &config_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2645,7 +2845,9 @@ static struct clk_fixed_factor ufs_tx_cfg_clk_src = {
- .div = 16,
- .hw.init = &(struct clk_init_data){
- .name = "ufs_tx_cfg_clk_src",
-- .parent_names = (const char *[]){ "ufs_axi_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &ufs_axi_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_fixed_factor_ops,
-@@ -2659,7 +2861,9 @@ static struct clk_branch gcc_ufs_tx_cfg_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_ufs_tx_cfg_clk",
-- .parent_names = (const char *[]){ "ufs_tx_cfg_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &ufs_tx_cfg_clk_src.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2672,7 +2876,9 @@ static struct clk_fixed_factor ufs_rx_cfg_clk_src = {
- .div = 16,
- .hw.init = &(struct clk_init_data){
- .name = "ufs_rx_cfg_clk_src",
-- .parent_names = (const char *[]){ "ufs_axi_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &ufs_axi_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_fixed_factor_ops,
-@@ -2712,7 +2918,9 @@ static struct clk_branch gcc_ufs_rx_cfg_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_ufs_rx_cfg_clk",
-- .parent_names = (const char *[]){ "ufs_rx_cfg_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &ufs_rx_cfg_clk_src.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2728,7 +2936,9 @@ static struct clk_branch gcc_ufs_tx_symbol_0_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_ufs_tx_symbol_0_clk",
-- .parent_names = (const char *[]){ "ufs_tx_symbol_0_clk_src" },
-+ .parent_data = &(const struct clk_parent_data){
-+ .fw_name = "ufs_tx_symbol_0_clk_src", .name = "ufs_tx_symbol_0_clk_src",
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2744,7 +2954,9 @@ static struct clk_branch gcc_ufs_rx_symbol_0_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_ufs_rx_symbol_0_clk",
-- .parent_names = (const char *[]){ "ufs_rx_symbol_0_clk_src" },
-+ .parent_data = &(const struct clk_parent_data){
-+ .fw_name = "ufs_rx_symbol_0_clk_src", .name = "ufs_rx_symbol_0_clk_src",
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2760,7 +2972,9 @@ static struct clk_branch gcc_ufs_rx_symbol_1_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_ufs_rx_symbol_1_clk",
-- .parent_names = (const char *[]){ "ufs_rx_symbol_1_clk_src" },
-+ .parent_data = &(const struct clk_parent_data){
-+ .fw_name = "ufs_rx_symbol_1_clk_src", .name = "ufs_rx_symbol_1_clk_src",
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2773,7 +2987,9 @@ static struct clk_fixed_factor ufs_ice_core_postdiv_clk_src = {
- .div = 2,
- .hw.init = &(struct clk_init_data){
- .name = "ufs_ice_core_postdiv_clk_src",
-- .parent_names = (const char *[]){ "ufs_ice_core_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &ufs_ice_core_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_fixed_factor_ops,
-@@ -2787,7 +3003,9 @@ static struct clk_branch gcc_ufs_unipro_core_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_ufs_unipro_core_clk",
-- .parent_names = (const char *[]){ "ufs_ice_core_postdiv_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &ufs_ice_core_postdiv_clk_src.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2802,7 +3020,9 @@ static struct clk_branch gcc_ufs_ice_core_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_ufs_ice_core_clk",
-- .parent_names = (const char *[]){ "ufs_ice_core_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &ufs_ice_core_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2841,7 +3061,9 @@ static struct clk_branch gcc_aggre0_snoc_axi_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_aggre0_snoc_axi_clk",
-- .parent_names = (const char *[]){ "system_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &system_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
- .ops = &clk_branch2_ops,
-@@ -2856,7 +3078,9 @@ static struct clk_branch gcc_aggre0_cnoc_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_aggre0_cnoc_ahb_clk",
-- .parent_names = (const char *[]){ "config_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &config_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
- .ops = &clk_branch2_ops,
-@@ -2871,7 +3095,9 @@ static struct clk_branch gcc_smmu_aggre0_axi_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_smmu_aggre0_axi_clk",
-- .parent_names = (const char *[]){ "system_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &system_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
- .ops = &clk_branch2_ops,
-@@ -2886,7 +3112,9 @@ static struct clk_branch gcc_smmu_aggre0_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_smmu_aggre0_ahb_clk",
-- .parent_names = (const char *[]){ "config_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &config_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
- .ops = &clk_branch2_ops,
-@@ -2901,7 +3129,9 @@ static struct clk_branch gcc_aggre2_ufs_axi_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_aggre2_ufs_axi_clk",
-- .parent_names = (const char *[]){ "ufs_axi_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &ufs_axi_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2916,7 +3146,9 @@ static struct clk_branch gcc_aggre2_usb3_axi_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_aggre2_usb3_axi_clk",
-- .parent_names = (const char *[]){ "usb30_master_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &usb30_master_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2931,7 +3163,9 @@ static struct clk_branch gcc_dcc_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_dcc_ahb_clk",
-- .parent_names = (const char *[]){ "config_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &config_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .ops = &clk_branch2_ops,
- },
-@@ -2945,7 +3179,9 @@ static struct clk_branch gcc_aggre0_noc_mpu_cfg_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_aggre0_noc_mpu_cfg_ahb_clk",
-- .parent_names = (const char *[]){ "config_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &config_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .ops = &clk_branch2_ops,
- },
-@@ -2959,7 +3195,9 @@ static struct clk_branch gcc_qspi_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_qspi_ahb_clk",
-- .parent_names = (const char *[]){ "periph_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &periph_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2974,7 +3212,9 @@ static struct clk_branch gcc_qspi_ser_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_qspi_ser_clk",
-- .parent_names = (const char *[]){ "qspi_ser_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &qspi_ser_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3087,7 +3327,9 @@ static struct clk_branch gcc_mss_cfg_ahb_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_mss_cfg_ahb_clk",
-- .parent_names = (const char *[]){ "config_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &config_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .ops = &clk_branch2_ops,
- },
-@@ -3101,7 +3343,9 @@ static struct clk_branch gcc_mss_mnoc_bimc_axi_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_mss_mnoc_bimc_axi_clk",
-- .parent_names = (const char *[]){ "system_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &system_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .ops = &clk_branch2_ops,
- },
-@@ -3115,7 +3359,9 @@ static struct clk_branch gcc_mss_snoc_axi_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_mss_snoc_axi_clk",
-- .parent_names = (const char *[]){ "system_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &system_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .ops = &clk_branch2_ops,
- },
-@@ -3129,7 +3375,9 @@ static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_mss_q6_bimc_axi_clk",
-- .parent_names = (const char *[]){ "system_noc_clk_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &system_noc_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .ops = &clk_branch2_ops,
- },
---
-2.42.0
-
net-add-dev_stats_read-helper.patch
ipvlan-properly-track-tx_errors.patch
regmap-debugfs-fix-a-erroneous-check-after-snprintf.patch
-clk-qcom-gcc-msm8996-use-array_size-instead-of-speci.patch
-clk-qcom-gcc-msm8996-drop-unsupported-clock-sources.patch
-clk-qcom-gcc-msm8996-move-clock-parent-tables-down.patch
-clk-qcom-gcc-msm8996-use-parent_hws-_data-instead-of.patch
-clk-qcom-gcc-msm8996-remove-rpm-bus-clocks.patch
clk-qcom-clk-rcg2-fix-clock-rate-overflow-for-high-p.patch
clk-qcom-gcc-sm8150-use-array_size-instead-of-specif.patch
clk-qcom-gcc-sm8150-fix-gcc_sdcc2_apps_clk_src.patch
projects / thirdparty / kernel / stable-queue.git / commitdiff
