crypto: qat - add support for decompression service to GEN6 devices

Add support to configure decompression as a separate service for QAT GEN6
devices. A new arbiter configuration has been added to map the hardware
decompression threads to all ring pairs.

The decompression service is enabled via sysfs by writing "decomp" to
"/sys/bus/pci/devices/<BDF>/qat/cfg_services".

The decompression service is not supported on QAT GEN2 and GEN4 devices,
and attempting it results in an invalid write error. The existing
compression service for QAT GEN2 and GEN4 devices remains unchanged and
supports both compression and decompression operations on the same ring
pair.

Co-developed-by: Karthikeyan Gopal <karthikeyan.gopal@intel.com>
Signed-off-by: Karthikeyan Gopal <karthikeyan.gopal@intel.com>
Signed-off-by: Suman Kumar Chakraborty <suman.kumar.chakraborty@intel.com>
Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

diff --git a/drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c b/drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c
index 359a6447ccb8379c2d02296ef727ac6c3591f40d..48a29a102dd0f80e46295d55950ecba4ef20161d 100644 (file)
--- a/drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c
+++ b/drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c
@@ -76,6 +76,10 @@ static const unsigned long thrd_mask_dcc[ADF_6XXX_MAX_ACCELENGINES] = {
        0x00, 0x00, 0x00, 0x00, 0x07, 0x07, 0x03, 0x03, 0x00
 };
 
+static const unsigned long thrd_mask_dcpr[ADF_6XXX_MAX_ACCELENGINES] = {
+       0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x00
+};
+
 static const char *const adf_6xxx_fw_objs[] = {
        [ADF_FW_CY_OBJ] = ADF_6XXX_CY_OBJ,
        [ADF_FW_DC_OBJ] = ADF_6XXX_DC_OBJ,
@@ -126,6 +130,9 @@ static int get_service(unsigned long *mask)
        if (test_and_clear_bit(SVC_DCC, mask))
                return SVC_DCC;
 
+       if (test_and_clear_bit(SVC_DECOMP, mask))
+               return SVC_DECOMP;
+
        return -EINVAL;
 }
 
@@ -139,6 +146,8 @@ static enum adf_cfg_service_type get_ring_type(enum adf_services service)
        case SVC_DC:
        case SVC_DCC:
                return COMP;
+       case SVC_DECOMP:
+               return DECOMP;
        default:
                return UNUSED;
        }
@@ -155,6 +164,8 @@ static const unsigned long *get_thrd_mask(enum adf_services service)
                return thrd_mask_cpr;
        case SVC_DCC:
                return thrd_mask_dcc;
+       case SVC_DECOMP:
+               return thrd_mask_dcpr;
        default:
                return NULL;
        }
@@ -648,7 +659,7 @@ static u32 get_accel_cap(struct adf_accel_dev *accel_dev)
                caps |= capabilities_asym;
        if (test_bit(SVC_SYM, &mask))
                caps |= capabilities_sym;
-       if (test_bit(SVC_DC, &mask))
+       if (test_bit(SVC_DC, &mask) || test_bit(SVC_DECOMP, &mask))
                caps |= capabilities_dc;
        if (test_bit(SVC_DCC, &mask)) {
                /*

diff --git a/drivers/crypto/intel/qat/qat_common/adf_cfg_common.h b/drivers/crypto/intel/qat/qat_common/adf_cfg_common.h
index 15fdf9854b814a5fa9619d0c2182842d19bb2b8e..81e9e9d7eccd22374076bb961e5632b12c2053a1 100644 (file)
--- a/drivers/crypto/intel/qat/qat_common/adf_cfg_common.h
+++ b/drivers/crypto/intel/qat/qat_common/adf_cfg_common.h
@@ -29,6 +29,7 @@ enum adf_cfg_service_type {
        COMP,
        SYM,
        ASYM,
+       DECOMP,
        USED
 };
 

diff --git a/drivers/crypto/intel/qat/qat_common/adf_cfg_services.c b/drivers/crypto/intel/qat/qat_common/adf_cfg_services.c
index c39871291da72f91e34441f9134b9f8b563323d0..f49227b10064041f6028322b304c2599143fbebc 100644 (file)
--- a/drivers/crypto/intel/qat/qat_common/adf_cfg_services.c
+++ b/drivers/crypto/intel/qat/qat_common/adf_cfg_services.c
@@ -15,6 +15,7 @@ static const char *const adf_cfg_services[] = {
        [SVC_SYM] = ADF_CFG_SYM,
        [SVC_DC] = ADF_CFG_DC,
        [SVC_DCC] = ADF_CFG_DCC,
+       [SVC_DECOMP] = ADF_CFG_DECOMP,
 };
 
 /*
@@ -43,6 +44,7 @@ static_assert(BITS_PER_LONG >= SVC_BASE_COUNT);
 static_assert(sizeof(ADF_CFG_SYM ADF_SERVICES_DELIMITER
                     ADF_CFG_ASYM ADF_SERVICES_DELIMITER
                     ADF_CFG_DC ADF_SERVICES_DELIMITER
+                    ADF_CFG_DECOMP ADF_SERVICES_DELIMITER
                     ADF_CFG_DCC) < ADF_CFG_MAX_VAL_LEN_IN_BYTES);
 
 static int adf_service_string_to_mask(struct adf_accel_dev *accel_dev, const char *buf,
@@ -167,6 +169,9 @@ int adf_get_service_enabled(struct adf_accel_dev *accel_dev)
        if (test_bit(SVC_DC, &mask))
                return SVC_DC;
 
+       if (test_bit(SVC_DECOMP, &mask))
+               return SVC_DECOMP;
+
        if (test_bit(SVC_DCC, &mask))
                return SVC_DCC;
 

diff --git a/drivers/crypto/intel/qat/qat_common/adf_cfg_services.h b/drivers/crypto/intel/qat/qat_common/adf_cfg_services.h
index 3742c450878f5b55a89d48065c4ecea999cbc2e7..8709b7a52907fcf2fd778f6654df50c7b5531944 100644 (file)
--- a/drivers/crypto/intel/qat/qat_common/adf_cfg_services.h
+++ b/drivers/crypto/intel/qat/qat_common/adf_cfg_services.h
@@ -11,6 +11,7 @@ enum adf_services {
        SVC_ASYM = 0,
        SVC_SYM,
        SVC_DC,
+       SVC_DECOMP,
        SVC_DCC,
        SVC_BASE_COUNT
 };

diff --git a/drivers/crypto/intel/qat/qat_common/adf_cfg_strings.h b/drivers/crypto/intel/qat/qat_common/adf_cfg_strings.h
index b79982c4a8565ccad878115c775a2bf5d56ad0de..30107a02ee7f4d27a282de18374e7816e50e1082 100644 (file)
--- a/drivers/crypto/intel/qat/qat_common/adf_cfg_strings.h
+++ b/drivers/crypto/intel/qat/qat_common/adf_cfg_strings.h
@@ -24,6 +24,7 @@
 #define ADF_CY "Cy"
 #define ADF_DC "Dc"
 #define ADF_CFG_DC "dc"
+#define ADF_CFG_DECOMP "decomp"
 #define ADF_CFG_CY "sym;asym"
 #define ADF_CFG_SYM "sym"
 #define ADF_CFG_ASYM "asym"

diff --git a/drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c b/drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c
index 14d0fdd66a4b2f64e1e6918c17285819c4535629..258adc0b49e07e761fa81cd1d1ab4c54edbe4bd6 100644 (file)
--- a/drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c
+++ b/drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c
@@ -262,6 +262,9 @@ bool adf_gen4_services_supported(unsigned long mask)
        if (mask >= BIT(SVC_BASE_COUNT))
                return false;
 
+       if (test_bit(SVC_DECOMP, &mask))
+               return false;
+
        switch (num_svc) {
        case ADF_ONE_SERVICE:
                return true;

diff --git a/drivers/crypto/intel/qat/qat_common/adf_sysfs.c b/drivers/crypto/intel/qat/qat_common/adf_sysfs.c
index 6c39194647f032d4b9e1acbd0720c692d3ab708f..79c63dfa8ff30cbfda236fa068874a4022f76125 100644 (file)
--- a/drivers/crypto/intel/qat/qat_common/adf_sysfs.c
+++ b/drivers/crypto/intel/qat/qat_common/adf_sysfs.c
@@ -269,6 +269,8 @@ static ssize_t rp2srv_show(struct device *dev, struct device_attribute *attr,
                return sysfs_emit(buf, "%s\n", ADF_CFG_SYM);
        case ASYM:
                return sysfs_emit(buf, "%s\n", ADF_CFG_ASYM);
+       case DECOMP:
+               return sysfs_emit(buf, "%s\n", ADF_CFG_DECOMP);
        default:
                break;
        }