[AArch64][PATCH 2/2] Support ARMv8.2 DC CVAP instruction.

ARMv8.2 adds the new system instruction DC CVAP. This patch adds support
for the instruction to binutils, enabled when -march=armv8.2-a is
selected.

gas/
2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>

	* config/tc-aarch64.c (parse_sys_ins_reg): Add check of
	architectural support for system register.

gas/testsuite/
2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>

	* gas/aarch64/sysreg-2.d: Add tests for dc instruction.
	* gas/aarch64/sysreg-2.s: Add uses of dc instruction.

include/opcode/
2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64.h (aarch64_sys_ins_reg_supported_p): Declare.

opcodes/
2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64-opc.c (aarch64_sys_regs_dc): Add "cvap".
	(aarch64_sys_ins_reg_supported_p): New.

Change-Id: I3158b97d9bbee9644c2d0e2986db807412ef1053

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 7aed13e395adc5062ce00d2b3ce379f9f77d5306..f8c33e9f7e77b73d84d24212cbbe56ef2b08b453 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,8 @@
+2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * config/tc-aarch64.c (parse_sys_ins_reg): Add check of
+       architectural support for system register.
+
 2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>
 
        * doc/c-aarch64.texi (AArch64 Extensions): Update entry for crc.

diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index d30671094fb68f7c4dcbb6bc125baead6716fc37..bb2f228553a2eba24bd6fb0dba38036bc24bb719 100644 (file)
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -3687,6 +3687,10 @@ parse_sys_ins_reg (char **str, struct hash_control *sys_ins_regs)
   if (!o)
     return NULL;
 
+  if (!aarch64_sys_ins_reg_supported_p (cpu_variant, o))
+    as_bad (_("selected processor does not support system register "
+             "name '%s'"), buf);
+
   *str = q;
   return o;
 }

diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 101321098e23aecb08da3d403c9a6be24c63e70f..e7ba8ef978cc9e0a54bcf1b71baa1d9ef067fc63 100644 (file)
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * gas/aarch64/sysreg-2.d: Add tests for dc instruction.
+       * gas/aarch64/sysreg-2.s: Add uses of dc instruction.
+
 2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>
 
        * gas/aarch64/uao-directive.d: New.

diff --git a/gas/testsuite/gas/aarch64/sysreg-2.d b/gas/testsuite/gas/aarch64/sysreg-2.d
index 31b9f33eb023b690d83f185d82c14f0981ece910..dffe08f83e43526bb5fc59137cbbb878be1d6ce5 100644 (file)
--- a/gas/testsuite/gas/aarch64/sysreg-2.d
+++ b/gas/testsuite/gas/aarch64/sysreg-2.d
@@ -27,3 +27,6 @@ Disassembly of section .text:
   [0-9a-f]+:   d518c125        msr     disr_el1, x5
   [0-9a-f]+:   d538c125        mrs     x5, disr_el1
   [0-9a-f]+:   d53cc125        mrs     x5, vdisr_el2
+  [0-9a-f]+:   d50b7a20        dc      cvac, x0
+  [0-9a-f]+:   d50b7b21        dc      cvau, x1
+  [0-9a-f]+:   d50b7c22        dc      cvap, x2

diff --git a/gas/testsuite/gas/aarch64/sysreg-2.s b/gas/testsuite/gas/aarch64/sysreg-2.s
index 2a6b06c7879ecf2295eaa3d1ace013daf27ea8ad..62b3a5e8af316a8affb03eb79371ca7bad3a8e08 100644 (file)
--- a/gas/testsuite/gas/aarch64/sysreg-2.s
+++ b/gas/testsuite/gas/aarch64/sysreg-2.s
@@ -30,3 +30,9 @@
        rw_sys_reg sys_reg=vsesr_el2 xreg=x5 r=1 w=0
        rw_sys_reg sys_reg=disr_el1 xreg=x5 r=1 w=1
        rw_sys_reg sys_reg=vdisr_el2 xreg=x5 r=1 w=0
+
+       /* DC CVAP.  */
+
+       dc cvac, x0
+       dc cvau, x1
+       dc cvap, x2

diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index 101882918f8fcac83b4a373f199b64db4ba33b67..eff25ed867f4f46e2cd211dfbbbe5be8f411a50d 100644 (file)
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,7 @@
+2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * aarch64.h (aarch64_sys_ins_reg_supported_p): Declare.
+
 2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>
 
        * aarch64.h (aarch64_sys_ins_reg): Replace has_xt with flags.

diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index d0f6c3ddefe623192c1e5c3566dc8a04a38da457..7477066fec2c363d5c640f4a46e5a2ab2273836c 100644 (file)
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -676,6 +676,9 @@ typedef struct
 } aarch64_sys_ins_reg;
 
 extern bfd_boolean aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *);
+extern bfd_boolean
+aarch64_sys_ins_reg_supported_p (const aarch64_feature_set,
+                                const aarch64_sys_ins_reg *);
 
 extern const aarch64_sys_ins_reg aarch64_sys_regs_ic [];
 extern const aarch64_sys_ins_reg aarch64_sys_regs_dc [];

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index a5e113be0593285a72c99627ed23d063228e3818..79fe6649df5d15b9ad9c654f534c0b28de4742bf 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * aarch64-opc.c (aarch64_sys_regs_dc): Add "cvap".
+       (aarch64_sys_ins_reg_supported_p): New.
+
 2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>
 
        * aarch64-dis.c (aarch64_ext_regrt_sysins): Replace use of has_xt

diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index e5b45648732d92f270b29b4843842065f94c318a..08d8d5d67a1cd8e787a272838881d16562486076 100644 (file)
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -3256,6 +3256,7 @@ const aarch64_sys_ins_reg aarch64_sys_regs_dc[] =
     { "cvac",       CPENS (3, C7, C10, 1), F_HASXT },
     { "csw",       CPENS (0, C7, C10, 2), F_HASXT },
     { "cvau",       CPENS (3, C7, C11, 1), F_HASXT },
+    { "cvap",       CPENS (3, C7, C12, 1), F_HASXT | F_ARCHEXT },
     { "civac",      CPENS (3, C7, C14, 1), F_HASXT },
     { "cisw",       CPENS (0, C7, C14, 2), F_HASXT },
     { 0,       CPENS(0,0,0,0), 0 }
@@ -3321,6 +3322,21 @@ aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *sys_ins_reg)
   return (sys_ins_reg->flags & F_HASXT) != 0;
 }
 
+extern bfd_boolean
+aarch64_sys_ins_reg_supported_p (const aarch64_feature_set features,
+                                const aarch64_sys_ins_reg *reg)
+{
+  if (!(reg->flags & F_ARCHEXT))
+    return TRUE;
+
+  /* DC CVAP.  Values are from aarch64_sys_regs_dc.  */
+  if (reg->value == CPENS (3, C7, C12, 1)
+      && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
+    return FALSE;
+
+  return TRUE;
+}
+
 #undef C0
 #undef C1
 #undef C2