soc: fsl: cpm1: qmc: Rename SCC_GSMRL_MODE_QMC

Current code handles CPM1 version of QMC. Even if GSMRL is specific to
the CPM1 version, the exact same purpose and format register (GUMRL) is
present in the QUICC Engine (QE) version of QMC. Compared to the QE
version, the values defined for the mode bitfield are different and the
0x0A value defined for the QMC mode is CPM1 specific.

In order to prepare the support for the QE version, rename this bitfield
value to clearly identify it as CPM1 specific.

Signed-off-by: Herve Codina <herve.codina@bootlin.com>
Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Link: https://lore.kernel.org/r/20240808071132.149251-31-herve.codina@bootlin.com
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>

diff --git a/drivers/soc/fsl/qe/qmc.c b/drivers/soc/fsl/qe/qmc.c
index 63af2608c3cde3281242e2661560e7aa630ae15b..062477b7426ed48c8f260c031711347091bc3a3c 100644 (file)
--- a/drivers/soc/fsl/qe/qmc.c
+++ b/drivers/soc/fsl/qe/qmc.c
@@ -27,7 +27,7 @@
 #define SCC_GSMRL_ENR          BIT(5)
 #define SCC_GSMRL_ENT          BIT(4)
 #define SCC_GSMRL_MODE_MASK    GENMASK(3, 0)
-#define SCC_GSMRL_MODE_QMC     FIELD_PREP_CONST(SCC_GSMRL_MODE_MASK, 0x0A)
+#define SCC_CPM1_GSMRL_MODE_QMC        FIELD_PREP_CONST(SCC_GSMRL_MODE_MASK, 0x0A)
 
 /* SCC general mode register low (32 bits) */
 #define SCC_GSMRH      0x04
@@ -1642,7 +1642,7 @@ static int qmc_cpm1_init_scc(struct qmc *qmc)
        qmc_write32(qmc->scc_regs + SCC_GSMRH, val);
 
        /* enable QMC mode */
-       qmc_write32(qmc->scc_regs + SCC_GSMRL, SCC_GSMRL_MODE_QMC);
+       qmc_write32(qmc->scc_regs + SCC_GSMRL, SCC_CPM1_GSMRL_MODE_QMC);
 
        /* Disable and clear interrupts */
        qmc_write16(qmc->scc_regs + SCC_SCCM, 0x0000);