]> git.ipfire.org Git - thirdparty/kernel/stable-queue.git/commitdiff
5.0-stable patches
authorGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Fri, 8 Mar 2019 10:49:03 +0000 (11:49 +0100)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Fri, 8 Mar 2019 10:49:03 +0000 (11:49 +0100)
added patches:
x86-boot-compressed-64-do-not-read-legacy-rom-on-efi-system.patch
x86-cpu-amd-set-the-cpb-bit-unconditionally-on-f17h.patch

queue-5.0/series
queue-5.0/x86-boot-compressed-64-do-not-read-legacy-rom-on-efi-system.patch [new file with mode: 0644]
queue-5.0/x86-cpu-amd-set-the-cpb-bit-unconditionally-on-f17h.patch [new file with mode: 0644]

index e7d76dc54207ba81d5b53856a1be62b6e48c4770..deb8d1cd7b0dee60e4b159bd7d0e373f010a67f0 100644 (file)
@@ -26,3 +26,5 @@ sctp-call-iov_iter_revert-after-sending-abort.patch
 sky2-disable-msi-on-dell-inspiron-1545-and-gateway-p-79.patch
 team-free-bpf-filter-when-unregistering-netdev.patch
 tipc-fix-rdm-dgram-connect-regression.patch
+x86-cpu-amd-set-the-cpb-bit-unconditionally-on-f17h.patch
+x86-boot-compressed-64-do-not-read-legacy-rom-on-efi-system.patch
diff --git a/queue-5.0/x86-boot-compressed-64-do-not-read-legacy-rom-on-efi-system.patch b/queue-5.0/x86-boot-compressed-64-do-not-read-legacy-rom-on-efi-system.patch
new file mode 100644 (file)
index 0000000..cfcd355
--- /dev/null
@@ -0,0 +1,76 @@
+From 6f913de3231e1d70a871135b38219da7810df218 Mon Sep 17 00:00:00 2001
+From: "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com>
+Date: Tue, 19 Feb 2019 10:52:24 +0300
+Subject: x86/boot/compressed/64: Do not read legacy ROM on EFI system
+
+From: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>
+
+commit 6f913de3231e1d70a871135b38219da7810df218 upstream.
+
+EFI systems do not necessarily provide a legacy ROM. If the ROM is missing
+the memory is not mapped at all.
+
+Trying to dereference values in the legacy ROM area leads to a crash on
+Macbook Pro.
+
+Only look for values in the legacy ROM area for non-EFI system.
+
+Fixes: 3548e131ec6a ("x86/boot/compressed/64: Find a place for 32-bit trampoline")
+Reported-by: Pitam Mitra <pitamm@gmail.com>
+Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>
+Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
+Tested-by: Bockjoo Kim <bockjoo@phys.ufl.edu>
+Cc: bp@alien8.de
+Cc: hpa@zytor.com
+Cc: stable@vger.kernel.org
+Link: https://lkml.kernel.org/r/20190219075224.35058-1-kirill.shutemov@linux.intel.com
+Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=202351
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/x86/boot/compressed/pgtable_64.c |   19 ++++++++++++++++---
+ 1 file changed, 16 insertions(+), 3 deletions(-)
+
+--- a/arch/x86/boot/compressed/pgtable_64.c
++++ b/arch/x86/boot/compressed/pgtable_64.c
+@@ -1,5 +1,7 @@
++#include <linux/efi.h>
+ #include <asm/e820/types.h>
+ #include <asm/processor.h>
++#include <asm/efi.h>
+ #include "pgtable.h"
+ #include "../string.h"
+@@ -37,9 +39,10 @@ int cmdline_find_option_bool(const char
+ static unsigned long find_trampoline_placement(void)
+ {
+-      unsigned long bios_start, ebda_start;
++      unsigned long bios_start = 0, ebda_start = 0;
+       unsigned long trampoline_start;
+       struct boot_e820_entry *entry;
++      char *signature;
+       int i;
+       /*
+@@ -47,8 +50,18 @@ static unsigned long find_trampoline_pla
+        * This code is based on reserve_bios_regions().
+        */
+-      ebda_start = *(unsigned short *)0x40e << 4;
+-      bios_start = *(unsigned short *)0x413 << 10;
++      /*
++       * EFI systems may not provide legacy ROM. The memory may not be mapped
++       * at all.
++       *
++       * Only look for values in the legacy ROM for non-EFI system.
++       */
++      signature = (char *)&boot_params->efi_info.efi_loader_signature;
++      if (strncmp(signature, EFI32_LOADER_SIGNATURE, 4) &&
++          strncmp(signature, EFI64_LOADER_SIGNATURE, 4)) {
++              ebda_start = *(unsigned short *)0x40e << 4;
++              bios_start = *(unsigned short *)0x413 << 10;
++      }
+       if (bios_start < BIOS_START_MIN || bios_start > BIOS_START_MAX)
+               bios_start = BIOS_START_MAX;
diff --git a/queue-5.0/x86-cpu-amd-set-the-cpb-bit-unconditionally-on-f17h.patch b/queue-5.0/x86-cpu-amd-set-the-cpb-bit-unconditionally-on-f17h.patch
new file mode 100644 (file)
index 0000000..25d0709
--- /dev/null
@@ -0,0 +1,47 @@
+From 0237199186e7a4aa5310741f0a6498a20c820fd7 Mon Sep 17 00:00:00 2001
+From: Jiaxun Yang <jiaxun.yang@flygoat.com>
+Date: Tue, 20 Nov 2018 11:00:18 +0800
+Subject: x86/CPU/AMD: Set the CPB bit unconditionally on F17h
+
+From: Jiaxun Yang <jiaxun.yang@flygoat.com>
+
+commit 0237199186e7a4aa5310741f0a6498a20c820fd7 upstream.
+
+Some F17h models do not have CPB set in CPUID even though the CPU
+supports it. Set the feature bit unconditionally on all F17h.
+
+ [ bp: Rewrite commit message and patch. ]
+
+Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
+Signed-off-by: Borislav Petkov <bp@suse.de>
+Acked-by: Tom Lendacky <thomas.lendacky@amd.com>
+Cc: "H. Peter Anvin" <hpa@zytor.com>
+Cc: Ingo Molnar <mingo@redhat.com>
+Cc: Sherry Hurwitz <sherry.hurwitz@amd.com>
+Cc: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
+Cc: Thomas Gleixner <tglx@linutronix.de>
+Cc: x86-ml <x86@kernel.org>
+Link: https://lkml.kernel.org/r/20181120030018.5185-1-jiaxun.yang@flygoat.com
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/x86/kernel/cpu/amd.c |    8 +++-----
+ 1 file changed, 3 insertions(+), 5 deletions(-)
+
+--- a/arch/x86/kernel/cpu/amd.c
++++ b/arch/x86/kernel/cpu/amd.c
+@@ -819,11 +819,9 @@ static void init_amd_bd(struct cpuinfo_x
+ static void init_amd_zn(struct cpuinfo_x86 *c)
+ {
+       set_cpu_cap(c, X86_FEATURE_ZEN);
+-      /*
+-       * Fix erratum 1076: CPB feature bit not being set in CPUID. It affects
+-       * all up to and including B1.
+-       */
+-      if (c->x86_model <= 1 && c->x86_stepping <= 1)
++
++      /* Fix erratum 1076: CPB feature bit not being set in CPUID. */
++      if (!cpu_has(c, X86_FEATURE_CPB))
+               set_cpu_cap(c, X86_FEATURE_CPB);
+ }