[(set (match_operand:DI 0 "register_operand" "")
(and:DI (match_operand:DI 1 "register_operand" "")
(match_operand:DI 2 "and_operand" "")))]
- ""
- "
-{
- /* Both operands must be register operands. */
- if (!TARGET_64BIT && !register_operand (operands[2], DImode))
- FAIL;
-}")
-
-(define_insn ""
- [(set (match_operand:DI 0 "register_operand" "=r")
- (and:DI (match_operand:DI 1 "register_operand" "%r")
- (match_operand:DI 2 "register_operand" "r")))]
- "!TARGET_64BIT"
- "and %1,%2,%0\;and %R1,%R2,%R0"
- [(set_attr "type" "binary")
- (set_attr "length" "8")])
+ "TARGET_64BIT"
+ "")
(define_insn ""
[(set (match_operand:DI 0 "register_operand" "=r,r")
[(set_attr "type" "binary,shift")
(set_attr "length" "4,4")])
-(define_insn ""
- [(set (match_operand:DI 0 "register_operand" "=r")
- (and:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
- (match_operand:DI 2 "register_operand" "r")))]
- "!TARGET_64BIT"
- "andcm %2,%1,%0\;andcm %R2,%R1,%R0"
- [(set_attr "type" "binary")
- (set_attr "length" "8")])
-
(define_insn ""
[(set (match_operand:DI 0 "register_operand" "=r")
(and:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
[(set (match_operand:DI 0 "register_operand" "")
(ior:DI (match_operand:DI 1 "register_operand" "")
(match_operand:DI 2 "reg_or_cint_ior_operand" "")))]
- ""
- "
-{
- /* Both operands must be register operands. */
- if (!TARGET_64BIT && !register_operand (operands[2], DImode))
- FAIL;
-}")
-
-(define_insn ""
- [(set (match_operand:DI 0 "register_operand" "=r")
- (ior:DI (match_operand:DI 1 "register_operand" "%r")
- (match_operand:DI 2 "register_operand" "r")))]
- "!TARGET_64BIT"
- "or %1,%2,%0\;or %R1,%R2,%R0"
- [(set_attr "type" "binary")
- (set_attr "length" "8")])
+ "TARGET_64BIT"
+ "")
(define_insn ""
[(set (match_operand:DI 0 "register_operand" "=r,r")
[(set (match_operand:DI 0 "register_operand" "")
(xor:DI (match_operand:DI 1 "register_operand" "")
(match_operand:DI 2 "register_operand" "")))]
- ""
- "
-{
-}")
-
-(define_insn ""
- [(set (match_operand:DI 0 "register_operand" "=r")
- (xor:DI (match_operand:DI 1 "register_operand" "%r")
- (match_operand:DI 2 "register_operand" "r")))]
- "!TARGET_64BIT"
- "xor %1,%2,%0\;xor %R1,%R2,%R0"
- [(set_attr "type" "binary")
- (set_attr "length" "8")])
+ "TARGET_64BIT"
+ "")
(define_insn ""
[(set (match_operand:DI 0 "register_operand" "=r")