+2018-11-07 Chenghua Xu <paul.hua.gm@gmail.com>
+
+ * config/mips/gs264e.md: New.
+ * config/mips/mips-cpus.def: Define gs264e.
+ * config/mips/mips-tables.opt: Regenerate.
+ * config/mips/mips.c (mips_rtx_cost_data): Add DEFAULT_COSTS for
+ gs264e.
+ (mips_issue_rate): Add support for gs264e.
+ (mips_multipass_dfa_lookahead): Likewise.
+ * config/mips/mips.h: Define TARGET_GS264E and TUNE_GS264E.
+ (MIPS_ISA_LEVEL_SPEC): Infer mips64r2 from gs264e.
+ (MIPS_ASE_MSA_SPEC): New.
+ (BASE_DRIVER_SELF_SPECS): march=gs264e implies -mmsa.
+ (ISA_HAS_FUSED_MADD4): Enable for TARGET_GS264E.
+ (ISA_HAS_UNFUSED_MADD4): Exclude TARGET_GS264E.
+ * config/mips/mips.md: Include gs264e.md.
+ (processor): Add gs264e.
+ * config/mips/mips.opt (MSA): Use Mask instead of Var.
+ * doc/invoke.texi: Add gs264e to supported architectures.
+
2018-11-07 Chenghua Xu <paul.hua.gm@gmail.com>
* config/mips/gs464e.md: New.
--- /dev/null
+;; Pipeline model for Loongson gs264e cores.
+
+;; Copyright (C) 2018 Free Software Foundation, Inc.
+;;
+;; This file is part of GCC.
+;;
+;; GCC is free software; you can redistribute it and/or modify it
+;; under the terms of the GNU General Public License as published
+;; by the Free Software Foundation; either version 3, or (at your
+;; option) any later version.
+;;
+;; GCC is distributed in the hope that it will be useful, but WITHOUT
+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+;; License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3. If not see
+;; <http://www.gnu.org/licenses/>.
+
+;; Uncomment the following line to output automata for debugging.
+;; (automata_option "v")
+
+;; Automaton for integer instructions.
+(define_automaton "gs264e_a_alu")
+
+;; Automaton for floating-point instructions.
+(define_automaton "gs264e_a_falu")
+
+;; Automaton for memory operations.
+(define_automaton "gs264e_a_mem")
+
+;; Describe the resources.
+
+(define_cpu_unit "gs264e_alu1" "gs264e_a_alu")
+(define_cpu_unit "gs264e_mem1" "gs264e_a_mem")
+(define_cpu_unit "gs264e_falu1" "gs264e_a_falu")
+
+;; Describe instruction reservations.
+
+(define_insn_reservation "gs264e_arith" 1
+ (and (eq_attr "cpu" "gs264e")
+ (eq_attr "type" "arith,clz,const,logical,
+ move,nop,shift,signext,slt"))
+ "gs264e_alu1")
+
+(define_insn_reservation "gs264e_branch" 1
+ (and (eq_attr "cpu" "gs264e")
+ (eq_attr "type" "branch,jump,call,condmove,trap"))
+ "gs264e_alu1")
+
+(define_insn_reservation "gs264e_mfhilo" 1
+ (and (eq_attr "cpu" "gs264e")
+ (eq_attr "type" "mfhi,mflo,mthi,mtlo"))
+ "gs264e_alu1")
+
+;; Operation imul3nc is fully pipelined.
+(define_insn_reservation "gs264e_imul3nc" 7
+ (and (eq_attr "cpu" "gs264e")
+ (eq_attr "type" "imul3nc"))
+ "gs264e_alu1")
+
+(define_insn_reservation "gs264e_imul" 7
+ (and (eq_attr "cpu" "gs264e")
+ (eq_attr "type" "imul,imadd"))
+ "gs264e_alu1")
+
+(define_insn_reservation "gs264e_idiv_si" 12
+ (and (eq_attr "cpu" "gs264e")
+ (and (eq_attr "type" "idiv")
+ (eq_attr "mode" "SI")))
+ "gs264e_alu1")
+
+(define_insn_reservation "gs264e_idiv_di" 25
+ (and (eq_attr "cpu" "gs264e")
+ (and (eq_attr "type" "idiv")
+ (eq_attr "mode" "DI")))
+ "gs264e_alu1")
+
+(define_insn_reservation "gs264e_load" 4
+ (and (eq_attr "cpu" "gs264e")
+ (eq_attr "type" "load"))
+ "gs264e_mem1")
+
+(define_insn_reservation "gs264e_fpload" 4
+ (and (eq_attr "cpu" "gs264e")
+ (eq_attr "type" "load,mfc,mtc"))
+ "gs264e_mem1")
+
+(define_insn_reservation "gs264e_prefetch" 0
+ (and (eq_attr "cpu" "gs264e")
+ (eq_attr "type" "prefetch,prefetchx"))
+ "gs264e_mem1")
+
+(define_insn_reservation "gs264e_store" 0
+ (and (eq_attr "cpu" "gs264e")
+ (eq_attr "type" "store,fpstore,fpidxstore"))
+ "gs264e_mem1")
+
+(define_insn_reservation "gs264e_fadd" 4
+ (and (eq_attr "cpu" "gs264e")
+ (eq_attr "type" "fadd,fmul,fmadd"))
+ "gs264e_falu1")
+
+(define_insn_reservation "gs264e_fcmp" 2
+ (and (eq_attr "cpu" "gs264e")
+ (eq_attr "type" "fabs,fcmp,fmove,fneg"))
+ "gs264e_falu1")
+
+(define_insn_reservation "gs264e_fcvt" 4
+ (and (eq_attr "cpu" "gs264e")
+ (eq_attr "type" "fcvt"))
+ "gs264e_falu1")
+
+(define_insn_reservation "gs264e_fdiv_sf" 12
+ (and (eq_attr "cpu" "gs264e")
+ (and (eq_attr "type" "fdiv,frdiv,fsqrt,frsqrt")
+ (eq_attr "mode" "SF")))
+ "gs264e_falu1")
+
+(define_insn_reservation "gs264e_fdiv_df" 19
+ (and (eq_attr "cpu" "gs264e")
+ (and (eq_attr "type" "fdiv,frdiv,fsqrt,frsqrt")
+ (eq_attr "mode" "DF")))
+ "gs264e_falu1")
+
+;; Force single-dispatch for unknown or multi.
+(define_insn_reservation "gs264e_unknown" 1
+ (and (eq_attr "cpu" "gs264e")
+ (eq_attr "type" "unknown,multi,atomic,syncloop"))
+ "gs264e_alu1 + gs264e_falu1 + gs264e_mem1")
+
+;; End of DFA-based pipeline description for gs264e
MIPS_CPU ("loongson3a", PROCESSOR_GS464, 65, PTF_AVOID_BRANCHLIKELY_SPEED)
MIPS_CPU ("gs464", PROCESSOR_GS464, 65, PTF_AVOID_BRANCHLIKELY_SPEED)
MIPS_CPU ("gs464e", PROCESSOR_GS464E, 65, PTF_AVOID_BRANCHLIKELY_SPEED)
+MIPS_CPU ("gs264e", PROCESSOR_GS264E, 65, PTF_AVOID_BRANCHLIKELY_SPEED)
MIPS_CPU ("octeon", PROCESSOR_OCTEON, 65, PTF_AVOID_BRANCHLIKELY_SPEED)
MIPS_CPU ("octeon+", PROCESSOR_OCTEON, 65, PTF_AVOID_BRANCHLIKELY_SPEED)
MIPS_CPU ("octeon2", PROCESSOR_OCTEON2, 65, PTF_AVOID_BRANCHLIKELY_SPEED)
Enum(mips_arch_opt_value) String(gs464e) Value(98) Canonical
EnumValue
-Enum(mips_arch_opt_value) String(octeon) Value(99) Canonical
+Enum(mips_arch_opt_value) String(gs264e) Value(99) Canonical
EnumValue
-Enum(mips_arch_opt_value) String(octeon+) Value(100) Canonical
+Enum(mips_arch_opt_value) String(octeon) Value(100) Canonical
EnumValue
-Enum(mips_arch_opt_value) String(octeon2) Value(101) Canonical
+Enum(mips_arch_opt_value) String(octeon+) Value(101) Canonical
EnumValue
-Enum(mips_arch_opt_value) String(octeon3) Value(102) Canonical
+Enum(mips_arch_opt_value) String(octeon2) Value(102) Canonical
EnumValue
-Enum(mips_arch_opt_value) String(xlp) Value(103) Canonical
+Enum(mips_arch_opt_value) String(octeon3) Value(103) Canonical
EnumValue
-Enum(mips_arch_opt_value) String(i6400) Value(104) Canonical
+Enum(mips_arch_opt_value) String(xlp) Value(104) Canonical
EnumValue
-Enum(mips_arch_opt_value) String(i6500) Value(105) Canonical
+Enum(mips_arch_opt_value) String(i6400) Value(105) Canonical
EnumValue
-Enum(mips_arch_opt_value) String(p6600) Value(106) Canonical
+Enum(mips_arch_opt_value) String(i6500) Value(106) Canonical
+
+EnumValue
+Enum(mips_arch_opt_value) String(p6600) Value(107) Canonical
{ /* Loongson gs464e. */
DEFAULT_COSTS
},
+ { /* Loongson gs264e. */
+ DEFAULT_COSTS
+ },
{ /* M4k */
DEFAULT_COSTS
},
case PROCESSOR_OCTEON2:
case PROCESSOR_OCTEON3:
case PROCESSOR_I6400:
+ case PROCESSOR_GS264E:
return 2;
case PROCESSOR_SB1:
if (TUNE_LOONGSON_2EF || TUNE_GS464 || TUNE_GS464E)
return 4;
- if (TUNE_OCTEON)
+ if (TUNE_OCTEON || TUNE_GS264E)
return 2;
if (TUNE_P5600 || TUNE_P6600 || TUNE_I6400)
#define TARGET_LOONGSON_2EF (TARGET_LOONGSON_2E || TARGET_LOONGSON_2F)
#define TARGET_GS464 (mips_arch == PROCESSOR_GS464)
#define TARGET_GS464E (mips_arch == PROCESSOR_GS464E)
+#define TARGET_GS264E (mips_arch == PROCESSOR_GS264E)
#define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
#define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
#define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
|| mips_tune == PROCESSOR_LOONGSON_2F)
#define TUNE_GS464 (mips_tune == PROCESSOR_GS464)
#define TUNE_GS464E (mips_tune == PROCESSOR_GS464E)
+#define TUNE_GS264E (mips_tune == PROCESSOR_GS264E)
#define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
#define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
#define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
%{march=mips32r6: -mips32r6} \
%{march=mips64|march=5k*|march=20k*|march=sb1*|march=sr71000 \
|march=xlr: -mips64} \
- %{march=mips64r2|march=loongson3a|march=gs464|march=gs464e|march=octeon \
- |march=xlp: -mips64r2} \
+ %{march=mips64r2|march=loongson3a|march=gs464|march=gs464e|march=gs264e \
+ |march=octeon|march=xlp: -mips64r2} \
%{march=mips64r3: -mips64r3} \
%{march=mips64r5: -mips64r5} \
%{march=mips64r6|march=i6400|march=i6500|march=p6600: -mips64r6}}"
MIPS_ISA_NAN2008_SPEC, \
MIPS_ASE_DSP_SPEC, \
MIPS_ASE_LOONGSON_MMI_SPEC, \
- MIPS_ASE_LOONGSON_EXT_SPEC
+ MIPS_ASE_LOONGSON_EXT_SPEC, \
+ MIPS_ASE_MSA_SPEC
+
#define MIPS_ASE_DSP_SPEC \
"%{!mno-dsp: \
#define MIPS_ASE_LOONGSON_EXT_SPEC \
"%{!mno-loongson-ext: \
%{march=loongson3a|march=gs464: -mloongson-ext} \
- {march=gs464e: %{!mno-loongson-ext2: -mloongson-ext2 -mloongson-ext}}}"
+ %{march=gs464e|march=gs264e: %{!mno-loongson-ext2: \
+ -mloongson-ext2 -mloongson-ext}}}"
+
+#define MIPS_ASE_MSA_SPEC \
+ "%{!mno-msa: \
+ %{march=gs264e: -mmsa}}"
#define DRIVER_SELF_SPECS \
MIPS_ISA_LEVEL_SPEC, \
#define ISA_HAS_FUSED_MADD4 (mips_madd4 \
&& (TARGET_MIPS8000 \
|| TARGET_GS464 \
- || TARGET_GS464E))
+ || TARGET_GS464E \
+ || TARGET_GS264E))
/* ISA has 4 operand unfused madd instructions of the form
'd = [+-] (a * b [+-] c)'. */
&& ISA_HAS_FP4 \
&& !TARGET_MIPS8000 \
&& !TARGET_GS464 \
- && !TARGET_GS464E)
+ && !TARGET_GS464E \
+ && !TARGET_GS264E)
/* ISA has 3 operand r6 fused madd instructions of the form
'c = c [+-] (a * b)'. */
loongson_2f
gs464
gs464e
+ gs264e
m4k
octeon
octeon2
(include "loongson2ef.md")
(include "gs464.md")
(include "gs464e.md")
+(include "gs264e.md")
(include "octeon.md")
(include "sb1.md")
(include "sr71k.md")
Use microMIPS instructions.
mmsa
-Target Report Var(TARGET_MSA)
+Target Report Mask(MSA)
Use MIPS MSA Extension instructions.
mmt
@samp{i6400}, @samp{i6500},
@samp{interaptiv},
@samp{loongson2e}, @samp{loongson2f}, @samp{loongson3a}, @samp{gs464},
-@samp{gs464e},
+@samp{gs464e}, @samp{gs264e},
@samp{m4k},
@samp{m14k}, @samp{m14kc}, @samp{m14ke}, @samp{m14kec},
@samp{m5100}, @samp{m5101},
projects / thirdparty / gcc.git / commitdiff
