]> git.ipfire.org Git - thirdparty/qemu.git/commitdiff
hw/pci-host: Constify all Property
authorRichard Henderson <richard.henderson@linaro.org>
Fri, 13 Dec 2024 16:35:23 +0000 (16:35 +0000)
committerRichard Henderson <richard.henderson@linaro.org>
Sun, 15 Dec 2024 18:55:54 +0000 (12:55 -0600)
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
17 files changed:
hw/pci-host/dino.c
hw/pci-host/gpex.c
hw/pci-host/grackle.c
hw/pci-host/gt64120.c
hw/pci-host/i440fx.c
hw/pci-host/mv64361.c
hw/pci-host/pnv_phb.c
hw/pci-host/pnv_phb3.c
hw/pci-host/pnv_phb4.c
hw/pci-host/pnv_phb4_pec.c
hw/pci-host/ppce500.c
hw/pci-host/q35.c
hw/pci-host/raven.c
hw/pci-host/sabre.c
hw/pci-host/uninorth.c
hw/pci-host/versatile.c
hw/pci-host/xilinx-pcie.c

index 283fc0dc57507e13b98eb186492b2cf8682069fb..ead9893f2130f9a92d2d27a082ed0a2e12461563 100644 (file)
@@ -492,7 +492,7 @@ static void dino_pcihost_init(Object *obj)
     qdev_init_gpio_in(DEVICE(obj), dino_set_irq, DINO_IRQS);
 }
 
-static Property dino_pcihost_properties[] = {
+static const Property dino_pcihost_properties[] = {
     DEFINE_PROP_LINK("memory-as", DinoState, memory_as, TYPE_MEMORY_REGION,
                      MemoryRegion *),
     DEFINE_PROP_END_OF_LIST(),
index e9cf455bf5231c2984aac18e01434bd4ee40055c..8a955ca13052a205e54ebb6432eabfcbf5a0d961 100644 (file)
@@ -147,7 +147,7 @@ static const char *gpex_host_root_bus_path(PCIHostState *host_bridge,
     return "0000:00";
 }
 
-static Property gpex_host_properties[] = {
+static const Property gpex_host_properties[] = {
     /*
      * Permit CPU accesses to unmapped areas of the PIO and MMIO windows
      * (discarding writes and returning -1 for reads) rather than aborting.
index 8e589ff2c9ea4b94130073d70c1e0aa5a73236f6..d64de7377440a3ade2cc9d52cac6861265ab5aed 100644 (file)
@@ -129,7 +129,7 @@ static char *grackle_ofw_unit_address(const SysBusDevice *dev)
     return g_strdup_printf("%x", s->ofw_addr);
 }
 
-static Property grackle_properties[] = {
+static const Property grackle_properties[] = {
     DEFINE_PROP_UINT32("ofw-addr", GrackleState, ofw_addr, -1),
     DEFINE_PROP_END_OF_LIST()
 };
index 14fc803d27948d12394edfd2f9d19b72a9fdfd0a..3c73ebe83ff95967ee54140652f9a7635e96c876 100644 (file)
@@ -1274,7 +1274,7 @@ static const TypeInfo gt64120_pci_info = {
     },
 };
 
-static Property gt64120_properties[] = {
+static const Property gt64120_properties[] = {
     DEFINE_PROP_BOOL("cpu-little-endian", GT64120State,
                      cpu_little_endian, false),
     DEFINE_PROP_END_OF_LIST(),
index 4f0a0438d773d31b13fd5d99e4819dfd1108c8a0..40780fbc525223e532cb6e725554b0456ee1a62e 100644 (file)
@@ -353,7 +353,7 @@ static const char *i440fx_pcihost_root_bus_path(PCIHostState *host_bridge,
     return "0000:00";
 }
 
-static Property i440fx_props[] = {
+static const Property i440fx_props[] = {
     DEFINE_PROP_SIZE(PCI_HOST_PROP_PCI_HOLE64_SIZE, I440FXState,
                      pci_hole64_size, I440FX_PCI_HOST_HOLE64_SIZE_DEFAULT),
     DEFINE_PROP_SIZE(PCI_HOST_BELOW_4G_MEM_SIZE, I440FXState,
index 421c287eb09a234d0e0a195b24e81e6327f2fcf6..2518d5abe6b8fe9d0f9870d16b3ad270dd47e3a2 100644 (file)
@@ -98,7 +98,7 @@ static void mv64361_pcihost_realize(DeviceState *dev, Error **errp)
     qdev_init_gpio_out(dev, s->irq, ARRAY_SIZE(s->irq));
 }
 
-static Property mv64361_pcihost_props[] = {
+static const Property mv64361_pcihost_props[] = {
     DEFINE_PROP_UINT8("index", MV64361PCIState, index, 0),
     DEFINE_PROP_END_OF_LIST()
 };
index d4c118d443620819315a9c1443d41fe3bbf20d22..888f0786a07e79792e0dda04fdcec22a52c8ce68 100644 (file)
@@ -183,7 +183,7 @@ static const char *pnv_phb_root_bus_path(PCIHostState *host_bridge,
     return phb->bus_path;
 }
 
-static Property pnv_phb_properties[] = {
+static const Property pnv_phb_properties[] = {
     DEFINE_PROP_UINT32("index", PnvPHB, phb_id, 0),
     DEFINE_PROP_UINT32("chip-id", PnvPHB, chip_id, 0),
     DEFINE_PROP_UINT32("version", PnvPHB, version, 0),
@@ -302,7 +302,7 @@ static void pnv_phb_root_port_realize(DeviceState *dev, Error **errp)
     pci_config_set_interrupt_pin(pci->config, 0);
 }
 
-static Property pnv_phb_root_port_properties[] = {
+static const Property pnv_phb_root_port_properties[] = {
     DEFINE_PROP_UINT32("version", PnvPHBRootPort, version, 0),
 
     DEFINE_PROP_END_OF_LIST(),
index 2a74dbe45f59b207b57b3b8af8856ac5cf04d114..529b33b5a2ace1a5f446d35fda19a0988dc4a6cb 100644 (file)
@@ -1090,7 +1090,7 @@ void pnv_phb3_update_regions(PnvPHB3 *phb)
     pnv_phb3_check_all_m64s(phb);
 }
 
-static Property pnv_phb3_properties[] = {
+static const Property pnv_phb3_properties[] = {
     DEFINE_PROP_UINT32("index", PnvPHB3, phb_id, 0),
     DEFINE_PROP_UINT32("chip-id", PnvPHB3, chip_id, 0),
     DEFINE_PROP_LINK("chip", PnvPHB3, chip, TYPE_PNV_CHIP, PnvChip *),
index 99991008c1322c0391f725cd3f08d0fe7f0ccc51..482fe25803c06f654c51cefbcb71bd74437ce8fd 100644 (file)
@@ -1688,7 +1688,7 @@ static void pnv_phb4_xive_notify(XiveNotifier *xf, uint32_t srcno,
     }
 }
 
-static Property pnv_phb4_properties[] = {
+static const Property pnv_phb4_properties[] = {
     DEFINE_PROP_UINT32("index", PnvPHB4, phb_id, 0),
     DEFINE_PROP_UINT32("chip-id", PnvPHB4, chip_id, 0),
     DEFINE_PROP_LINK("pec", PnvPHB4, pec, TYPE_PNV_PHB4_PEC,
index ce8e228f987bac92b5005a5707288e3f4c4c6bd4..f8975403d3325b8b81d539940f8dfa6d680698cf 100644 (file)
@@ -283,7 +283,7 @@ static int pnv_pec_dt_xscom(PnvXScomInterface *dev, void *fdt,
     return 0;
 }
 
-static Property pnv_pec_properties[] = {
+static const Property pnv_pec_properties[] = {
     DEFINE_PROP_UINT32("index", PnvPhb4PecState, index, 0),
     DEFINE_PROP_UINT32("chip-id", PnvPhb4PecState, chip_id, 0),
     DEFINE_PROP_LINK("chip", PnvPhb4PecState, chip, TYPE_PNV_CHIP,
index b70631045a091506ff91d1c401a1221cdc7f8ca7..54071fc125a62a4c98f7a619588d811460486d8e 100644 (file)
@@ -507,7 +507,7 @@ static void e500_host_bridge_class_init(ObjectClass *klass, void *data)
     dc->user_creatable = false;
 }
 
-static Property pcihost_properties[] = {
+static const Property pcihost_properties[] = {
     DEFINE_PROP_UINT32("first_slot", PPCE500PCIState, first_slot, 0x11),
     DEFINE_PROP_UINT32("first_pin_irq", PPCE500PCIState, first_pin_irq, 0x1),
     DEFINE_PROP_END_OF_LIST(),
index f3e713318edffde746003085badfb3a63743ba85..af0b77ea1e6ad58c7e7282ed5b56e4ee98766db1 100644 (file)
@@ -170,7 +170,7 @@ static void q35_host_get_pci_hole64_end(Object *obj, Visitor *v,
  * properties need to be initialized manually by
  * q35_host_initfn() after the object_initialize() call.
  */
-static Property q35_host_props[] = {
+static const Property q35_host_props[] = {
     DEFINE_PROP_UINT64(PCIE_HOST_MCFG_BASE, Q35PCIHost, parent_obj.base_addr,
                         MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT),
     DEFINE_PROP_SIZE(PCI_HOST_PROP_PCI_HOLE64_SIZE, Q35PCIHost,
@@ -662,7 +662,7 @@ static void mch_realize(PCIDevice *d, Error **errp)
                                    OBJECT(&mch->smram));
 }
 
-static Property mch_props[] = {
+static const Property mch_props[] = {
     DEFINE_PROP_UINT16("extended-tseg-mbytes", MCHPCIState, ext_tseg_mbytes,
                        16),
     DEFINE_PROP_BOOL("smbase-smram", MCHPCIState, has_smram_at_smbase, true),
index a7dfddd69ea9dc8568fbac2a0c47a93e8dca18b3..b0a4a669f5929ee5520c28687108267cfb6b8d3a 100644 (file)
@@ -422,7 +422,7 @@ static const TypeInfo raven_info = {
     },
 };
 
-static Property raven_pcihost_properties[] = {
+static const Property raven_pcihost_properties[] = {
     DEFINE_PROP_UINT32("elf-machine", PREPPCIState, pci_dev.elf_machine,
                        EM_NONE),
     DEFINE_PROP_STRING("bios-name", PREPPCIState, pci_dev.bios_name),
index 1707feb9513f7bf32d895efc3086a69af4cb5380..623afed6447dc6eba2f8af4510ca4d8142fef8c8 100644 (file)
@@ -492,7 +492,7 @@ static char *sabre_ofw_unit_address(const SysBusDevice *dev)
                (uint32_t)(s->special_base & 0xffffffff));
 }
 
-static Property sabre_properties[] = {
+static const Property sabre_properties[] = {
     DEFINE_PROP_UINT64("special-base", SabreState, special_base, 0),
     DEFINE_PROP_UINT64("mem-base", SabreState, mem_base, 0),
     DEFINE_PROP_END_OF_LIST(),
index e4c1abd8715293a7bed25287227cdd45df80ef14..bd670cfa9db6673756f44371de430b8f4b29b032 100644 (file)
@@ -423,7 +423,7 @@ static const TypeInfo unin_internal_pci_host_info = {
     },
 };
 
-static Property pci_unin_main_pci_host_props[] = {
+static const Property pci_unin_main_pci_host_props[] = {
     DEFINE_PROP_UINT32("ofw-addr", UNINHostState, ofw_addr, -1),
     DEFINE_PROP_END_OF_LIST()
 };
index d257acee17234d4c07fa261461e7d2b638937c54..5d596406916fec92e00bc9869d963875c32e8740 100644 (file)
@@ -498,7 +498,7 @@ static const TypeInfo versatile_pci_host_info = {
     },
 };
 
-static Property pci_vpb_properties[] = {
+static const Property pci_vpb_properties[] = {
     DEFINE_PROP_UINT8("broken-irq-mapping", PCIVPBState, irq_mapping_prop,
                       PCI_VPB_IRQMAP_ASSUME_OK),
     DEFINE_PROP_END_OF_LIST()
index 24f691ea82902ae5810a7cc0b89bd02015e6eaa7..848403970bcc73589b4cb430b091b33c3b79efe7 100644 (file)
@@ -156,7 +156,7 @@ static void xilinx_pcie_host_init(Object *obj)
     qdev_prop_set_bit(DEVICE(root), "multifunction", false);
 }
 
-static Property xilinx_pcie_host_props[] = {
+static const Property xilinx_pcie_host_props[] = {
     DEFINE_PROP_UINT32("bus_nr", XilinxPCIEHost, bus_nr, 0),
     DEFINE_PROP_SIZE("cfg_base", XilinxPCIEHost, cfg_base, 0),
     DEFINE_PROP_SIZE("cfg_size", XilinxPCIEHost, cfg_size, 32 * MiB),