* config/mips/mips.md (*branch_bit<bbv><mode>,

	*branch_bit<bbv><mode>_inverted): Renumber operands so that the
	label becomes operands[1].

From-SVN: r142694

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 64a7b927315e91e52833ffac0f2c9242623bef64..c792f1e2598d376f550a4a58fd7ccb8deaa7d2c8 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2008-12-11  Adam Nemet  <anemet@caviumnetworks.com>
+
+       * config/mips/mips.md (*branch_bit<bbv><mode>,
+       *branch_bit<bbv><mode>_inverted): Renumber operands so that the
+       label becomes operands[1].
+
 2008-12-11  Harsha Jagasia  <harsha.jagasia@amd.com>
 
        PR tree-optimization/38446

diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
index b9226c5c61d29cf63e2557187b2dddbff82240d8..1b26f0298539af529446e279519a281348c2d6b4 100644 (file)
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -5203,18 +5203,18 @@
   [(set (pc)
        (if_then_else
         (equality_op (zero_extract:GPR
-                      (match_operand:GPR 1 "register_operand" "d")
+                      (match_operand:GPR 0 "register_operand" "d")
                       (const_int 1)
                       (match_operand 2 "const_int_operand" ""))
                      (const_int 0))
-        (label_ref (match_operand 0 ""))
+        (label_ref (match_operand 1 ""))
         (pc)))]
   "ISA_HAS_BBIT && UINTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode)"
 {
   return
     mips_output_conditional_branch (insn, operands,
-                                   MIPS_BRANCH ("bbit<bbv>", "%1,%2,%0"),
-                                   MIPS_BRANCH ("bbit<bbinv>", "%1,%2,%0"));
+                                   MIPS_BRANCH ("bbit<bbv>", "%0,%2,%1"),
+                                   MIPS_BRANCH ("bbit<bbinv>", "%0,%2,%1"));
 }
   [(set_attr "type"         "branch")
    (set_attr "mode"         "none")
@@ -5224,18 +5224,18 @@
   [(set (pc)
        (if_then_else
         (equality_op (zero_extract:GPR
-                      (match_operand:GPR 1 "register_operand" "d")
+                      (match_operand:GPR 0 "register_operand" "d")
                       (const_int 1)
                       (match_operand 2 "const_int_operand" ""))
                      (const_int 0))
         (pc)
-        (label_ref (match_operand 0 ""))))]
+        (label_ref (match_operand 1 ""))))]
   "ISA_HAS_BBIT && UINTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode)"
 {
   return
     mips_output_conditional_branch (insn, operands,
-                                   MIPS_BRANCH ("bbit<bbinv>", "%1,%2,%0"),
-                                   MIPS_BRANCH ("bbit<bbv>", "%1,%2,%0"));
+                                   MIPS_BRANCH ("bbit<bbinv>", "%0,%2,%1"),
+                                   MIPS_BRANCH ("bbit<bbv>", "%0,%2,%1"));
 }
   [(set_attr "type"         "branch")
    (set_attr "mode"         "none")