RISC-V: Support Zcmp push/pop instructions.

Support zcmp extension push/pop/popret and popret zero instructions.
The `reg_list' is a list containing 1 to 13 registers, we can use:
"{ra}, {ra, s0}, {ra, s0-s1}, {ra, s0-s2} ... {ra, s0-sN}"
to present this feature.

Passed gcc/binutils regressions of riscv-gnu-toolchain.

Most of work was finished by Sinan Lin.
Co-Authored by: Charlie Keaney <charlie.keaney@embecosm.com>
Co-Authored by: Mary Bennett <mary.bennett@embecosm.com>
Co-Authored by: Nandni Jamnadas <nandni.jamnadas@embecosm.com>
Co-Authored by: Sinan Lin <sinan.lin@linux.alibaba.com>
Co-Authored by: Simon Cook <simon.cook@embecosm.com>
Co-Authored by: Shihua Liao <shihua@iscas.ac.cn>
Co-Authored by: Yulong Shi <yulong@iscas.ac.cn>

bfd/ChangeLog:

        * elfxx-riscv.c (riscv_implicit_subset): Imply zca for zcmp.
	(riscv_supported_std_z_ext): Added zcmp with version 1.0.
	(riscv_parse_check_conflicts): Zcmp conflicts with d/zcd.
        (riscv_multi_subset_supports): Handle zcmp.
        (riscv_multi_subset_supports_ext): Ditto.

gas/ChangeLog:

	* NEWS: Updated.
        * config/tc-riscv.c (regno_to_reg_list): New function, used to map
	register to reg_list number.
        (reglist_lookup): Called reglist_lookup_internal.  Return false if
	reg_list number is zero, which is an invalid value.
	(reglist_lookup_internal): Parse register list, and return the last
	register by regno_to_reg_list.
        (validate_riscv_insn):  New operators.
        (riscv_ip): Ditto.
	* testsuite/gas/riscv/march-help.l: Updated.
        * testsuite/gas/riscv/zcmp-push-pop-fail.d: New test.
        * testsuite/gas/riscv/zcmp-push-pop-fail.l: New test.
        * testsuite/gas/riscv/zcmp-push-pop-fail.s: New test.
        * testsuite/gas/riscv/zcmp-push-pop.d: New test.
        * testsuite/gas/riscv/zcmp-push-pop.s: New test.

include/ChangeLog:

        * opcode/riscv-opc.h (MATCH/MASK_CM_PUSH): New macros for zcmp.
        (MATCH/MASK_CM_POP): Ditto.
        (MATCH/MASK_CM_POPRET): Ditto.
        (MATCH/MASK_CM_POPRETZ): Ditto.
        (DECLARE_INSN): New declarations for zcmp.
        * opcode/riscv.h (EXTRACT/ENCODE/VALID_ZCMP_SPIMM): Handle spimm
	operand for zcmp.
        (OP_MASK_REG_LIST): Handle operand for zcmp register list.
        (OP_SH_REG_LIST): Ditto.
        (ZCMP_SP_ALIGNMENT): New argument, used in riscv_get_sp_base.
        (X_S0, X_S1, X_S2, X_S10, X_S11): New register numbers.
        (enum riscv_insn_class): Added INSN_CLASS_ZCMP.
        (extern riscv_get_sp_base): Added.

opcodes/ChangeLog:

        * riscv-dis.c (print_reg_list): New function, used to get zcmp
	reg_list field.
        (riscv_get_spimm): New function, used to get zcmp sp adjustment
	immediate.
        (print_insn_args): Handle new operands for zcmp.
        * riscv-opc.c (riscv_get_sp_base): New function, used by gas and
	objdump.  Get sp base adjustment.
	(riscv_opcodes): Added zcmp instructions.

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 28be6651945354f1bc95ecb58ef7c5da4ee057ab..b08e44577b85327d83e979ea8b68ab19e74944c1 100644 (file)
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1267,6 +1267,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
   {"zcf", "zca",       check_implicit_always},
   {"zcd", "zca",       check_implicit_always},
   {"zcb", "zca",       check_implicit_always},
+  {"zcmp", "zca",      check_implicit_always},
   {"smaia", "ssaia",           check_implicit_always},
   {"smcntrpmf", "zicsr",       check_implicit_always},
   {"smstateen", "ssstateen",   check_implicit_always},
@@ -1415,6 +1416,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
   {"zcb",              ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
   {"zcf",              ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
   {"zcd",              ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
+  {"zcmp",             ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
   {NULL, 0, 0, 0, 0}
 };
 
@@ -2056,6 +2058,13 @@ riscv_parse_check_conflicts (riscv_parse_subset_t *rps)
       rps->error_handler (_("rv%d does not support the `q' extension"), xlen);
       no_conflict = false;
     }
+  if (riscv_subset_supports (rps, "zcmp")
+      && riscv_subset_supports (rps, "zcd"))
+    {
+      rps->error_handler
+       (_("zcmp' is incompatible with `d/zcd' extension"));
+      no_conflict = false;
+    }
   if (riscv_lookup_subset (rps->subset_list, "zcf", &subset)
       && xlen > 32)
     {
@@ -2645,6 +2654,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
     case INSN_CLASS_ZCB_AND_ZMMUL:
       return (riscv_subset_supports (rps, "zcb")
              && riscv_subset_supports (rps, "zmmul"));
+    case INSN_CLASS_ZCMP:
+      return riscv_subset_supports (rps, "zcmp");
     case INSN_CLASS_SVINVAL:
       return riscv_subset_supports (rps, "svinval");
     case INSN_CLASS_H:
@@ -2899,6 +2910,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
       return _("zcb' and `zbb");
     case INSN_CLASS_ZCB_AND_ZMMUL:
       return _("zcb' and `zmmul', or `zcb' and `m");
+    case INSN_CLASS_ZCMP:
+      return "zcmp";
     case INSN_CLASS_SVINVAL:
       return "svinval";
     case INSN_CLASS_H:

diff --git a/gas/NEWS b/gas/NEWS
index 4a7f6dcbb0ba6bd8571208516d9c3130f39b5bcd..cb58ca8fb8d40b7b34a23452ec0b37bdb6049570 100644 (file)
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -11,6 +11,8 @@
 * Remove support for RISC-V privileged spec 1.9.1, but linker can still
   recognize it in case of linking old objects.
 
+* Add support for RISC-V Zcmp extension with version 1.0.
+
 * The base register operand in D(X,B) and D(L,B) may be explicitly omitted
   in assembly on s390. It can now be coded as D(X,) or D(L,) instead of D(X,0)
   D(X,%r0), D(L,0), and D(L,%r0).

diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 94f0c679bb93653a9afbf584db55faeeaafaaabc..1757ff6e9e2846fd3e5d01d1e6b8a989bcb118dd 100644 (file)
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -1254,6 +1254,158 @@ flt_lookup (float f, const float *array, size_t size, unsigned *regnop)
   return false;
 }
 
+/* Map ra and s-register to [4,15], so that we can check if the
+   reg2 in register list reg1-reg2 or single reg2 is valid or not,
+   and obtain the corresponding reg_list value.
+
+   ra - 4
+   s0 - 5
+   s1 - 6
+    ....
+   s10 - 0 (invalid)
+   s11 - 15.  */
+
+static int
+regno_to_reg_list (unsigned regno)
+{
+  if (regno == X_RA)
+    return 4;
+  else if (regno == X_S0 || regno == X_S1)
+    return 5 + regno - X_S0;
+  else if (regno >= X_S2 && regno < X_S10)
+    return 7 + regno - X_S2;
+  else if (regno == X_S11)
+    return 15;
+
+  /* Invalid symbol.  */
+  return 0;
+}
+
+/* Parse register list, and return the last register by regno_to_reg_list.
+
+   If ABI register names are used (e.g. ra and s0), the register
+   list could be "{ra}", "{ra, s0}", "{ra, s0-sN}", where 0 < N < 10 or
+   N == 11.
+
+   If numeric register names are used (e.g. x1 and x8), the register list
+   could be "{x1}", "{x1,x8}", "{x1,x8-x9}", "{x1,x8-x9,x18}" and
+   "{x1,x8-x9,x18-xN}", where 19 < N < 25 or N == 27.
+
+   The numeric and ABI register names cannot be used at the same time.
+
+   TODO: Report errors for the following cases,
+   1. Too many registers in the list.
+   2. Cases which return 0.
+   3. Illegal formats, for example, {x1,x8-NULL,x18-x24/x18}, {x1-x2,x8}.  */
+
+static unsigned
+reglist_lookup_internal (char *reglist)
+{
+  unsigned regno = 0;
+  unsigned reg_list = 0;
+  char *regname[3][2] = {{NULL}};
+  char *save_tok, *save_subtok;
+  unsigned i, j;
+
+  char *token = strtok_r (reglist, ",", &save_tok);
+  for (i = 0; i < 3 && token != NULL;
+       token = strtok_r (NULL, ",", &save_tok), i++)
+    {
+      char *subtoken = strtok_r (token, "-", &save_subtok);
+      for (j = 0; j < 2 && subtoken != NULL;
+          subtoken = strtok_r (NULL, "-", &save_subtok), j++)
+       regname[i][j] = subtoken;
+    }
+
+  bool reg1_numeric = false;
+  for (i = 0; i < 3; i++)
+    {
+      if (regname[i][0] == NULL)
+       continue;
+#define REG_TO_REG_LIST(NAME, NUM, LIST) \
+  (reg_lookup (&NAME, RCLASS_GPR, &NUM) && (LIST = regno_to_reg_list (NUM)))
+#define REG_NUMERIC(NAME) (NAME[0] == 'x')
+#define REG_CONFLICT(NAME, REG_NUMERIC) \
+  ((NAME[0] == 'x' && !REG_NUMERIC) || (NAME[0] != 'x' && REG_NUMERIC))
+      switch (i)
+       {
+       case 0:
+         reg1_numeric = REG_NUMERIC (regname[i][0]);
+         if (!REG_TO_REG_LIST (regname[i][0], regno, reg_list)
+             || regno != X_RA)
+           return 0;
+         break;
+       case 1:
+         if (REG_CONFLICT (regname[i][0], reg1_numeric)
+             /* The second register should be s0 or its numeric names x8.  */
+             || !REG_TO_REG_LIST (regname[i][0], regno, reg_list)
+             || regno != X_S0)
+           return 0;
+         else if (regname[i][1] == NULL)
+           return reg_list;
+
+         if (REG_CONFLICT (regname[i][1], reg1_numeric)
+             /* The third register is x9 if the numeric name is used.
+                Otherwise, it could be any other sN register, where N > 0.  */
+             || !REG_TO_REG_LIST (regname[i][1], regno, reg_list)
+             || regno <= X_S0
+             || (reg1_numeric && regno != X_S1))
+           return 0;
+         break;
+       case 2:
+         /* Must use register numeric names.  */
+         if (!reg1_numeric
+             || !REG_NUMERIC (regname[i][0])
+             /* The fourth register should be s2.  */
+             || !REG_TO_REG_LIST (regname[i][0], regno, reg_list)
+             || regno != X_S2)
+           return 0;
+         else if (regname[i][1] == NULL)
+           return reg_list;
+
+         if (!reg1_numeric
+             || !REG_NUMERIC (regname[i][1])
+             /* The fifth register could be any other sN register, where N > 1.  */
+             || !REG_TO_REG_LIST (regname[i][1], regno, reg_list)
+             || regno <= X_S2)
+           return 0;
+         break;
+       default:
+         return 0;
+       }
+#undef REG_TO_REG_LIST
+#undef REG_NUMERIC
+#undef REG_CONFLICT
+    }
+  return reg_list;
+}
+
+/* Parse register list.  Return false if REG_LIST is zero, which is an
+   invalid value.  */
+
+static bool
+reglist_lookup (char **s, unsigned *reg_list)
+{
+  *reg_list = 0;
+  char *reglist = strdup (*s);
+  if (reglist != NULL)
+    {
+      char *token = strtok (reglist, "}");
+      if (token != NULL)
+       {
+         *s += strlen (token);
+         *reg_list = reglist_lookup_internal (reglist);
+       }
+      else
+       {
+         as_bad (_("cannot find `}' for cm.push/cm.pop"));
+         *reg_list = 0;
+       }
+    }
+  free (reglist);
+  return *reg_list == 0 ? false : true;
+}
+
 #define USE_BITS(mask,shift) (used_bits |= ((insn_t)(mask) << (shift)))
 #define USE_IMM(n, s) \
   (used_bits |= ((insn_t)((1ull<<n)-1) << (s)))
@@ -1370,6 +1522,8 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
        case ',': break;
        case '(': break;
        case ')': break;
+       case '{': break;
+       case '}': break;
        case '<': USE_BITS (OP_MASK_SHAMTW, OP_SH_SHAMTW); break;
        case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
        case 'A': break; /* Macro operand, must be symbol.  */
@@ -1450,6 +1604,10 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
                case 'h': used_bits |= ENCODE_ZCB_HALFWORD_UIMM (-1U); break;
                /* halfword immediate operators, load/store halfword insns.  */
                case 'b': used_bits |= ENCODE_ZCB_BYTE_UIMM (-1U); break;
+               /* Immediate offset operand for cm.push and cm.pop.  */
+               case 'p': used_bits |= ENCODE_ZCMP_SPIMM (-1U); break;
+               /* Register list operand for cm.push and cm.pop.  */
+               case 'r': USE_BITS (OP_MASK_REG_LIST, OP_SH_REG_LIST); break;
                case 'f': break;
                default:
                  goto unknown_validate_operand;
@@ -3206,6 +3364,8 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
            case ')':
            case '[':
            case ']':
+           case '{':
+           case '}':
              if (*asarg++ == *oparg)
                continue;
              break;
@@ -3661,6 +3821,27 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
                        break;
                      ip->insn_opcode |= ENCODE_ZCB_BYTE_UIMM (imm_expr->X_add_number);
                      goto rvc_imm_done;
+                   case 'r':
+                     if (!reglist_lookup (&asarg, &regno))
+                       break;
+                     INSERT_OPERAND (REG_LIST, *ip, regno);
+                     continue;
+                   case 'p':
+                     if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p)
+                       || imm_expr->X_op != O_constant)
+                       break;
+                     /* Convert stack adjustment of cm.push to a positive
+                        offset.  */
+                     if (ip->insn_mo->match == MATCH_CM_PUSH)
+                       imm_expr->X_add_number *= -1;
+                     /* Subtract base stack adjustment and get spimm.  */
+                     imm_expr->X_add_number -=
+                       riscv_get_sp_base (ip->insn_opcode, *riscv_rps_as.xlen);
+                     if (!VALID_ZCMP_SPIMM (imm_expr->X_add_number))
+                       break;
+                     ip->insn_opcode |=
+                       ENCODE_ZCMP_SPIMM (imm_expr->X_add_number);
+                     goto rvc_imm_done;
                    case 'f': /* Operand for matching immediate 255.  */
                      if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p)
                          || imm_expr->X_op != O_constant

diff --git a/gas/testsuite/gas/riscv/march-help.l b/gas/testsuite/gas/riscv/march-help.l
index 7f92194d10d20bf49f478b1860c2cd10175a1c32..e45221e5ed88ceeed6b374cfca9eac9e7beb3226 100644 (file)
--- a/gas/testsuite/gas/riscv/march-help.l
+++ b/gas/testsuite/gas/riscv/march-help.l
@@ -87,6 +87,7 @@ All available -march extensions for RISC-V:
        zcb                                     1.0
        zcf                                     1.0
        zcd                                     1.0
+       zcmp                                    1.0
        smaia                                   1.0
        smcntrpmf                               1.0
        smepmp                                  1.0

diff --git a/gas/testsuite/gas/riscv/zcmp-push-pop-fail.d b/gas/testsuite/gas/riscv/zcmp-push-pop-fail.d
new file mode 100644 (file)
index 0000000..84ecf26
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zcmp-push-pop-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv64i_zcmp
+#source: zcmp-push-pop-fail.s
+#error_output: zcmp-push-pop-fail.l

diff --git a/gas/testsuite/gas/riscv/zcmp-push-pop-fail.l b/gas/testsuite/gas/riscv/zcmp-push-pop-fail.l
new file mode 100644 (file)
index 0000000..955e495
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zcmp-push-pop-fail.l
@@ -0,0 +1,9 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cm.push \{a0\},-64'
+.*: Error: illegal operands `cm.pop \{ra,s1\},-64'
+.*: Error: illegal operands `cm.popret \{ra,s2-s3\},-64'
+.*: Error: illegal operands `cm.popretz \{ra,s0-s10\},-112'
+.*: Error: illegal operands `cm.push \{ra\},0'
+.*: Error: illegal operands `cm.pop \{ra,s0\},-80'
+.*: Error: illegal operands `cm.popret \{ra,s0-s1\},-15'
+.*: Error: illegal operands `cm.popretz \{ra,s0-s11\},-165'

diff --git a/gas/testsuite/gas/riscv/zcmp-push-pop-fail.s b/gas/testsuite/gas/riscv/zcmp-push-pop-fail.s
new file mode 100644 (file)
index 0000000..0e8df58
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zcmp-push-pop-fail.s
@@ -0,0 +1,13 @@
+target:
+
+       # reg_list
+       cm.push {a0}, -64
+       cm.pop {ra, s1}, -64
+       cm.popret {ra, s2-s3}, -64
+       cm.popretz {ra, s0-s10}, -112
+
+       # spimm
+       cm.push {ra}, 0
+       cm.pop {ra, s0}, -80
+       cm.popret {ra, s0-s1}, -15
+       cm.popretz {ra, s0-s11}, -165

diff --git a/gas/testsuite/gas/riscv/zcmp-push-pop.d b/gas/testsuite/gas/riscv/zcmp-push-pop.d
new file mode 100644 (file)
index 0000000..e212950
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zcmp-push-pop.d
@@ -0,0 +1,154 @@
+#as: -march=rv64i_zcmp
+#source: zcmp-push-pop.s
+#objdump: -dr -Mno-aliases
+
+.*:[    ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[       ]*[0-9a-f]+:[   ]+b84e[         ]+cm.push[      ]+\{ra\},-64
+[       ]*[0-9a-f]+:[   ]+b85e[         ]+cm.push[      ]+\{ra,s0\},-64
+[       ]*[0-9a-f]+:[   ]+b86a[         ]+cm.push[      ]+\{ra,s0-s1\},-64
+[       ]*[0-9a-f]+:[   ]+b87a[         ]+cm.push[      ]+\{ra,s0-s2\},-64
+[       ]*[0-9a-f]+:[   ]+b8da[         ]+cm.push[      ]+\{ra,s0-s8\},-112
+[       ]*[0-9a-f]+:[   ]+b8e6[         ]+cm.push[      ]+\{ra,s0-s9\},-112
+[       ]*[0-9a-f]+:[   ]+b8f2[         ]+cm.push[      ]+\{ra,s0-s11\},-112
+[       ]*[0-9a-f]+:[   ]+b84e[         ]+cm.push[      ]+\{ra\},-64
+[       ]*[0-9a-f]+:[   ]+b85e[         ]+cm.push[      ]+\{ra,s0\},-64
+[       ]*[0-9a-f]+:[   ]+b86a[         ]+cm.push[      ]+\{ra,s0-s1\},-64
+[       ]*[0-9a-f]+:[   ]+b87a[         ]+cm.push[      ]+\{ra,s0-s2\},-64
+[       ]*[0-9a-f]+:[   ]+b8da[         ]+cm.push[      ]+\{ra,s0-s8\},-112
+[       ]*[0-9a-f]+:[   ]+b8e6[         ]+cm.push[      ]+\{ra,s0-s9\},-112
+[       ]*[0-9a-f]+:[   ]+b8f2[         ]+cm.push[      ]+\{ra,s0-s11},-112
+[       ]*[0-9a-f]+:[   ]+b842[         ]+cm.push[      ]+\{ra\},-16
+[       ]*[0-9a-f]+:[   ]+b846[         ]+cm.push[      ]+\{ra\},-32
+[       ]*[0-9a-f]+:[   ]+b84e[         ]+cm.push[      ]+\{ra\},-64
+[       ]*[0-9a-f]+:[   ]+b872[         ]+cm.push[      ]+\{ra,s0-s2\},-32
+[       ]*[0-9a-f]+:[   ]+b87a[         ]+cm.push[      ]+\{ra,s0-s2\},-64
+[       ]*[0-9a-f]+:[   ]+b87e[         ]+cm.push[      ]+\{ra,s0-s2\},-80
+[       ]*[0-9a-f]+:[   ]+b882[         ]+cm.push[      ]+\{ra,s0-s3\},-48
+[       ]*[0-9a-f]+:[   ]+b886[         ]+cm.push[      ]+\{ra,s0-s3\},-64
+[       ]*[0-9a-f]+:[   ]+b88e[         ]+cm.push[      ]+\{ra,s0-s3\},-96
+[       ]*[0-9a-f]+:[   ]+b8b2[         ]+cm.push[      ]+\{ra,s0-s6\},-64
+[       ]*[0-9a-f]+:[   ]+b8b6[         ]+cm.push[      ]+\{ra,s0-s6\},-80
+[       ]*[0-9a-f]+:[   ]+b8be[         ]+cm.push[      ]+\{ra,s0-s6\},-112
+[       ]*[0-9a-f]+:[   ]+b8c2[         ]+cm.push[      ]+\{ra,s0-s7\},-80
+[       ]*[0-9a-f]+:[   ]+b8c6[         ]+cm.push[      ]+\{ra,s0-s7\},-96
+[       ]*[0-9a-f]+:[   ]+b8ce[         ]+cm.push[      ]+\{ra,s0-s7\},-128
+[       ]*[0-9a-f]+:[   ]+b8e2[         ]+cm.push[      ]+\{ra,s0-s9\},-96
+[       ]*[0-9a-f]+:[   ]+b8e6[         ]+cm.push[      ]+\{ra,s0-s9\},-112
+[       ]*[0-9a-f]+:[   ]+b8ee[         ]+cm.push[      ]+\{ra,s0-s9\},-144
+[       ]*[0-9a-f]+:[   ]+b8f2[         ]+cm.push[      ]+\{ra,s0-s11\},-112
+[       ]*[0-9a-f]+:[   ]+b8f6[         ]+cm.push[      ]+\{ra,s0-s11\},-128
+[       ]*[0-9a-f]+:[   ]+b8fa[         ]+cm.push[      ]+\{ra,s0-s11\},-144
+[       ]*[0-9a-f]+:[   ]+b8fe[         ]+cm.push[      ]+\{ra,s0-s11\},-160
+[       ]*[0-9a-f]+:[   ]+ba4e[         ]+cm.pop[       ]+\{ra\},64
+[       ]*[0-9a-f]+:[   ]+ba5e[         ]+cm.pop[       ]+\{ra,s0\},64
+[       ]*[0-9a-f]+:[   ]+ba6a[         ]+cm.pop[       ]+\{ra,s0-s1\},64
+[       ]*[0-9a-f]+:[   ]+ba7a[         ]+cm.pop[       ]+\{ra,s0-s2\},64
+[       ]*[0-9a-f]+:[   ]+bada[         ]+cm.pop[       ]+\{ra,s0-s8\},112
+[       ]*[0-9a-f]+:[   ]+bae6[         ]+cm.pop[       ]+\{ra,s0-s9\},112
+[       ]*[0-9a-f]+:[   ]+baf2[         ]+cm.pop[       ]+\{ra,s0-s11\},112
+[       ]*[0-9a-f]+:[   ]+ba4e[         ]+cm.pop[       ]+\{ra\},64
+[       ]*[0-9a-f]+:[   ]+ba5e[         ]+cm.pop[       ]+\{ra,s0\},64
+[       ]*[0-9a-f]+:[   ]+ba6a[         ]+cm.pop[       ]+\{ra,s0-s1\},64
+[       ]*[0-9a-f]+:[   ]+ba7a[         ]+cm.pop[       ]+\{ra,s0-s2\},64
+[       ]*[0-9a-f]+:[   ]+bada[         ]+cm.pop[       ]+\{ra,s0-s8\},112
+[       ]*[0-9a-f]+:[   ]+bae6[         ]+cm.pop[       ]+\{ra,s0-s9\},112
+[       ]*[0-9a-f]+:[   ]+baf2[         ]+cm.pop[       ]+\{ra,s0-s11},112
+[       ]*[0-9a-f]+:[   ]+ba42[         ]+cm.pop[       ]+\{ra\},16
+[       ]*[0-9a-f]+:[   ]+ba46[         ]+cm.pop[       ]+\{ra\},32
+[       ]*[0-9a-f]+:[   ]+ba4e[         ]+cm.pop[       ]+\{ra\},64
+[       ]*[0-9a-f]+:[   ]+ba72[         ]+cm.pop[       ]+\{ra,s0-s2\},32
+[       ]*[0-9a-f]+:[   ]+ba7a[         ]+cm.pop[       ]+\{ra,s0-s2\},64
+[       ]*[0-9a-f]+:[   ]+ba7e[         ]+cm.pop[       ]+\{ra,s0-s2\},80
+[       ]*[0-9a-f]+:[   ]+ba82[         ]+cm.pop[       ]+\{ra,s0-s3\},48
+[       ]*[0-9a-f]+:[   ]+ba86[         ]+cm.pop[       ]+\{ra,s0-s3\},64
+[       ]*[0-9a-f]+:[   ]+ba8e[         ]+cm.pop[       ]+\{ra,s0-s3\},96
+[       ]*[0-9a-f]+:[   ]+bab2[         ]+cm.pop[       ]+\{ra,s0-s6\},64
+[       ]*[0-9a-f]+:[   ]+bab6[         ]+cm.pop[       ]+\{ra,s0-s6\},80
+[       ]*[0-9a-f]+:[   ]+babe[         ]+cm.pop[       ]+\{ra,s0-s6\},112
+[       ]*[0-9a-f]+:[   ]+bac2[         ]+cm.pop[       ]+\{ra,s0-s7\},80
+[       ]*[0-9a-f]+:[   ]+bac6[         ]+cm.pop[       ]+\{ra,s0-s7\},96
+[       ]*[0-9a-f]+:[   ]+bace[         ]+cm.pop[       ]+\{ra,s0-s7\},128
+[       ]*[0-9a-f]+:[   ]+bae2[         ]+cm.pop[       ]+\{ra,s0-s9\},96
+[       ]*[0-9a-f]+:[   ]+bae6[         ]+cm.pop[       ]+\{ra,s0-s9\},112
+[       ]*[0-9a-f]+:[   ]+baee[         ]+cm.pop[       ]+\{ra,s0-s9\},144
+[       ]*[0-9a-f]+:[   ]+baf2[         ]+cm.pop[       ]+\{ra,s0-s11\},112
+[       ]*[0-9a-f]+:[   ]+baf6[         ]+cm.pop[       ]+\{ra,s0-s11\},128
+[       ]*[0-9a-f]+:[   ]+bafa[         ]+cm.pop[       ]+\{ra,s0-s11\},144
+[       ]*[0-9a-f]+:[   ]+bafe[         ]+cm.pop[       ]+\{ra,s0-s11\},160
+[       ]*[0-9a-f]+:[   ]+be4e[         ]+cm.popret[    ]+\{ra\},64
+[       ]*[0-9a-f]+:[   ]+be5e[         ]+cm.popret[    ]+\{ra,s0\},64
+[       ]*[0-9a-f]+:[   ]+be6a[         ]+cm.popret[    ]+\{ra,s0-s1\},64
+[       ]*[0-9a-f]+:[   ]+be7a[         ]+cm.popret[    ]+\{ra,s0-s2\},64
+[       ]*[0-9a-f]+:[   ]+beda[         ]+cm.popret[    ]+\{ra,s0-s8\},112
+[       ]*[0-9a-f]+:[   ]+bee6[         ]+cm.popret[    ]+\{ra,s0-s9\},112
+[       ]*[0-9a-f]+:[   ]+bef2[         ]+cm.popret[    ]+\{ra,s0-s11\},112
+[       ]*[0-9a-f]+:[   ]+be4e[         ]+cm.popret[    ]+\{ra\},64
+[       ]*[0-9a-f]+:[   ]+be5e[         ]+cm.popret[    ]+\{ra,s0\},64
+[       ]*[0-9a-f]+:[   ]+be6a[         ]+cm.popret[    ]+\{ra,s0-s1\},64
+[       ]*[0-9a-f]+:[   ]+be7a[         ]+cm.popret[    ]+\{ra,s0-s2\},64
+[       ]*[0-9a-f]+:[   ]+beda[         ]+cm.popret[    ]+\{ra,s0-s8\},112
+[       ]*[0-9a-f]+:[   ]+bee6[         ]+cm.popret[    ]+\{ra,s0-s9\},112
+[       ]*[0-9a-f]+:[   ]+bef2[         ]+cm.popret[    ]+\{ra,s0-s11},112
+[       ]*[0-9a-f]+:[   ]+be42[         ]+cm.popret[    ]+\{ra\},16
+[       ]*[0-9a-f]+:[   ]+be46[         ]+cm.popret[    ]+\{ra\},32
+[       ]*[0-9a-f]+:[   ]+be4e[         ]+cm.popret[    ]+\{ra\},64
+[       ]*[0-9a-f]+:[   ]+be72[         ]+cm.popret[    ]+\{ra,s0-s2\},32
+[       ]*[0-9a-f]+:[   ]+be7a[         ]+cm.popret[    ]+\{ra,s0-s2\},64
+[       ]*[0-9a-f]+:[   ]+be7e[         ]+cm.popret[    ]+\{ra,s0-s2\},80
+[       ]*[0-9a-f]+:[   ]+be82[         ]+cm.popret[    ]+\{ra,s0-s3\},48
+[       ]*[0-9a-f]+:[   ]+be86[         ]+cm.popret[    ]+\{ra,s0-s3\},64
+[       ]*[0-9a-f]+:[   ]+be8e[         ]+cm.popret[    ]+\{ra,s0-s3\},96
+[       ]*[0-9a-f]+:[   ]+beb2[         ]+cm.popret[    ]+\{ra,s0-s6\},64
+[       ]*[0-9a-f]+:[   ]+beb6[         ]+cm.popret[    ]+\{ra,s0-s6\},80
+[       ]*[0-9a-f]+:[   ]+bebe[         ]+cm.popret[    ]+\{ra,s0-s6\},112
+[       ]*[0-9a-f]+:[   ]+bec2[         ]+cm.popret[    ]+\{ra,s0-s7\},80
+[       ]*[0-9a-f]+:[   ]+bec6[         ]+cm.popret[    ]+\{ra,s0-s7\},96
+[       ]*[0-9a-f]+:[   ]+bece[         ]+cm.popret[    ]+\{ra,s0-s7\},128
+[       ]*[0-9a-f]+:[   ]+bee2[         ]+cm.popret[    ]+\{ra,s0-s9\},96
+[       ]*[0-9a-f]+:[   ]+bee6[         ]+cm.popret[    ]+\{ra,s0-s9\},112
+[       ]*[0-9a-f]+:[   ]+beee[         ]+cm.popret[    ]+\{ra,s0-s9\},144
+[       ]*[0-9a-f]+:[   ]+bef2[         ]+cm.popret[    ]+\{ra,s0-s11\},112
+[       ]*[0-9a-f]+:[   ]+bef6[         ]+cm.popret[    ]+\{ra,s0-s11\},128
+[       ]*[0-9a-f]+:[   ]+befa[         ]+cm.popret[    ]+\{ra,s0-s11\},144
+[       ]*[0-9a-f]+:[   ]+befe[         ]+cm.popret[    ]+\{ra,s0-s11\},160
+[       ]*[0-9a-f]+:[   ]+bc4e[         ]+cm.popretz[   ]+\{ra\},64
+[       ]*[0-9a-f]+:[   ]+bc5e[         ]+cm.popretz[   ]+\{ra,s0\},64
+[       ]*[0-9a-f]+:[   ]+bc6a[         ]+cm.popretz[   ]+\{ra,s0-s1\},64
+[       ]*[0-9a-f]+:[   ]+bc7a[         ]+cm.popretz[   ]+\{ra,s0-s2\},64
+[       ]*[0-9a-f]+:[   ]+bcda[         ]+cm.popretz[   ]+\{ra,s0-s8\},112
+[       ]*[0-9a-f]+:[   ]+bce6[         ]+cm.popretz[   ]+\{ra,s0-s9\},112
+[       ]*[0-9a-f]+:[   ]+bcf2[         ]+cm.popretz[   ]+\{ra,s0-s11\},112
+[       ]*[0-9a-f]+:[   ]+bc4e[         ]+cm.popretz[   ]+\{ra\},64
+[       ]*[0-9a-f]+:[   ]+bc5e[         ]+cm.popretz[   ]+\{ra,s0\},64
+[       ]*[0-9a-f]+:[   ]+bc6a[         ]+cm.popretz[   ]+\{ra,s0-s1\},64
+[       ]*[0-9a-f]+:[   ]+bc7a[         ]+cm.popretz[   ]+\{ra,s0-s2\},64
+[       ]*[0-9a-f]+:[   ]+bcda[         ]+cm.popretz[   ]+\{ra,s0-s8\},112
+[       ]*[0-9a-f]+:[   ]+bce6[         ]+cm.popretz[   ]+\{ra,s0-s9\},112
+[       ]*[0-9a-f]+:[   ]+bcf2[         ]+cm.popretz[   ]+\{ra,s0-s11},112
+[       ]*[0-9a-f]+:[   ]+bc42[         ]+cm.popretz[   ]+\{ra\},16
+[       ]*[0-9a-f]+:[   ]+bc46[         ]+cm.popretz[   ]+\{ra\},32
+[       ]*[0-9a-f]+:[   ]+bc4e[         ]+cm.popretz[   ]+\{ra\},64
+[       ]*[0-9a-f]+:[   ]+bc72[         ]+cm.popretz[   ]+\{ra,s0-s2\},32
+[       ]*[0-9a-f]+:[   ]+bc7a[         ]+cm.popretz[   ]+\{ra,s0-s2\},64
+[       ]*[0-9a-f]+:[   ]+bc7e[         ]+cm.popretz[   ]+\{ra,s0-s2\},80
+[       ]*[0-9a-f]+:[   ]+bc82[         ]+cm.popretz[   ]+\{ra,s0-s3\},48
+[       ]*[0-9a-f]+:[   ]+bc86[         ]+cm.popretz[   ]+\{ra,s0-s3\},64
+[       ]*[0-9a-f]+:[   ]+bc8e[         ]+cm.popretz[   ]+\{ra,s0-s3\},96
+[       ]*[0-9a-f]+:[   ]+bcb2[         ]+cm.popretz[   ]+\{ra,s0-s6\},64
+[       ]*[0-9a-f]+:[   ]+bcb6[         ]+cm.popretz[   ]+\{ra,s0-s6\},80
+[       ]*[0-9a-f]+:[   ]+bcbe[         ]+cm.popretz[   ]+\{ra,s0-s6\},112
+[       ]*[0-9a-f]+:[   ]+bcc2[         ]+cm.popretz[   ]+\{ra,s0-s7\},80
+[       ]*[0-9a-f]+:[   ]+bcc6[         ]+cm.popretz[   ]+\{ra,s0-s7\},96
+[       ]*[0-9a-f]+:[   ]+bcce[         ]+cm.popretz[   ]+\{ra,s0-s7\},128
+[       ]*[0-9a-f]+:[   ]+bce2[         ]+cm.popretz[   ]+\{ra,s0-s9\},96
+[       ]*[0-9a-f]+:[   ]+bce6[         ]+cm.popretz[   ]+\{ra,s0-s9\},112
+[       ]*[0-9a-f]+:[   ]+bcee[         ]+cm.popretz[   ]+\{ra,s0-s9\},144
+[       ]*[0-9a-f]+:[   ]+bcf2[         ]+cm.popretz[   ]+\{ra,s0-s11\},112
+[       ]*[0-9a-f]+:[   ]+bcf6[         ]+cm.popretz[   ]+\{ra,s0-s11\},128
+[       ]*[0-9a-f]+:[   ]+bcfa[         ]+cm.popretz[   ]+\{ra,s0-s11\},144
+[       ]*[0-9a-f]+:[   ]+bcfe[         ]+cm.popretz[   ]+\{ra,s0-s11\},160

diff --git a/gas/testsuite/gas/riscv/zcmp-push-pop.s b/gas/testsuite/gas/riscv/zcmp-push-pop.s
new file mode 100644 (file)
index 0000000..dc441bc
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zcmp-push-pop.s
@@ -0,0 +1,162 @@
+target:
+
+       # push
+       # abi names
+       cm.push {ra}, -64
+       cm.push {ra, s0}, -64
+       cm.push {ra, s0-s1}, -64
+       cm.push {ra, s0-s2}, -64
+       cm.push {ra, s0-s8}, -112
+       cm.push {ra, s0-s9}, -112
+       cm.push {ra, s0-s11}, -112
+       # numeric names
+       cm.push {x1}, -64
+       cm.push {x1, x8}, -64
+       cm.push {x1, x8-x9}, -64
+       cm.push {x1, x8-x9, x18}, -64
+       cm.push {x1, x8-x9, x18-x24}, -112
+       cm.push {x1, x8-x9, x18-x25}, -112
+       cm.push {x1, x8-x9, x18-x27}, -112
+       # spimm
+       cm.push {ra}, -16
+       cm.push {ra}, -32
+       cm.push {ra}, -64
+       cm.push {ra, s0-s2}, -32
+       cm.push {ra, s0-s2}, -64
+       cm.push {ra, s0-s2}, -80
+       cm.push {ra, s0-s3}, -48
+       cm.push {ra, s0-s3}, -64
+       cm.push {ra, s0-s3}, -96
+       cm.push {ra, s0-s6}, -64
+       cm.push {ra, s0-s6}, -80
+       cm.push {ra, s0-s6}, -112
+       cm.push {ra, s0-s7}, -80
+       cm.push {ra, s0-s7}, -96
+       cm.push {ra, s0-s7}, -128
+       cm.push {ra, s0-s9}, -96
+       cm.push {ra, s0-s9}, -112
+       cm.push {ra, s0-s9}, -144
+       cm.push {ra, s0-s11}, -112
+       cm.push {ra, s0-s11}, -128
+       cm.push {ra, s0-s11}, -144
+       cm.push {ra, s0-s11}, -160
+       # pop
+       # abi names
+       cm.pop {ra}, 64
+       cm.pop {ra, s0}, 64
+       cm.pop {ra, s0-s1}, 64
+       cm.pop {ra, s0-s2}, 64
+       cm.pop {ra, s0-s8}, 112
+       cm.pop {ra, s0-s9}, 112
+       cm.pop {ra, s0-s11}, 112
+       # numeric names
+       cm.pop {x1}, 64
+       cm.pop {x1, x8}, 64
+       cm.pop {x1, x8-x9}, 64
+       cm.pop {x1, x8-x9, x18}, 64
+       cm.pop {x1, x8-x9, x18-x24}, 112
+       cm.pop {x1, x8-x9, x18-x25}, 112
+       cm.pop {x1, x8-x9, x18-x27}, 112
+       # spimm
+       cm.pop {ra}, 16
+       cm.pop {ra}, 32
+       cm.pop {ra}, 64
+       cm.pop {ra, s0-s2}, 32
+       cm.pop {ra, s0-s2}, 64
+       cm.pop {ra, s0-s2}, 80
+       cm.pop {ra, s0-s3}, 48
+       cm.pop {ra, s0-s3}, 64
+       cm.pop {ra, s0-s3}, 96
+       cm.pop {ra, s0-s6}, 64
+       cm.pop {ra, s0-s6}, 80
+       cm.pop {ra, s0-s6}, 112
+       cm.pop {ra, s0-s7}, 80
+       cm.pop {ra, s0-s7}, 96
+       cm.pop {ra, s0-s7}, 128
+       cm.pop {ra, s0-s9}, 96
+       cm.pop {ra, s0-s9}, 112
+       cm.pop {ra, s0-s9}, 144
+       cm.pop {ra, s0-s11}, 112
+       cm.pop {ra, s0-s11}, 128
+       cm.pop {ra, s0-s11}, 144
+       cm.pop {ra, s0-s11}, 160
+       # popret
+       # abi names
+       cm.popret {ra}, 64
+       cm.popret {ra, s0}, 64
+       cm.popret {ra, s0-s1}, 64
+       cm.popret {ra, s0-s2}, 64
+       cm.popret {ra, s0-s8}, 112
+       cm.popret {ra, s0-s9}, 112
+       cm.popret {ra, s0-s11}, 112
+       # numeric names
+       cm.popret {x1}, 64
+       cm.popret {x1, x8}, 64
+       cm.popret {x1, x8-x9}, 64
+       cm.popret {x1, x8-x9, x18}, 64
+       cm.popret {x1, x8-x9, x18-x24}, 112
+       cm.popret {x1, x8-x9, x18-x25}, 112
+       cm.popret {x1, x8-x9, x18-x27}, 112
+       # spimm
+       cm.popret {ra}, 16
+       cm.popret {ra}, 32
+       cm.popret {ra}, 64
+       cm.popret {ra, s0-s2}, 32
+       cm.popret {ra, s0-s2}, 64
+       cm.popret {ra, s0-s2}, 80
+       cm.popret {ra, s0-s3}, 48
+       cm.popret {ra, s0-s3}, 64
+       cm.popret {ra, s0-s3}, 96
+       cm.popret {ra, s0-s6}, 64
+       cm.popret {ra, s0-s6}, 80
+       cm.popret {ra, s0-s6}, 112
+       cm.popret {ra, s0-s7}, 80
+       cm.popret {ra, s0-s7}, 96
+       cm.popret {ra, s0-s7}, 128
+       cm.popret {ra, s0-s9}, 96
+       cm.popret {ra, s0-s9}, 112
+       cm.popret {ra, s0-s9}, 144
+       cm.popret {ra, s0-s11}, 112
+       cm.popret {ra, s0-s11}, 128
+       cm.popret {ra, s0-s11}, 144
+       cm.popret {ra, s0-s11}, 160
+       # popretz
+       # abi names
+       cm.popretz {ra}, 64
+       cm.popretz {ra, s0}, 64
+       cm.popretz {ra, s0-s1}, 64
+       cm.popretz {ra, s0-s2}, 64
+       cm.popretz {ra, s0-s8}, 112
+       cm.popretz {ra, s0-s9}, 112
+       cm.popretz {ra, s0-s11}, 112
+       # numeric names
+       cm.popretz {x1}, 64
+       cm.popretz {x1, x8}, 64
+       cm.popretz {x1, x8-x9}, 64
+       cm.popretz {x1, x8-x9, x18}, 64
+       cm.popretz {x1, x8-x9, x18-x24}, 112
+       cm.popretz {x1, x8-x9, x18-x25}, 112
+       cm.popretz {x1, x8-x9, x18-x27}, 112
+       # spimm
+       cm.popretz {ra}, 16
+       cm.popretz {ra}, 32
+       cm.popretz {ra}, 64
+       cm.popretz {ra, s0-s2}, 32
+       cm.popretz {ra, s0-s2}, 64
+       cm.popretz {ra, s0-s2}, 80
+       cm.popretz {ra, s0-s3}, 48
+       cm.popretz {ra, s0-s3}, 64
+       cm.popretz {ra, s0-s3}, 96
+       cm.popretz {ra, s0-s6}, 64
+       cm.popretz {ra, s0-s6}, 80
+       cm.popretz {ra, s0-s6}, 112
+       cm.popretz {ra, s0-s7}, 80
+       cm.popretz {ra, s0-s7}, 96
+       cm.popretz {ra, s0-s7}, 128
+       cm.popretz {ra, s0-s9}, 96
+       cm.popretz {ra, s0-s9}, 112
+       cm.popretz {ra, s0-s9}, 144
+       cm.popretz {ra, s0-s11}, 112
+       cm.popretz {ra, s0-s11}, 128
+       cm.popretz {ra, s0-s11}, 144
+       cm.popretz {ra, s0-s11}, 160

diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 1459ef231ddcf078675dc21011ffa7f655adbf92..ae14e14d42797b02a0e7ea822ccd812408fdcd5a 100644 (file)
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2271,6 +2271,15 @@
 #define MASK_C_NOT 0xfc7f
 #define MATCH_C_MUL 0x9c41
 #define MASK_C_MUL 0xfc63
+/* Zcmp instructions.  */
+#define MATCH_CM_PUSH 0xb802
+#define MASK_CM_PUSH 0xff03
+#define MATCH_CM_POP 0xba02
+#define MASK_CM_POP 0xff03
+#define MATCH_CM_POPRET 0xbe02
+#define MASK_CM_POPRET 0xff03
+#define MATCH_CM_POPRETZ 0xbc02
+#define MASK_CM_POPRETZ 0xff03
 /* Svinval instruction.  */
 #define MATCH_SINVAL_VMA 0x16000073
 #define MASK_SINVAL_VMA 0xfe007fff
@@ -3964,6 +3973,11 @@ DECLARE_INSN(c_lhu, MATCH_C_LHU, MASK_C_LHU)
 DECLARE_INSN(c_lh, MATCH_C_LH, MASK_C_LH)
 DECLARE_INSN(c_sb, MATCH_C_SB, MASK_C_SB)
 DECLARE_INSN(c_sh, MATCH_C_SH, MASK_C_SH)
+/* Zcmp instructions.  */
+DECLARE_INSN(cm_push, MATCH_CM_PUSH, MASK_CM_PUSH)
+DECLARE_INSN(cm_pop, MATCH_CM_POP, MASK_CM_POP)
+DECLARE_INSN(cm_popret, MATCH_CM_POPRET, MASK_CM_POPRET)
+DECLARE_INSN(cm_popretz, MATCH_CM_POPRETZ, MASK_CM_POPRETZ)
 /* Vendor-specific (T-Head) XTheadBa instructions.  */
 DECLARE_INSN(th_addsl, MATCH_TH_ADDSL, MASK_TH_ADDSL)
 /* Vendor-specific (T-Head) XTheadBb instructions.  */

diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 3245873aa6db855c4e776654c8999d300cdc64b3..d967b78f70630e5e23b8ec6c48dec69097e205d9 100644 (file)
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -112,6 +112,8 @@ static inline unsigned int riscv_insn_length (insn_t insn)
   (RV_X(x, 6, 1) | (RV_X(x, 5, 1) << 1))
 #define EXTRACT_ZCB_HALFWORD_UIMM(x) \
   (RV_X(x, 5, 1) << 1)
+#define EXTRACT_ZCMP_SPIMM(x) \
+  (RV_X(x, 2, 2) << 4)
 /* Vendor-specific (CORE-V) extract macros.  */
 #define EXTRACT_CV_IS2_UIMM5(x) \
   (RV_X(x, 20, 5))
@@ -168,6 +170,8 @@ static inline unsigned int riscv_insn_length (insn_t insn)
   ((RV_X(x, 0, 1) << 6) | (RV_X(x, 1, 1) << 5))
 #define ENCODE_ZCB_HALFWORD_UIMM(x) \
   (RV_X(x, 1, 1) << 5)
+#define ENCODE_ZCMP_SPIMM(x) \
+  (RV_X(x, 4, 2) << 2)
 /* Vendor-specific (CORE-V) encode macros.  */
 #define ENCODE_CV_IS2_UIMM5(x) \
   (RV_X(x, 0, 5) << 20)
@@ -200,6 +204,7 @@ static inline unsigned int riscv_insn_length (insn_t insn)
 #define VALID_RVV_VC_IMM(x) (EXTRACT_RVV_VC_IMM(ENCODE_RVV_VC_IMM(x)) == (x))
 #define VALID_ZCB_BYTE_UIMM(x) (EXTRACT_ZCB_BYTE_UIMM(ENCODE_ZCB_BYTE_UIMM(x)) == (x))
 #define VALID_ZCB_HALFWORD_UIMM(x) (EXTRACT_ZCB_HALFWORD_UIMM(ENCODE_ZCB_HALFWORD_UIMM(x)) == (x))
+#define VALID_ZCMP_SPIMM(x) (EXTRACT_ZCMP_SPIMM(ENCODE_ZCMP_SPIMM(x)) == (x))
 
 #define RISCV_RTYPE(insn, rd, rs1, rs2) \
   ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2))
@@ -337,6 +342,11 @@ static inline unsigned int riscv_insn_length (insn_t insn)
 #define OP_MASK_XTHEADVTYPE_RES        0xf
 #define OP_SH_XTHEADVTYPE_RES  7
 
+/* Zc fields.  */
+#define OP_MASK_REG_LIST       0xf
+#define OP_SH_REG_LIST         4
+#define ZCMP_SP_ALIGNMENT      16
+
 #define NVECR 32
 #define NVECM 1
 
@@ -355,6 +365,11 @@ static inline unsigned int riscv_insn_length (insn_t insn)
 #define X_T0 5
 #define X_T1 6
 #define X_T2 7
+#define X_S0 8
+#define X_S1 9
+#define X_S2 18
+#define X_S10 26
+#define X_S11 27
 #define X_T3 28
 
 #define NGPR 32
@@ -464,6 +479,7 @@ enum riscv_insn_class
   INSN_CLASS_ZCB_AND_ZBA,
   INSN_CLASS_ZCB_AND_ZBB,
   INSN_CLASS_ZCB_AND_ZMMUL,
+  INSN_CLASS_ZCMP,
   INSN_CLASS_SVINVAL,
   INSN_CLASS_ZICBOM,
   INSN_CLASS_ZICBOP,
@@ -613,4 +629,6 @@ extern const float riscv_fli_numval[32];
 extern const struct riscv_opcode riscv_opcodes[];
 extern const struct riscv_opcode riscv_insn_types[];
 
+extern unsigned int riscv_get_sp_base (insn_t, unsigned int);
+
 #endif /* _RISCV_H_ */

diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index 3019b9a5130f2f8e877026e3a8217f382ed93743..684098d386a83b7aa00d2a21683014b704f97039 100644 (file)
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -215,6 +215,48 @@ maybe_print_address (struct riscv_private_data *pd, int base_reg, int offset,
     pd->print_addr = (bfd_vma)(uint32_t)pd->print_addr;
 }
 
+/* Get Zcmp reg_list field.  */
+
+static void
+print_reg_list (disassemble_info *info, insn_t l)
+{
+  bool numeric = riscv_gpr_names == riscv_gpr_names_numeric;
+  unsigned reg_list = (int)EXTRACT_OPERAND (REG_LIST, l);
+  unsigned r_start = numeric ? X_S2 : X_S0;
+  info->fprintf_func (info->stream, "%s", riscv_gpr_names[X_RA]);
+
+  if (reg_list == 5)
+    info->fprintf_func (info->stream, ",%s",
+                       riscv_gpr_names[X_S0]);
+  else if (reg_list == 6 || (numeric && reg_list > 6))
+    info->fprintf_func (info->stream, ",%s-%s",
+                       riscv_gpr_names[X_S0],
+                       riscv_gpr_names[X_S1]);
+  if (reg_list == 15)
+    info->fprintf_func (info->stream, ",%s-%s",
+                       riscv_gpr_names[r_start],
+                       riscv_gpr_names[X_S11]);
+  else if (reg_list == 7 && numeric)
+    info->fprintf_func (info->stream, ",%s",
+                       riscv_gpr_names[X_S2]);
+  else if (reg_list > 6)
+    info->fprintf_func (info->stream, ",%s-%s",
+                       riscv_gpr_names[r_start],
+                       riscv_gpr_names[reg_list + 11]);
+}
+
+/* Get Zcmp sp adjustment immediate.  */
+
+static int
+riscv_get_spimm (insn_t l)
+{
+  int spimm = riscv_get_sp_base(l, *riscv_rps_dis.xlen);
+  spimm += EXTRACT_ZCMP_SPIMM (l);
+  if (((l ^ MATCH_CM_PUSH) & MASK_CM_PUSH) == 0)
+    spimm *= -1;
+  return spimm;
+}
+
 /* Print insn arguments for 32/64-bit code.  */
 
 static void
@@ -420,6 +462,8 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
        case ')':
        case '[':
        case ']':
+       case '{':
+       case '}':
          print (info->stream, dis_style_text, "%c", *oparg);
          break;
 
@@ -634,6 +678,13 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
                  print (info->stream, dis_style_immediate, "%d",
                         (int)EXTRACT_ZCB_HALFWORD_UIMM (l));
                  break;
+               case 'r':
+                 print_reg_list (info, l);
+                 break;
+               case 'p':
+                 print (info->stream, dis_style_immediate, "%d",
+                        riscv_get_spimm (l));
+                 break;
                default:
                  goto undefined_modifier;
                }

diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index daa888de8ac9e0168f37b30711025a4c506e910b..38a4624da7eb8a00b8a109ad85237b432d636ed3 100644 (file)
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -143,6 +143,20 @@ const float riscv_fli_numval[32] =
   0x1p+3, 0x1p+4, 0x1p+7, 0x1p+8, 0x1p+15, 0x1p+16, 0x0p+0, 0x0p+0
 };
 
+/* Get sp base adjustment.  */
+
+unsigned int
+riscv_get_sp_base (insn_t opcode, unsigned int xlen)
+{
+  unsigned reg_size = xlen / 8;
+  unsigned reg_list = EXTRACT_BITS (opcode, OP_MASK_REG_LIST, OP_SH_REG_LIST);
+  unsigned min_sp_adj = (reg_list - 3) * reg_size
+                       + (reg_list == 15 ? reg_size : 0);
+  return (((min_sp_adj / ZCMP_SP_ALIGNMENT)
+          + (min_sp_adj % ZCMP_SP_ALIGNMENT != 0))
+         * ZCMP_SP_ALIGNMENT);
+}
+
 #define MASK_RS1 (OP_MASK_RS1 << OP_SH_RS1)
 #define MASK_RS2 (OP_MASK_RS2 << OP_SH_RS2)
 #define MASK_RD (OP_MASK_RD << OP_SH_RD)
@@ -2068,6 +2082,12 @@ const struct riscv_opcode riscv_opcodes[] =
 {"c.zext.b",   0, INSN_CLASS_ZCB, "Cs",  MATCH_C_ZEXT_B, MASK_C_ZEXT_B, match_opcode, 0 },
 {"c.sext.w",  64, INSN_CLASS_ZCB, "d",  MATCH_C_ADDIW, MASK_C_ADDIW|MASK_RVC_IMM, match_rd_nonzero, INSN_ALIAS },
 
+/* Zcmp instructions.  */
+{"cm.push",    0,  INSN_CLASS_ZCMP, "{Wcr},Wcp",  MATCH_CM_PUSH, MASK_CM_PUSH, match_opcode, 0 },
+{"cm.pop",     0,  INSN_CLASS_ZCMP, "{Wcr},Wcp",  MATCH_CM_POP, MASK_CM_POP, match_opcode, 0 },
+{"cm.popret",  0,  INSN_CLASS_ZCMP, "{Wcr},Wcp",  MATCH_CM_POPRET, MASK_CM_POPRET, match_opcode, 0 },
+{"cm.popretz", 0,  INSN_CLASS_ZCMP, "{Wcr},Wcp",  MATCH_CM_POPRETZ, MASK_CM_POPRETZ, match_opcode, 0 },
+
 /* Supervisor instructions.  */
 {"csrr",       0, INSN_CLASS_ZICSR, "d,E",   MATCH_CSRRS, MASK_CSRRS|MASK_RS1, match_opcode, INSN_ALIAS },
 {"csrwi",      0, INSN_CLASS_ZICSR, "E,Z",   MATCH_CSRRWI, MASK_CSRRWI|MASK_RD, match_opcode, INSN_ALIAS },