drm/amd/amdgpu: fix the HDP LS/DS/SD programming

confirmed that IPH_MEM_POWER_CTRL_EN and RC_MEM_POWER_CTRL_EN
have to be set for SRAM LS/DS/SD

Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index 5d1c2eba34129986edb7cf6977436f09a9b7b910..081fde347dd49936e7d2c6428448ea13f7e271ca 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -889,6 +889,16 @@ static void nv_update_hdp_mem_power_gating(struct amdgpu_device *adev,
                                                 RC_MEM_POWER_DS_EN, enable);
        }
 
+       /* confirmed that IPH_MEM_POWER_CTRL_EN and RC_MEM_POWER_CTRL_EN have to
+        * be set for SRAM LS/DS/SD */
+       if (adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | AMD_CG_SUPPORT_HDP_DS |
+                                                       AMD_CG_SUPPORT_HDP_SD)) {
+               hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
+                                               IPH_MEM_POWER_CTRL_EN, 1);
+               hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
+                                               RC_MEM_POWER_CTRL_EN, 1);
+       }
+
        WREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl);
 
        /* restore IPH & RC clock override after clock/power mode changing */