arm64: dts: qcom: sdx75: Add AOSS node

Add AOSS channel devicetree node for Qcom's SDX75 SoC.

Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
Link: https://lore.kernel.org/r/20240426055326.3141727-7-quic_rohiagar@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/sdx75.dtsi b/arch/arm64/boot/dts/qcom/sdx75.dtsi
index 8f71efa9f9380a1d5a70d4450e9d89ece36c0cfa..d433ed196db69a81eed7f5033d61cc68bd0c7622 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sdx75.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdx75.dtsi
@@ -11,6 +11,7 @@
 #include <dt-bindings/interconnect/qcom,icc.h>
 #include <dt-bindings/interconnect/qcom,sdx75.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/mailbox/qcom-ipcc.h>
 #include <dt-bindings/power/qcom,rpmhpd.h>
 #include <dt-bindings/power/qcom-rpmpd.h>
 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
@@ -641,6 +642,17 @@
                        interrupt-controller;
                };
 
+               aoss_qmp: power-controller@c310000 {
+                       compatible = "qcom,sdx75-aoss-qmp", "qcom,aoss-qmp";
+                       reg = <0 0x0c310000 0 0x1000>;
+                       interrupt-parent = <&ipcc>;
+                       interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
+                                                    IRQ_TYPE_EDGE_RISING>;
+                       mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
+
+                       #clock-cells = <0>;
+               };
+
                spmi_bus: spmi@c400000 {
                        compatible = "qcom,spmi-pmic-arb";
                        reg = <0x0 0x0c400000 0x0 0x3000>,