]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
drm/xe/ptl: Apply Wa_14023061436
authorNirmoy Das <nirmoy.das@intel.com>
Wed, 8 Jan 2025 14:13:23 +0000 (15:13 +0100)
committerNirmoy Das <nirmoy.das@intel.com>
Mon, 13 Jan 2025 11:01:44 +0000 (12:01 +0100)
Enable WMTP for the BTD kernel to address Wa14023061436 by setting the
proper TDL Chicken Bit.

v2: Apply it on engine_was[] as this register is not part of LRC(Matt)
    Apply it for first_render_or_compute in case this gets extended to
    compute only platforms(Matt).

Cc: Gustavo Sousa <gustavo.sousa@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250108141323.311601-1-nirmoy.das@intel.com
Signed-off-by: Nirmoy Das <nirmoy.das@intel.com>
drivers/gpu/drm/xe/regs/xe_gt_regs.h
drivers/gpu/drm/xe/xe_wa.c

index 162f18e975dae4c3115959a5e21c1abcee1c5089..b4283ac030f41fb5b42a2b0df48faec1b791e45c 100644 (file)
 #define   LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK       REG_GENMASK(13, 11)
 #define   DIS_ATOMIC_CHAINING_TYPED_WRITES     REG_BIT(3)
 
+#define TDL_CHICKEN                            XE_REG_MCR(0xe5f4, XE_REG_OPTION_MASKED)
+#define   QID_WAIT_FOR_THREAD_NOT_RUN_DISABLE  REG_BIT(12)
+
 #define LSC_CHICKEN_BIT_0                      XE_REG_MCR(0xe7c8)
 #define   DISABLE_D8_D16_COASLESCE             REG_BIT(30)
 #define   WR_REQ_CHAINING_DIS                  REG_BIT(26)
index 570fe03764025c741240b7838b34dd98ccfd6b1b..744dba4fdb58bb4a3d036e868c70bbdb5bd3c926 100644 (file)
@@ -613,6 +613,11 @@ static const struct xe_rtp_entry_sr engine_was[] = {
          XE_RTP_ACTIONS(FIELD_SET(SAMPLER_MODE, SMP_WAIT_FETCH_MERGING_COUNTER,
                                   SMP_FORCE_128B_OVERFETCH))
        },
+       { XE_RTP_NAME("14023061436"),
+         XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3001),
+                      FUNC(xe_rtp_match_first_render_or_compute)),
+         XE_RTP_ACTIONS(SET(TDL_CHICKEN, QID_WAIT_FOR_THREAD_NOT_RUN_DISABLE))
+       },
 
        {}
 };