+2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
+
+ * reloc.c: Add MORELLO_ADR_HI20_PCREL,
+ MORELLO_ADR_HI20_NC_PCREL and MORELLO_ADR_GOT_PAGE.
+ * elfnn-aarch64.c (elfNN_aarch64_howto_table): Likewise.
+ (aarch64_reloc_got_type): Add MORELLO_ADR_GOT_PAGE.
+ (_bfd_aarch64_erratum_843419_branch_to_stub): Add C64 argument
+ to _bfd_aarch64_reencode_adr_imm.
+ (elfNN_aarch64_final_link_relocate,
+ elfNN_aarch64_check_relocs): Add MORELLO_ADR_GOT_PAGE,
+ MORELLO_ADR_HI20_PCREL and MORELLO_ADR_HI20_NC_PCREL.
+ * elfxx-aarch64.c (_bfd_aarch64_reencode_adr_imm): Add C64
+ argument.
+ (_bfd_aarch64_elf_put_addend): Adjust callers.
+ * elfxx-aarch64.h (_bfd_aarch64_reencode_adr_imm): Add C64
+ argument.
+ * libbfd.h (bfd_reloc_code_real_names): Add
+ MORELLO_ADR_GOT_PAGE, MORELLO_ADR_HI20_PCREL and
+ MORELLO_ADR_HI20_NC_PCREL.
+ * bfd-in2.h: Regenerate.
+
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* elfnn-aarch64.c (elfNN_aarch64_howto_table): Add
instruction, giving a 21 bit signed byte offset. */
BFD_RELOC_AARCH64_LD_LO19_PCREL,
+/* Morello ADRP instruction, with bits 12 to 31 of a pc-relative page
+offset, giving a 4KB aligned page base address. */
+ BFD_RELOC_MORELLO_ADR_HI20_PCREL,
+
+/* Morello ADRP instruction, with bits 12 to 31 of a pc-relative page
+offset, giving a 4KB aligned page base address, but with no overflow
+checking. */
+ BFD_RELOC_MORELLO_ADR_HI20_NC_PCREL,
+
/* AArch64 ADR instruction, holding a simple 21 bit pc-relative byte offset. */
BFD_RELOC_AARCH64_ADR_LO21_PCREL,
conjunction with BFD_RELOC_AARCH64_LD64_GOT_LO12_NC. */
BFD_RELOC_AARCH64_ADR_GOT_PAGE,
+/* Get to the page base of the global offset table entry for a symbol as
+part of an ADRP instruction using a 20 bit PC relative value.Used in
+conjunction with BFD_RELOC_MORELLO_LD128_GOT_LO12_NC. */
+ BFD_RELOC_MORELLO_ADR_GOT_PAGE,
+
/* Unsigned 12 bit byte offset for 64 bit load/store from the page of
the GOT entry for this symbol. Used in conjunction with
BFD_RELOC_AARCH64_ADR_GOT_PAGE. Valid in LP64 ABI only. */
0x7ffff, /* dst_mask */
TRUE), /* pcrel_offset */
+ /* C64 ADRP: ((PG(S+A)-PG(P)) >> 12) & 0xfffff */
+ HOWTO64 (MORELLO_R (ADR_PREL_PG_HI20), /* type */
+ 12, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 20, /* bitsize */
+ TRUE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_signed, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ MORELLO_R_STR (ADR_PREL_PG_HI20), /* name */
+ FALSE, /* partial_inplace */
+ 0xfffff, /* src_mask */
+ 0xfffff, /* dst_mask */
+ TRUE), /* pcrel_offset */
+
+ /* C64 ADRP: ((PG(S+A)-PG(P)) >> 12) & 0xfffff [no overflow check] */
+ HOWTO64 (MORELLO_R (ADR_PREL_PG_HI20_NC), /* type */
+ 12, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 20, /* bitsize */
+ TRUE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ MORELLO_R_STR (ADR_PREL_PG_HI20_NC), /* name */
+ FALSE, /* partial_inplace */
+ 0xfffff, /* src_mask */
+ 0xfffff, /* dst_mask */
+ TRUE), /* pcrel_offset */
+
/* ADR: (S+A-P) & 0x1fffff */
HOWTO (AARCH64_R (ADR_PREL_LO21), /* type */
0, /* rightshift */
0x1fffff, /* dst_mask */
TRUE), /* pcrel_offset */
+ /* Get to the page for the GOT entry for the symbol
+ (G(S) - P) using a C64 ADRP instruction. */
+ HOWTO64 (MORELLO_R (ADR_GOT_PAGE), /* type */
+ 12, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 20, /* bitsize */
+ TRUE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ MORELLO_R_STR (ADR_GOT_PAGE), /* name */
+ FALSE, /* partial_inplace */
+ 0xfffff, /* src_mask */
+ 0xfffff, /* dst_mask */
+ TRUE), /* pcrel_offset */
+
/* LD64: GOT offset G(S) & 0xff8 */
HOWTO64 (AARCH64_R (LD64_GOT_LO12_NC), /* type */
3, /* rightshift */
switch (r_type)
{
case BFD_RELOC_AARCH64_ADR_GOT_PAGE:
+ case BFD_RELOC_MORELLO_ADR_GOT_PAGE:
case BFD_RELOC_AARCH64_GOT_LD_PREL19:
case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14:
case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC:
if ((htab->fix_erratum_843419 & ERRAT_ADR)
&& (imm >= AARCH64_MIN_ADRP_IMM && imm <= AARCH64_MAX_ADRP_IMM))
{
- insn = (_bfd_aarch64_reencode_adr_imm (AARCH64_ADR_OP, imm)
+ insn = (_bfd_aarch64_reencode_adr_imm (AARCH64_ADR_OP, imm, 0)
| AARCH64_RT (insn));
bfd_putl32 (insn, contents + stub_entry->adrp_offset);
/* Stub is not needed, don't map it out. */
return _bfd_aarch64_elf_put_addend (input_bfd, hit_data, bfd_r_type,
howto, value);
case BFD_RELOC_AARCH64_ADR_GOT_PAGE:
+ case BFD_RELOC_MORELLO_ADR_GOT_PAGE:
case BFD_RELOC_AARCH64_GOT_LD_PREL19:
case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14:
case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC:
return _bfd_aarch64_elf_put_addend (input_bfd, hit_data, bfd_r_type, howto, value);
case BFD_RELOC_AARCH64_ADD_LO12:
case BFD_RELOC_AARCH64_ADR_HI21_PCREL:
+ case BFD_RELOC_MORELLO_ADR_HI20_PCREL:
break;
}
}
case BFD_RELOC_AARCH64_64_PCREL:
case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL:
case BFD_RELOC_AARCH64_ADR_HI21_PCREL:
+ case BFD_RELOC_MORELLO_ADR_HI20_NC_PCREL:
+ case BFD_RELOC_MORELLO_ADR_HI20_PCREL:
case BFD_RELOC_AARCH64_ADR_LO21_PCREL:
case BFD_RELOC_AARCH64_LD_LO19_PCREL:
case BFD_RELOC_MORELLO_LD_LO17_PCREL:
break;
case BFD_RELOC_AARCH64_ADR_GOT_PAGE:
+ case BFD_RELOC_MORELLO_ADR_GOT_PAGE:
case BFD_RELOC_AARCH64_GOT_LD_PREL19:
case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14:
case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC:
case BFD_RELOC_AARCH64_ADD_LO12:
case BFD_RELOC_AARCH64_ADR_GOT_PAGE:
+ case BFD_RELOC_MORELLO_ADR_GOT_PAGE:
case BFD_RELOC_AARCH64_ADR_HI21_PCREL:
+ case BFD_RELOC_MORELLO_ADR_HI20_PCREL:
case BFD_RELOC_AARCH64_CALL26:
case BFD_RELOC_AARCH64_GOT_LD_PREL19:
case BFD_RELOC_AARCH64_JUMP26:
case BFD_RELOC_AARCH64_ADD_LO12:
case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL:
case BFD_RELOC_AARCH64_ADR_HI21_PCREL:
+ case BFD_RELOC_MORELLO_ADR_HI20_NC_PCREL:
+ case BFD_RELOC_MORELLO_ADR_HI20_PCREL:
case BFD_RELOC_AARCH64_ADR_LO21_PCREL:
case BFD_RELOC_AARCH64_LDST128_LO12:
case BFD_RELOC_AARCH64_LDST16_LO12:
/* RR: We probably want to keep a consistency check that
there are no dangling GOT_PAGE relocs. */
case BFD_RELOC_AARCH64_ADR_GOT_PAGE:
+ case BFD_RELOC_MORELLO_ADR_GOT_PAGE:
case BFD_RELOC_AARCH64_GOT_LD_PREL19:
case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14:
case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC:
/* Reencode the IMM field of ADR. */
uint32_t
-_bfd_aarch64_reencode_adr_imm (uint32_t insn, uint32_t imm)
+_bfd_aarch64_reencode_adr_imm (uint32_t insn, uint32_t imm, uint32_t c64)
{
- return (insn & ~((MASK (2) << 29) | (MASK (19) << 5)))
- | ((imm & MASK (2)) << 29) | ((imm & (MASK (19) << 2)) << 3);
+ return (insn & ~((MASK (2) << 29) | (MASK (19 - c64) << 5)))
+ | ((imm & MASK (2)) << 29) | ((imm & (MASK (19 - c64) << 2)) << 3);
}
/* Reencode the imm field of ld/st pos immediate. */
case BFD_RELOC_AARCH64_TLSDESC_CALL:
break;
+ case BFD_RELOC_MORELLO_ADR_GOT_PAGE:
+ case BFD_RELOC_MORELLO_ADR_HI20_NC_PCREL:
+ case BFD_RELOC_MORELLO_ADR_HI20_PCREL:
+ contents = _bfd_aarch64_reencode_adr_imm (contents, addend, 1);
+ break;
+
case BFD_RELOC_AARCH64_ADR_GOT_PAGE:
case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL:
case BFD_RELOC_AARCH64_ADR_HI21_PCREL:
case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21:
case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21:
case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21:
- contents = _bfd_aarch64_reencode_adr_imm (contents, addend);
+ contents = _bfd_aarch64_reencode_adr_imm (contents, addend, 0);
break;
case BFD_RELOC_AARCH64_ADD_LO12:
value = value + addend;
break;
+ case BFD_RELOC_MORELLO_ADR_HI20_NC_PCREL:
+ case BFD_RELOC_MORELLO_ADR_HI20_PCREL:
case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL:
case BFD_RELOC_AARCH64_ADR_HI21_PCREL:
if (weak_undef_p)
value = value + addend - place;
break;
+ case BFD_RELOC_MORELLO_ADR_GOT_PAGE:
case BFD_RELOC_AARCH64_ADR_GOT_PAGE:
case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21:
case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21:
_bfd_aarch64_decode_adrp_imm (uint32_t);
extern uint32_t
-_bfd_aarch64_reencode_adr_imm (uint32_t, uint32_t);
+_bfd_aarch64_reencode_adr_imm (uint32_t, uint32_t, uint32_t);
extern bfd_reloc_status_type
_bfd_aarch64_elf_put_addend (bfd *, bfd_byte *, bfd_reloc_code_real_type,
"BFD_RELOC_AARCH64_MOVW_PREL_G3",
"BFD_RELOC_MORELLO_LD_LO17_PCREL",
"BFD_RELOC_AARCH64_LD_LO19_PCREL",
+ "BFD_RELOC_MORELLO_ADR_HI20_PCREL",
+ "BFD_RELOC_MORELLO_ADR_HI20_NC_PCREL",
"BFD_RELOC_AARCH64_ADR_LO21_PCREL",
"BFD_RELOC_AARCH64_ADR_HI21_PCREL",
"BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL",
"BFD_RELOC_AARCH64_LDST128_LO12",
"BFD_RELOC_AARCH64_GOT_LD_PREL19",
"BFD_RELOC_AARCH64_ADR_GOT_PAGE",
+ "BFD_RELOC_MORELLO_ADR_GOT_PAGE",
"BFD_RELOC_AARCH64_LD64_GOT_LO12_NC",
"BFD_RELOC_AARCH64_LD32_GOT_LO12_NC",
"BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC",
AArch64 Load Literal instruction, holding a 19 bit pc-relative word
offset. The lowest two bits must be zero and are not stored in the
instruction, giving a 21 bit signed byte offset.
+ENUM
+ BFD_RELOC_MORELLO_ADR_HI20_PCREL
+ENUMDOC
+ Morello ADRP instruction, with bits 12 to 31 of a pc-relative page
+ offset, giving a 4KB aligned page base address.
+ENUM
+ BFD_RELOC_MORELLO_ADR_HI20_NC_PCREL
+ENUMDOC
+ Morello ADRP instruction, with bits 12 to 31 of a pc-relative page
+ offset, giving a 4KB aligned page base address, but with no overflow
+ checking.
ENUM
BFD_RELOC_AARCH64_ADR_LO21_PCREL
ENUMDOC
Get to the page base of the global offset table entry for a symbol as
part of an ADRP instruction using a 21 bit PC relative value.Used in
conjunction with BFD_RELOC_AARCH64_LD64_GOT_LO12_NC.
+ENUM
+ BFD_RELOC_MORELLO_ADR_GOT_PAGE
+ENUMDOC
+ Get to the page base of the global offset table entry for a symbol as
+ part of an ADRP instruction using a 20 bit PC relative value.Used in
+ conjunction with BFD_RELOC_MORELLO_LD128_GOT_LO12_NC.
ENUM
BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
ENUMDOC
+2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
+
+ * config/tc-aarch64.c (reloc_table_entry): Add c64_adrp_type
+ field.
+ (reloc_table): Adjust.
+ (parse_adrp): Adjust users.
+ (md_apply_fix): Add MORELLO_ADR_GOT_PAGE,
+ MORELLO_ADR_HI20_PCREL and MORELLO_ADR_HI20_NC_PCREL.
+ * testsuite/gas/aarch64/morello_insn-c64.d: Adjust test.
+
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* config/tc-aarch64.c (process_omitted_operand,
int pc_rel;
bfd_reloc_code_real_type adr_type;
bfd_reloc_code_real_type adrp_type;
+ bfd_reloc_code_real_type c64_adrp_type;
bfd_reloc_code_real_type movw_type;
bfd_reloc_code_real_type add_type;
bfd_reloc_code_real_type ldst_type;
0, /* adr_type */
0,
0,
+ 0,
BFD_RELOC_AARCH64_ADD_LO12,
BFD_RELOC_AARCH64_LDST_LO12,
0},
{"pg_hi21", 1,
0, /* adr_type */
BFD_RELOC_AARCH64_ADR_HI21_PCREL,
+ BFD_RELOC_MORELLO_ADR_HI20_PCREL,
0,
0,
0,
0},
- /* Higher 21 bits of pc-relative page offset: ADRP, no check */
+ /* Higher 21 bits (20 bits for C64) of pc-relative page offset: ADRP, no
+ check */
{"pg_hi21_nc", 1,
0, /* adr_type */
BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL,
+ BFD_RELOC_MORELLO_ADR_HI20_NC_PCREL,
0,
0,
0,
{"abs_g0", 0,
0, /* adr_type */
0,
+ 0,
BFD_RELOC_AARCH64_MOVW_G0,
0,
0,
{"abs_g0_s", 0,
0, /* adr_type */
0,
+ 0,
BFD_RELOC_AARCH64_MOVW_G0_S,
0,
0,
{"abs_g0_nc", 0,
0, /* adr_type */
0,
+ 0,
BFD_RELOC_AARCH64_MOVW_G0_NC,
0,
0,
{"abs_g1", 0,
0, /* adr_type */
0,
+ 0,
BFD_RELOC_AARCH64_MOVW_G1,
0,
0,
{"abs_g1_s", 0,
0, /* adr_type */
0,
+ 0,
BFD_RELOC_AARCH64_MOVW_G1_S,
0,
0,
{"abs_g1_nc", 0,
0, /* adr_type */
0,
+ 0,
BFD_RELOC_AARCH64_MOVW_G1_NC,
0,
0,
{"abs_g2", 0,
0, /* adr_type */
0,
+ 0,
BFD_RELOC_AARCH64_MOVW_G2,
0,
0,
{"abs_g2_s", 0,
0, /* adr_type */
0,
+ 0,
BFD_RELOC_AARCH64_MOVW_G2_S,
0,
0,
{"abs_g2_nc", 0,
0, /* adr_type */
0,
+ 0,
BFD_RELOC_AARCH64_MOVW_G2_NC,
0,
0,
{"abs_g3", 0,
0, /* adr_type */
0,
+ 0,
BFD_RELOC_AARCH64_MOVW_G3,
0,
0,
{"prel_g0", 1,
0, /* adr_type */
0,
+ 0,
BFD_RELOC_AARCH64_MOVW_PREL_G0,
0,
0,
{"prel_g0_nc", 1,
0, /* adr_type */
0,
+ 0,
BFD_RELOC_AARCH64_MOVW_PREL_G0_NC,
0,
0,
{"prel_g1", 1,
0, /* adr_type */
0,
+ 0,
BFD_RELOC_AARCH64_MOVW_PREL_G1,
0,
0,
{"prel_g1_nc", 1,
0, /* adr_type */
0,
+ 0,
BFD_RELOC_AARCH64_MOVW_PREL_G1_NC,
0,
0,
{"prel_g2", 1,
0, /* adr_type */
0,
+ 0,
BFD_RELOC_AARCH64_MOVW_PREL_G2,
0,
0,
{"prel_g2_nc", 1,
0, /* adr_type */
0,
+ 0,
BFD_RELOC_AARCH64_MOVW_PREL_G2_NC,
0,
0,
{"prel_g3", 1,
0, /* adr_type */
0,
+ 0,
BFD_RELOC_AARCH64_MOVW_PREL_G3,
0,
0,
{"got", 1,
0, /* adr_type */
BFD_RELOC_AARCH64_ADR_GOT_PAGE,
+ BFD_RELOC_MORELLO_ADR_GOT_PAGE,
0,
0,
0,
0,
0,
0,
+ 0,
BFD_RELOC_AARCH64_LD_GOT_LO12_NC,
0},
{"gotoff_g0_nc", 0,
0, /* adr_type */
0,
+ 0,
BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC,
0,
0,
{"gotoff_g1", 0,
0, /* adr_type */
0,
+ 0,
BFD_RELOC_AARCH64_MOVW_GOTOFF_G1,
0,
0,
0,
0,
0,
+ 0,
BFD_RELOC_AARCH64_LD64_GOTOFF_LO15,
0},
{"gottprel_g0_nc", 0,
0, /* adr_type */
0,
+ 0,
BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC,
0,
0,
{"gottprel_g1", 0,
0, /* adr_type */
0,
+ 0,
BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1,
0,
0,
0,
0,
0,
+ 0,
0},
/* 12 bit offset into the page containing GOT TLS entry for a symbol */
0, /* adr_type */
0,
0,
+ 0,
BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC,
0,
0},
{"tlsgd_g0_nc", 0,
0, /* adr_type */
0,
+ 0,
BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC,
0,
0,
{"tlsgd_g1", 0,
0, /* adr_type */
0,
+ 0,
BFD_RELOC_AARCH64_TLSGD_MOVW_G1,
0,
0,
0,
0,
0,
+ 0,
BFD_RELOC_AARCH64_TLSDESC_LD_PREL19},
/* 12 bit offset into the page containing GOT TLS entry for a symbol */
0, /* adr_type */
0,
0,
+ 0,
BFD_RELOC_AARCH64_TLSDESC_ADD_LO12,
BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC,
0},
0,
0,
0,
+ 0,
0},
/* 12 bit offset into the page containing GOT TLS entry for a symbol */
0, /* adr_type */
0,
0,
+ 0,
BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC,
0,
0},
0, /* adr_type */
0,
0,
+ 0,
BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12,
BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12,
0},
0, /* adr_type */
0,
0,
+ 0,
BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC,
BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC,
0},
0, /* adr_type */
0,
0,
+ 0,
BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12,
0,
0},
{"dtprel_g0", 0,
0, /* adr_type */
0,
+ 0,
BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0,
0,
0,
{"dtprel_g0_nc", 0,
0, /* adr_type */
0,
+ 0,
BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC,
0,
0,
{"dtprel_g1", 0,
0, /* adr_type */
0,
+ 0,
BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1,
0,
0,
{"dtprel_g1_nc", 0,
0, /* adr_type */
0,
+ 0,
BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC,
0,
0,
{"dtprel_g2", 0,
0, /* adr_type */
0,
+ 0,
BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2,
0,
0,
{"tlsdesc_off_g0_nc", 0,
0, /* adr_type */
0,
+ 0,
BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC,
0,
0,
{"tlsdesc_off_g1", 0,
0, /* adr_type */
0,
+ 0,
BFD_RELOC_AARCH64_TLSDESC_OFF_G1,
0,
0,
0,
0,
0,
+ 0,
BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19},
/* 12 bit offset into the page containing GOT TLS entry for a symbol */
0,
0,
0,
+ 0,
BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC,
0},
0, /* adr_type */
0,
0,
+ 0,
BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12,
0,
0},
0, /* adr_type */
0,
0,
+ 0,
BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12,
BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12,
0},
0, /* adr_type */
0,
0,
+ 0,
BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12,
0,
0},
0, /* adr_type */
0,
0,
+ 0,
BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC,
BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC,
0},
{"tprel_g2", 0,
0, /* adr_type */
0,
+ 0,
BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2,
0,
0,
{"tprel_g1", 0,
0, /* adr_type */
0,
+ 0,
BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1,
0,
0,
{"tprel_g1_nc", 0,
0, /* adr_type */
0,
+ 0,
BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC,
0,
0,
{"tprel_g0", 0,
0, /* adr_type */
0,
+ 0,
BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0,
0,
0,
{"tprel_g0_nc", 0,
0, /* adr_type */
0,
+ 0,
BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC,
0,
0,
0,
0,
0,
+ 0,
BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15,
0},
0,
0,
0,
+ 0,
BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14,
0},
};
if (*p == ':')
{
struct reloc_table_entry *entry;
+ bfd_reloc_code_real_type adrp_type;
/* Try to parse a relocation. Anything else is an error. */
++p;
return FALSE;
}
- if (entry->adrp_type == 0)
+ adrp_type = (AARCH64_CPU_HAS_FEATURE (cpu_variant, AARCH64_FEATURE_C64)
+ ? entry->c64_adrp_type : entry->adrp_type);
+
+ if (adrp_type == 0)
{
set_syntax_error
(_("this relocation modifier is not allowed on this instruction"));
return FALSE;
}
- inst.reloc.type = entry->adrp_type;
+ inst.reloc.type = adrp_type;
}
else
- inst.reloc.type = BFD_RELOC_AARCH64_ADR_HI21_PCREL;
+ inst.reloc.type = (AARCH64_CPU_HAS_FEATURE (cpu_variant,
+ AARCH64_FEATURE_C64)
+ ? BFD_RELOC_MORELLO_ADR_HI20_PCREL
+ : BFD_RELOC_AARCH64_ADR_HI21_PCREL);
inst.reloc.pc_rel = 1;
case BFD_RELOC_AARCH64_ADD_LO12:
case BFD_RELOC_AARCH64_ADR_GOT_PAGE:
+ case BFD_RELOC_MORELLO_ADR_GOT_PAGE:
+ case BFD_RELOC_MORELLO_ADR_HI20_NC_PCREL:
+ case BFD_RELOC_MORELLO_ADR_HI20_PCREL:
case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL:
case BFD_RELOC_AARCH64_ADR_HI21_PCREL:
case BFD_RELOC_AARCH64_GOT_LD_PREL19:
case BFD_RELOC_AARCH64_ADD_LO12:
case BFD_RELOC_AARCH64_ADR_GOT_PAGE:
+ case BFD_RELOC_MORELLO_ADR_GOT_PAGE:
+ case BFD_RELOC_MORELLO_ADR_HI20_NC_PCREL:
+ case BFD_RELOC_MORELLO_ADR_HI20_PCREL:
case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL:
case BFD_RELOC_AARCH64_ADR_HI21_PCREL:
case BFD_RELOC_AARCH64_GOT_LD_PREL19:
.* <Label>:
.*: 10000000 adr c0, .* <Label>
.*: 90800000 adrp c0, .* <.*>
- .*: R_AARCH64_ADR_PREL_PG_HI21 .*
+ .*: R_MORELLO_ADR_PREL_PG_HI20 .*
.*: b0000000 adrdp c0, #0x1000
.*: 023fc135 add c21, c9, #0xff0
.*: 023ffd35 add c21, c9, #0xfff
+2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
+
+ * elf/aarch64.h: Add R_MORELLO_ADR_PREL_PG_HI20,
+ R_MORELLO_ADR_PREL_PG_HI20_NC and R_MORELLO_ADR_GOT_PAGE.
+
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* opcode/aarch64.h (aarch64_opnd): New operand Cat_SYS.
/* A64C LD-lit: ((S+A-P) >> 4) & 0x1ffff */
RELOC_NUMBER (R_MORELLO_LD_PREL_LO17, 57348)
+/* ADRP: ((PG(S+A)-PG(P)) >> 12) & 0xfffff */
+RELOC_NUMBER (R_MORELLO_ADR_PREL_PG_HI20, 57349)
+
+/* ADRP: ((PG(S+A)-PG(P)) >> 12) & 0xfffff */
+RELOC_NUMBER (R_MORELLO_ADR_PREL_PG_HI20_NC, 57350)
+
+RELOC_NUMBER (R_MORELLO_ADR_GOT_PAGE, 57351)
+
END_RELOC_NUMBERS (R_AARCH64_end)
enum aarch64_st_branch_type
projects / thirdparty / binutils-gdb.git / commitdiff
